* [U-Boot] [PATCH v3] t2080qds/ddr: update ddr parameters
@ 2013-12-12 7:10 Shengzhou Liu
2014-01-02 21:58 ` York Sun
0 siblings, 1 reply; 4+ messages in thread
From: Shengzhou Liu @ 2013-12-12 7:10 UTC (permalink / raw)
To: u-boot
- Optimize UDIMM parameters for whole range from 1500MT/s to 2140MT/s.
- Remove unused patameters: 'cpo', 'wrdata delay', '2T',
which are unrelated to DDR3/3L.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
---
Against master branch of git://git.denx.de/u-boot-mpc85xx.git
v3: remain old RDIMM code without updating for now.
v2: throw an error in case of RDIMM.
board/freescale/t2080qds/ddr.c | 11 ++-----
board/freescale/t2080qds/ddr.h | 65 +++++++++++++++++-------------------------
2 files changed, 28 insertions(+), 48 deletions(-)
diff --git a/board/freescale/t2080qds/ddr.c b/board/freescale/t2080qds/ddr.c
index 5db5d21..4a4d570 100644
--- a/board/freescale/t2080qds/ddr.c
+++ b/board/freescale/t2080qds/ddr.c
@@ -24,7 +24,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
- if (ctrl_num > 2) {
+ if (ctrl_num > 1) {
printf("Not supported controller number %d\n", ctrl_num);
return;
}
@@ -40,8 +40,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
else
pbsp = udimms[0];
-
- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
@@ -49,9 +48,6 @@ void fsl_ddr_board_options(memctl_options_t *popts,
if (pbsp->n_ranks == pdimm->n_ranks &&
(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
@@ -69,13 +65,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
printf("for data rate %lu MT/s\n", ddr_freq);
printf("Trying to use the highest speed (%u) parameters\n",
pbsp_highest->datarate_mhz_high);
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- popts->twot_en = pbsp_highest->force_2t;
} else {
panic("DIMM is not supported by this board");
}
diff --git a/board/freescale/t2080qds/ddr.h b/board/freescale/t2080qds/ddr.h
index 964eaad..5828596 100644
--- a/board/freescale/t2080qds/ddr.h
+++ b/board/freescale/t2080qds/ddr.h
@@ -14,9 +14,6 @@ struct board_specific_parameters {
u32 wrlvl_start;
u32 wrlvl_ctl_2;
u32 wrlvl_ctl_3;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
};
/*
@@ -28,58 +25,48 @@ struct board_specific_parameters {
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
- {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
- {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
- {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
- {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
- {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
- {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
- {1, 1800, 2, 5, 6, 0x06070709, 0x110a0b08, 0xff, 2, 0},
- {1, 1866, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0},
- {1, 1900, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0},
- {1, 2000, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0},
- {1, 2133, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0},
+ {2, 1500, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
+ {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
+ {2, 1700, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
+ {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
+ {2, 2140, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
+ {2, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b},
+ {1, 1500, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
+ {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
+ {1, 1700, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
+ {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
+ {1, 2140, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
+ {1, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b},
{}
};
static const struct board_specific_parameters rdimm0[] = {
/*
* memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
- {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0},
- {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
- {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
- {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
- {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
- {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ /* TODO: need tuning these parameters if RDIMM is used */
+ {4, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906},
+ {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
+ {2, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
+ {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
+ {1, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
+ {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07},
{}
};
-/*
- * The three slots have slightly different timing. The center values are good
- * for all slots. We use identical speed tables for them. In future use, if
- * DIMMs require separated tables, make more entries as needed.
- */
static const struct board_specific_parameters *udimms[] = {
udimm0,
};
-/*
- * The three slots have slightly different timing. See comments above.
- */
static const struct board_specific_parameters *rdimms[] = {
rdimm0,
};
-
-
#endif
--
1.8.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH v3] t2080qds/ddr: update ddr parameters
2013-12-12 7:10 Shengzhou Liu
@ 2014-01-02 21:58 ` York Sun
0 siblings, 0 replies; 4+ messages in thread
From: York Sun @ 2014-01-02 21:58 UTC (permalink / raw)
To: u-boot
On 12/11/2013 11:10 PM, Shengzhou Liu wrote:
> - Optimize UDIMM parameters for whole range from 1500MT/s to 2140MT/s.
> - Remove unused patameters: 'cpo', 'wrdata delay', '2T',
> which are unrelated to DDR3/3L.
>
> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
> ---
> Against master branch of git://git.denx.de/u-boot-mpc85xx.git
> v3: remain old RDIMM code without updating for now.
> v2: throw an error in case of RDIMM.
>
> board/freescale/t2080qds/ddr.c | 11 ++-----
> board/freescale/t2080qds/ddr.h | 65 +++++++++++++++++-------------------------
> 2 files changed, 28 insertions(+), 48 deletions(-)
>
> diff --git a/board/freescale/t2080qds/ddr.c b/board/freescale/t2080qds/ddr.c
> index 5db5d21..4a4d570 100644
> --- a/board/freescale/t2080qds/ddr.c
> +++ b/board/freescale/t2080qds/ddr.c
> @@ -24,7 +24,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
> const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
> ulong ddr_freq;
>
> - if (ctrl_num > 2) {
> + if (ctrl_num > 1) {
> printf("Not supported controller number %d\n", ctrl_num);
> return;
> }
> @@ -40,8 +40,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
> else
> pbsp = udimms[0];
>
> -
> - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
> + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
> * freqency and n_banks specified in board_specific_parameters table.
> */
> ddr_freq = get_ddr_freq(0) / 1000000;
> @@ -49,9 +48,6 @@ void fsl_ddr_board_options(memctl_options_t *popts,
> if (pbsp->n_ranks == pdimm->n_ranks &&
> (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
> if (ddr_freq <= pbsp->datarate_mhz_high) {
> - popts->cpo_override = pbsp->cpo;
> - popts->write_data_delay =
> - pbsp->write_data_delay;
> popts->clk_adjust = pbsp->clk_adjust;
> popts->wrlvl_start = pbsp->wrlvl_start;
> popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
> @@ -69,13 +65,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
> printf("for data rate %lu MT/s\n", ddr_freq);
> printf("Trying to use the highest speed (%u) parameters\n",
> pbsp_highest->datarate_mhz_high);
> - popts->cpo_override = pbsp_highest->cpo;
> - popts->write_data_delay = pbsp_highest->write_data_delay;
> popts->clk_adjust = pbsp_highest->clk_adjust;
> popts->wrlvl_start = pbsp_highest->wrlvl_start;
> popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
> popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
> - popts->twot_en = pbsp_highest->force_2t;
> } else {
> panic("DIMM is not supported by this board");
> }
> diff --git a/board/freescale/t2080qds/ddr.h b/board/freescale/t2080qds/ddr.h
> index 964eaad..5828596 100644
> --- a/board/freescale/t2080qds/ddr.h
> +++ b/board/freescale/t2080qds/ddr.h
> @@ -14,9 +14,6 @@ struct board_specific_parameters {
> u32 wrlvl_start;
> u32 wrlvl_ctl_2;
> u32 wrlvl_ctl_3;
> - u32 cpo;
> - u32 write_data_delay;
> - u32 force_2t;
> };
>
> /*
> @@ -28,58 +25,48 @@ struct board_specific_parameters {
> static const struct board_specific_parameters udimm0[] = {
> /*
> * memory controller 0
> - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
> - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
> + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
> + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
> */
> - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
> - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
> - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
> - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
> - {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
> - {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
> - {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
> - {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
> - {1, 1800, 2, 5, 6, 0x06070709, 0x110a0b08, 0xff, 2, 0},
> - {1, 1866, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0},
> - {1, 1900, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0},
> - {1, 2000, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0},
> - {1, 2133, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0},
> + {2, 1500, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
> + {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
> + {2, 1700, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
> + {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
> + {2, 2140, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
> + {2, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b},
> + {1, 1500, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
> + {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
> + {1, 1700, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
> + {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
> + {1, 2140, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
> + {1, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b},
Having two lines with same (ranks, hi mhz, rank GB) is wrong. clk adjust is the
value you want to look up from this table, not an index to search.
York
^ permalink raw reply [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH v3] t2080qds/ddr: update ddr parameters
@ 2014-01-13 5:01 Shengzhou Liu
2014-01-21 23:01 ` York Sun
0 siblings, 1 reply; 4+ messages in thread
From: Shengzhou Liu @ 2014-01-13 5:01 UTC (permalink / raw)
To: u-boot
- Optimize UDIMM parameters for whole range from 1500MT/s to 2140MT/s.
- Remove unused patameters: 'cpo', 'wrdata delay', '2T', which are
unrelated to DDR3/3L.
Tested with UDIMM 9JSF25672AZ-2G1K1 and verified speed 1200/1866/2133MT/s.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
---
v3: fix issue of two line with same parameters and add more commit description.
v2: rebase.
board/freescale/t2080qds/ddr.c | 12 ++------
board/freescale/t2080qds/ddr.h | 65 +++++++++++++++++-------------------------
2 files changed, 28 insertions(+), 49 deletions(-)
diff --git a/board/freescale/t2080qds/ddr.c b/board/freescale/t2080qds/ddr.c
index 5db5d21..ed1334d 100644
--- a/board/freescale/t2080qds/ddr.c
+++ b/board/freescale/t2080qds/ddr.c
@@ -24,7 +24,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
- if (ctrl_num > 2) {
+ if (ctrl_num > 1) {
printf("Not supported controller number %d\n", ctrl_num);
return;
}
@@ -40,8 +40,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
else
pbsp = udimms[0];
-
- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
@@ -49,14 +48,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
if (pbsp->n_ranks == pdimm->n_ranks &&
(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- popts->twot_en = pbsp->force_2t;
goto found;
}
pbsp_highest = pbsp;
@@ -69,13 +64,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
printf("for data rate %lu MT/s\n", ddr_freq);
printf("Trying to use the highest speed (%u) parameters\n",
pbsp_highest->datarate_mhz_high);
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- popts->twot_en = pbsp_highest->force_2t;
} else {
panic("DIMM is not supported by this board");
}
diff --git a/board/freescale/t2080qds/ddr.h b/board/freescale/t2080qds/ddr.h
index 964eaad..9fc879a 100644
--- a/board/freescale/t2080qds/ddr.h
+++ b/board/freescale/t2080qds/ddr.h
@@ -14,9 +14,6 @@ struct board_specific_parameters {
u32 wrlvl_start;
u32 wrlvl_ctl_2;
u32 wrlvl_ctl_3;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
};
/*
@@ -28,58 +25,48 @@ struct board_specific_parameters {
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
- {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
- {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
- {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
- {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
- {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
- {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
- {1, 1800, 2, 5, 6, 0x06070709, 0x110a0b08, 0xff, 2, 0},
- {1, 1866, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0},
- {1, 1900, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0},
- {1, 2000, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0},
- {1, 2133, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0},
+ {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
+ {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
+ {2, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
+ {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
+ {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
+ {2, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b},
+ {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
+ {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
+ {1, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
+ {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
+ {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
+ {1, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b},
{}
};
static const struct board_specific_parameters rdimm0[] = {
/*
* memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
- {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0},
- {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
- {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
- {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
- {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
- {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ /* TODO: need tuning these parameters if RDIMM is used */
+ {4, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906},
+ {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
+ {2, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
+ {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
+ {1, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
+ {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07},
{}
};
-/*
- * The three slots have slightly different timing. The center values are good
- * for all slots. We use identical speed tables for them. In future use, if
- * DIMMs require separated tables, make more entries as needed.
- */
static const struct board_specific_parameters *udimms[] = {
udimm0,
};
-/*
- * The three slots have slightly different timing. See comments above.
- */
static const struct board_specific_parameters *rdimms[] = {
rdimm0,
};
-
-
#endif
--
1.8.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH v3] t2080qds/ddr: update ddr parameters
2014-01-13 5:01 [U-Boot] [PATCH v3] t2080qds/ddr: update ddr parameters Shengzhou Liu
@ 2014-01-21 23:01 ` York Sun
0 siblings, 0 replies; 4+ messages in thread
From: York Sun @ 2014-01-21 23:01 UTC (permalink / raw)
To: u-boot
On 01/12/2014 09:01 PM, Shengzhou Liu wrote:
> - Optimize UDIMM parameters for whole range from 1500MT/s to 2140MT/s.
> - Remove unused patameters: 'cpo', 'wrdata delay', '2T', which are
> unrelated to DDR3/3L.
>
> Tested with UDIMM 9JSF25672AZ-2G1K1 and verified speed 1200/1866/2133MT/s.
>
> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
> ---
> v3: fix issue of two line with same parameters and add more commit description.
> v2: rebase.
Applied to u-boot-mpc85xx master branch. Awaiting upstream.
York
^ permalink raw reply [flat|nested] 4+ messages in thread
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