[U-Boot] [PATCH v3] net/designware: make driver compatible with data cache

[Stefan Roese <sr@denx.de>]

Hi Alexey,

On 22.01.2014 17:49, Alexey Brodkin wrote:
> From: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
>
> Up until now this driver only worked with data cache disabled.
> To make it work with enabled data cache following changes were required:
>
>   * Flush Tx/Rx buffer descriptors their modification
>   * Invalidate Tx/Rx buffer descriptors before reading its values
>   * Flush cache for data passed from CPU to GMAC
>   * Invalidate cache for data passed from GMAC to CPU
>
> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

A small nitpicking comment below.

> Cc: Joe Hershberger <joe.hershberger@ni.com>
> Cc: Vipin Kumar <vipin.kumar@st.com>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Mischa Jonker <mjonker@synopsys.com>
> Cc: Shiraz Hashim <shiraz.hashim@st.com>
> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
> Cc: Amit Virdi <amit.virdi@st.com>
> Cc: Sonic Zhang <sonic.zhang@analog.com>
>
> Compared to v2:
>   1. Removed trailing white space
> ---
>   drivers/net/designware.c | 53 +++++++++++++++++++++++++++++++++++++++++++++---
>   1 file changed, 50 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/designware.c b/drivers/net/designware.c
> index 22155b4..c0c8659 100644
> --- a/drivers/net/designware.c
> +++ b/drivers/net/designware.c
> @@ -51,6 +51,11 @@ static void tx_descs_init(struct eth_device *dev)
>   	/* Correcting the last pointer of the chain */
>   	desc_p->dmamac_next = &desc_table_p[0];
>
> +	/* Flush all Tx buffer descriptors at once */
> +	flush_dcache_range((unsigned int)priv->tx_mac_descrtable,
> +			   (unsigned int)priv->tx_mac_descrtable +
> +			   sizeof(priv->tx_mac_descrtable));
> +
>   	writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
>   }
>
> @@ -63,6 +68,15 @@ static void rx_descs_init(struct eth_device *dev)
>   	struct dmamacdescr *desc_p;
>   	u32 idx;
>
> +	/* Before passing buffers to GMAC we need to make sure zeros
> +	 * written there right after "priv" structure allocation were
> +	 * flushed into RAM.
> +	 * Otherwise there's a chance to get some of them flushed in RAM when
> +	 * GMAC is already pushing data to RAM via DMA. This way incoming from
> +	 * GMAC data will be corrupted. */

Please use this recommended multi-line comment style:

	/*
	 * Before ...
	 * ...
	 *
	 * ... will be corrupted.
	 */

Thanks,
Stefan