[U-Boot] [PATCH V2 03/13] ARM: tegra: enable PLLX only once it's been fully configured

Stephen Warren
2014-01-24T00:42:50Z

From: Stephen Warren <swarren@nvidia.com>

This programming sequence is correct per Jimmy Zhang, and makes sense
too!

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2: New patch, split out from the later Tegra124 changes.
---
arch/arm/cpu/arm720t/tegra-common/cpu.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index 03f67b163cc5..322ce10d6fe3 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -144,18 +144,23 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
reg |= (1 << PLL_DCCON_SHIFT);
writel(reg, &pll->pll_misc);

- /* Enable PLLX */
- reg = readl(&pll->pll_base);
- reg |= PLL_ENABLE_MASK;
-
/* Disable BYPASS */
+ reg = readl(&pll->pll_base);
reg &= ~PLL_BYPASS_MASK;
writel(reg, &pll->pll_base);
+ debug("pllx_set_rate: base = 0x%08X\n", reg);

/* Set lock_enable to PLLX_MISC */
reg = readl(&pll->pll_misc);
reg |= PLL_LOCK_ENABLE_MASK;
writel(reg, &pll->pll_misc);
+ debug("pllx_set_rate: misc = 0x%08X\n", reg);
+
+ /* Enable PLLX last, once it's all configured */
+ reg = readl(&pll->pll_base);
+ reg |= PLL_ENABLE_MASK;
+ writel(reg, &pll->pll_base);
+ debug("pllx_set_rate: base final = 0x%08X\n", reg);

return 0;
}
--
1.8.1.5