* [U-Boot] [PATCH v3] mx6: Enable L2 cache support
@ 2014-01-28 14:54 Fabio Estevam
2014-01-28 14:58 ` Stefano Babic
2014-01-28 16:53 ` Dirk Behme
0 siblings, 2 replies; 6+ messages in thread
From: Fabio Estevam @ 2014-01-28 14:54 UTC (permalink / raw)
To: u-boot
Add L2 cache support and enable it by default.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v2:
- Add L2_PL310_BASE definition in imx_regs.h
Changes since v1:
- Fx typo in commit log
arch/arm/cpu/armv7/mx6/soc.c | 20 ++++++++++++++++++++
arch/arm/include/asm/arch-mx6/imx-regs.h | 1 +
include/configs/mx6_common.h | 5 +++++
3 files changed, 26 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 0208cba..b84de87 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -8,6 +8,8 @@
*/
#include <common.h>
+#include <asm/armv7.h>
+#include <asm/pl310.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
@@ -336,3 +338,21 @@ void imx_setup_hdmi(void)
writel(reg, &mxc_ccm->chsccdr);
}
#endif
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define L2CACHE 1
+void v7_outer_cache_enable(void)
+{
+ struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+
+ setbits_le32(&pl310->pl310_ctrl, L2CACHE);
+
+}
+
+void v7_outer_cache_disable(void)
+{
+ struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+
+ clrbits_le32(&pl310->pl310_ctrl, L2CACHE);
+}
+#endif /* !CONFIG_SYS_L2CACHE_OFF */
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index f2ad6e9..c2d210a 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -53,6 +53,7 @@
#define GLOBAL_TIMER_BASE_ADDR 0x00A00200
#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
+#define L2_PL310_BASE 0x00A02000
#define GPV0_BASE_ADDR 0x00B00000
#define GPV1_BASE_ADDR 0x00C00000
#define PCIE_ARB_BASE_ADDR 0x01000000
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 514d634..63afa46 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -22,4 +22,9 @@
#define CONFIG_ARM_ERRATA_751472
#define CONFIG_BOARD_POSTCLK_INIT
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE L2_PL310_BASE
+#endif
+
#endif
--
1.8.1.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* [U-Boot] [PATCH v3] mx6: Enable L2 cache support
2014-01-28 14:54 [U-Boot] [PATCH v3] mx6: Enable L2 cache support Fabio Estevam
@ 2014-01-28 14:58 ` Stefano Babic
2014-01-28 16:53 ` Dirk Behme
1 sibling, 0 replies; 6+ messages in thread
From: Stefano Babic @ 2014-01-28 14:58 UTC (permalink / raw)
To: u-boot
On 28/01/2014 15:54, Fabio Estevam wrote:
> Add L2 cache support and enable it by default.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> Changes since v2:
> - Add L2_PL310_BASE definition in imx_regs.h
> Changes since v1:
> - Fx typo in commit log
>
> arch/arm/cpu/armv7/mx6/soc.c | 20 ++++++++++++++++++++
> arch/arm/include/asm/arch-mx6/imx-regs.h | 1 +
> include/configs/mx6_common.h | 5 +++++
> 3 files changed, 26 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index 0208cba..b84de87 100644
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -8,6 +8,8 @@
> */
>
> #include <common.h>
> +#include <asm/armv7.h>
> +#include <asm/pl310.h>
> #include <asm/errno.h>
> #include <asm/io.h>
> #include <asm/arch/imx-regs.h>
> @@ -336,3 +338,21 @@ void imx_setup_hdmi(void)
> writel(reg, &mxc_ccm->chsccdr);
> }
> #endif
> +
> +#ifndef CONFIG_SYS_L2CACHE_OFF
> +#define L2CACHE 1
> +void v7_outer_cache_enable(void)
> +{
> + struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
> +
> + setbits_le32(&pl310->pl310_ctrl, L2CACHE);
> +
> +}
> +
> +void v7_outer_cache_disable(void)
> +{
> + struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
> +
> + clrbits_le32(&pl310->pl310_ctrl, L2CACHE);
> +}
> +#endif /* !CONFIG_SYS_L2CACHE_OFF */
> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
> index f2ad6e9..c2d210a 100644
> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
> @@ -53,6 +53,7 @@
> #define GLOBAL_TIMER_BASE_ADDR 0x00A00200
> #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
> #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
> +#define L2_PL310_BASE 0x00A02000
> #define GPV0_BASE_ADDR 0x00B00000
> #define GPV1_BASE_ADDR 0x00C00000
> #define PCIE_ARB_BASE_ADDR 0x01000000
> diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
> index 514d634..63afa46 100644
> --- a/include/configs/mx6_common.h
> +++ b/include/configs/mx6_common.h
> @@ -22,4 +22,9 @@
> #define CONFIG_ARM_ERRATA_751472
> #define CONFIG_BOARD_POSTCLK_INIT
>
> +#ifndef CONFIG_SYS_L2CACHE_OFF
> +#define CONFIG_SYS_L2_PL310
> +#define CONFIG_SYS_PL310_BASE L2_PL310_BASE
> +#endif
> +
> #endif
>
Acked-by: Stefano Babic <sbabic@denx.de>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 6+ messages in thread* [U-Boot] [PATCH v3] mx6: Enable L2 cache support
2014-01-28 14:54 [U-Boot] [PATCH v3] mx6: Enable L2 cache support Fabio Estevam
2014-01-28 14:58 ` Stefano Babic
@ 2014-01-28 16:53 ` Dirk Behme
2014-01-28 19:12 ` Fabio Estevam
2014-01-29 12:47 ` Stefano Babic
1 sibling, 2 replies; 6+ messages in thread
From: Dirk Behme @ 2014-01-28 16:53 UTC (permalink / raw)
To: u-boot
Hi Fabio,
Am 28.01.2014 15:54, schrieb Fabio Estevam:
> Add L2 cache support and enable it by default.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> Changes since v2:
> - Add L2_PL310_BASE definition in imx_regs.h
> Changes since v1:
> - Fx typo in commit log
>
> arch/arm/cpu/armv7/mx6/soc.c | 20 ++++++++++++++++++++
> arch/arm/include/asm/arch-mx6/imx-regs.h | 1 +
> include/configs/mx6_common.h | 5 +++++
> 3 files changed, 26 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index 0208cba..b84de87 100644
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -8,6 +8,8 @@
> */
>
> #include <common.h>
> +#include <asm/armv7.h>
> +#include <asm/pl310.h>
> #include <asm/errno.h>
> #include <asm/io.h>
> #include <asm/arch/imx-regs.h>
> @@ -336,3 +338,21 @@ void imx_setup_hdmi(void)
> writel(reg, &mxc_ccm->chsccdr);
> }
> #endif
> +
> +#ifndef CONFIG_SYS_L2CACHE_OFF
> +#define L2CACHE 1
> +void v7_outer_cache_enable(void)
> +{
> + struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
> +
> + setbits_le32(&pl310->pl310_ctrl, L2CACHE);
> +
> +}
Just for better understanding: Do you want to keep this intentionally
simple? Or is there any special reason why you don't set additional
(performance) registers here? E.g. the L2 PREFETCH and POWER
registers, and the tag and data latency settings? Like done in the kernel.
Best regards
Dirk
^ permalink raw reply [flat|nested] 6+ messages in thread* [U-Boot] [PATCH v3] mx6: Enable L2 cache support
2014-01-28 16:53 ` Dirk Behme
@ 2014-01-28 19:12 ` Fabio Estevam
2014-01-29 12:47 ` Stefano Babic
1 sibling, 0 replies; 6+ messages in thread
From: Fabio Estevam @ 2014-01-28 19:12 UTC (permalink / raw)
To: u-boot
Hi Dirk,
On Tue, Jan 28, 2014 at 2:53 PM, Dirk Behme <dirk.behme@gmail.com> wrote:
> Just for better understanding: Do you want to keep this intentionally
> simple? Or is there any special reason why you don't set additional
> (performance) registers here? E.g. the L2 PREFETCH and POWER registers, and
> the tag and data latency settings? Like done in the kernel.
The idea was to keep it simple initially and then we can extend L2
support as needed.
Regards,
Fabio Estevam
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH v3] mx6: Enable L2 cache support
2014-01-28 16:53 ` Dirk Behme
2014-01-28 19:12 ` Fabio Estevam
@ 2014-01-29 12:47 ` Stefano Babic
2014-01-29 17:57 ` Fabio Estevam
1 sibling, 1 reply; 6+ messages in thread
From: Stefano Babic @ 2014-01-29 12:47 UTC (permalink / raw)
To: u-boot
Hi Dirk,
On 28/01/2014 17:53, Dirk Behme wrote:
>
> Just for better understanding: Do you want to keep this intentionally
> simple? Or is there any special reason why you don't set additional
> (performance) registers here? E.g. the L2 PREFETCH and POWER registers,
> and the tag and data latency settings? Like done in the kernel.
This is a good point ! If it is true that L2 PREFETCH is turned on in
mainline kernel, but it was *explicitely* turned off by Jason in FSL
Kernel with the patch with subject ENGR00278489 (ARM PL310 errata: 7522719).
It seems to me that Fabio has already applied Jason's patch - maybe
should we check as in FSL kernel which i.MX6 is running (DL and Solo are
not affected). Jason, can you a little explain this topic ? Was the
patch sent to Shaw, too (set in CC) ?
Thanks,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH v3] mx6: Enable L2 cache support
2014-01-29 12:47 ` Stefano Babic
@ 2014-01-29 17:57 ` Fabio Estevam
0 siblings, 0 replies; 6+ messages in thread
From: Fabio Estevam @ 2014-01-29 17:57 UTC (permalink / raw)
To: u-boot
Hi Stefano,
On Wed, Jan 29, 2014 at 10:47 AM, Stefano Babic <sbabic@denx.de> wrote:
> Hi Dirk,
>
> On 28/01/2014 17:53, Dirk Behme wrote:
>
>>
>> Just for better understanding: Do you want to keep this intentionally
>> simple? Or is there any special reason why you don't set additional
>> (performance) registers here? E.g. the L2 PREFETCH and POWER registers,
>> and the tag and data latency settings? Like done in the kernel.
>
> This is a good point ! If it is true that L2 PREFETCH is turned on in
> mainline kernel, but it was *explicitely* turned off by Jason in FSL
> Kernel with the patch with subject ENGR00278489 (ARM PL310 errata: 7522719).
Mainline kernel and recent FSL kernels (3.0.35 4.1.0 or 3.10.17) keep
L2 prefetch enabled.
Check this commit:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_3.0.35_4.1.0&id=517182a385808f60bf94e2361712d714f0a78a61
Regards,
Fabio Estevam
^ permalink raw reply [flat|nested] 6+ messages in thread
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2014-01-28 14:54 [U-Boot] [PATCH v3] mx6: Enable L2 cache support Fabio Estevam
2014-01-28 14:58 ` Stefano Babic
2014-01-28 16:53 ` Dirk Behme
2014-01-28 19:12 ` Fabio Estevam
2014-01-29 12:47 ` Stefano Babic
2014-01-29 17:57 ` Fabio Estevam
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