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* [U-Boot] [PATCH v2 1/2] i2c: zynq: Support for 0-length register address
@ 2014-01-22  8:46 Michal Simek
  2014-01-22  8:46 ` [U-Boot] [PATCH v2 2/2] i2c: zynq: Add support for the second i2c controller Michal Simek
  2014-01-30  5:26 ` [U-Boot] [PATCH v2 1/2] i2c: zynq: Support for 0-length register address Heiko Schocher
  0 siblings, 2 replies; 5+ messages in thread
From: Michal Simek @ 2014-01-22  8:46 UTC (permalink / raw)
  To: u-boot

From: Michael Burr <michael.burr@logicpd.com>

Fixed bug with alen == 0 in 'i2c_write', 'i2c_read'
Further minor corrections:
- Write 'address' register before 'data' register.
- Write 'transfer_size' register before 'address' register.

Signed-off-by: Michael Burr <michael.burr@logicpd.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

---

Changes in v2:
- Fix incorrect rebase

Changes in v1:
- Based on original thread from Michael Burr
  http://lists.denx.de/pipermail/u-boot/2013-October/165060.html
- MS rebase on latest&greatest

 drivers/i2c/zynq_i2c.c | 42 +++++++++++++++++++++++-------------------
 1 file changed, 23 insertions(+), 19 deletions(-)

diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c
index 70a9aea..11ef0f8 100644
--- a/drivers/i2c/zynq_i2c.c
+++ b/drivers/i2c/zynq_i2c.c
@@ -189,20 +189,22 @@ static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 	 * Temporarily disable restart (by clearing hold)
 	 * It doesn't seem to work.
 	 */
-	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW |
-		ZYNQ_I2C_CONTROL_HOLD);
+	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 	writel(0xFF, &zynq_i2c->interrupt_status);
-	while (alen--)
-		writel(addr >> (8*alen), &zynq_i2c->data);
-	writel(dev, &zynq_i2c->address);
+	if (alen) {
+		clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
+		writel(dev, &zynq_i2c->address);
+		while (alen--)
+			writel(addr >> (8 * alen), &zynq_i2c->data);

-	/* Wait for the address to be sent */
-	if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
-		/* Release the bus */
-		clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
-		return -ETIMEDOUT;
+		/* Wait for the address to be sent */
+		if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
+			/* Release the bus */
+			clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
+			return -ETIMEDOUT;
+		}
+		debug("Device acked address\n");
 	}
-	debug("Device acked address\n");

 	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
 		ZYNQ_I2C_CONTROL_RW);
@@ -247,17 +249,19 @@ static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 		ZYNQ_I2C_CONTROL_HOLD);
 	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
 	writel(0xFF, &zynq_i2c->interrupt_status);
-	while (alen--)
-		writel(addr >> (8*alen), &zynq_i2c->data);
-	/* Start the tranfer */
 	writel(dev, &zynq_i2c->address);
-	if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
-		/* Release the bus */
-		clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
-		return -ETIMEDOUT;
+	if (alen) {
+		while (alen--)
+			writel(addr >> (8 * alen), &zynq_i2c->data);
+		/* Start the tranfer */
+		if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
+			/* Release the bus */
+			clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
+			return -ETIMEDOUT;
+		}
+		debug("Device acked address\n");
 	}

-	debug("Device acked address\n");
 	while (length--) {
 		writel(*(cur_data++), &zynq_i2c->data);
 		if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) {
--
1.8.2.3

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^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [U-Boot] [PATCH v2 0/2] I2C: Zynq
@ 2013-10-15 17:18 Michael Burr
  2013-10-15 17:18 ` [U-Boot] [PATCH v2 1/2] I2C: Zynq: Support for 0-length register address Michael Burr
  0 siblings, 1 reply; 5+ messages in thread
From: Michael Burr @ 2013-10-15 17:18 UTC (permalink / raw)
  To: u-boot

This series of two patches contains improvements for the I2C driver on the
Xilinx Zynq architecture. In general, the goals are:
 > Support for both I2C bus masters ("I2C0" and "I2C1") in the Zynq PS.
 > Full support for bus multiplexers.
 > Support for all register-address sizes (0, 1, 2).

The changes to file 'zynq_i2c.c' in this patch series are
meant to be applied in order: in other words, first apply the
changes from the PATCH 1/2 version; then apply the changes in the
PATCH 2/2 version.


Michael Burr (2):
   I2C: Zynq: Support for 0-length register address
   I2C:Zynq: Adapt this driver to the new model

  README                 |    9 +++
  drivers/i2c/Makefile   |    2 +-
  drivers/i2c/zynq_i2c.c |  147 
+++++++++++++++++++++++++++++-------------------
  include/configs/zynq.h |   10 ++--
  4 files changed, 102 insertions(+), 66 deletions(-)

-- 
1.7.9.5

^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2014-01-30  5:27 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-01-22  8:46 [U-Boot] [PATCH v2 1/2] i2c: zynq: Support for 0-length register address Michal Simek
2014-01-22  8:46 ` [U-Boot] [PATCH v2 2/2] i2c: zynq: Add support for the second i2c controller Michal Simek
2014-01-30  5:27   ` Heiko Schocher
2014-01-30  5:26 ` [U-Boot] [PATCH v2 1/2] i2c: zynq: Support for 0-length register address Heiko Schocher
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2013-10-15 17:18 [U-Boot] [PATCH v2 0/2] I2C: Zynq Michael Burr
2013-10-15 17:18 ` [U-Boot] [PATCH v2 1/2] I2C: Zynq: Support for 0-length register address Michael Burr

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