[U-Boot] [PATCH 1/4] ARM: tegra: move CONFIG_TEGRAnn

[U-Boot] [PATCH 1/4] ARM: tegra: move CONFIG_TEGRAnn

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

<asm/arch-tegra/tegra.h> needs to use CONFIG_TEGRA* to conditionalize
some definitions, since some modules moved between generations. Move
the definition of CONFIG_TEGRAnn to a header that's included earlier,
so that it's set by the time tegra.h needs to use it.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 arch/arm/include/asm/arch-tegra114/tegra.h | 2 ++
 arch/arm/include/asm/arch-tegra124/tegra.h | 2 ++
 arch/arm/include/asm/arch-tegra20/tegra.h  | 2 ++
 arch/arm/include/asm/arch-tegra30/tegra.h  | 2 ++
 include/configs/tegra114-common.h          | 5 -----
 include/configs/tegra124-common.h          | 5 -----
 include/configs/tegra20-common.h           | 5 -----
 include/configs/tegra30-common.h           | 5 -----
 8 files changed, 8 insertions(+), 20 deletions(-)

diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h
index 5d426b524a1e..705ca5758e2b 100644
--- a/arch/arm/include/asm/arch-tegra114/tegra.h
+++ b/arch/arm/include/asm/arch-tegra114/tegra.h
@@ -17,6 +17,8 @@
 #ifndef _TEGRA114_H_
 #define _TEGRA114_H_
 
+#define CONFIG_TEGRA114
+
 #define NV_PA_SDRAM_BASE	0x80000000	/* 0x80000000 for real T114 */
 #define NV_PA_TSC_BASE		0x700F0000	/* System Counter TSC regs */
 
diff --git a/arch/arm/include/asm/arch-tegra124/tegra.h b/arch/arm/include/asm/arch-tegra124/tegra.h
index db3d8379203b..86ebd19453ef 100644
--- a/arch/arm/include/asm/arch-tegra124/tegra.h
+++ b/arch/arm/include/asm/arch-tegra124/tegra.h
@@ -8,6 +8,8 @@
 #ifndef _TEGRA124_H_
 #define _TEGRA124_H_
 
+#define CONFIG_TEGRA124
+
 #define NV_PA_SDRAM_BASE	0x80000000
 #define NV_PA_TSC_BASE		0x700F0000	/* System Counter TSC regs */
 #define NV_PA_MC_BASE		0x70019000	/* Mem Ctlr regs (MCB, etc.) */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h
index 18856ac3727d..6a4b40ec7608 100644
--- a/arch/arm/include/asm/arch-tegra20/tegra.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra.h
@@ -8,6 +8,8 @@
 #ifndef _TEGRA20_H_
 #define _TEGRA20_H_
 
+#define CONFIG_TEGRA20
+
 #define NV_PA_SDRAM_BASE	0x00000000
 
 #include <asm/arch-tegra/tegra.h>
diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h
index c02c5d850037..4ad8b1c05346 100644
--- a/arch/arm/include/asm/arch-tegra30/tegra.h
+++ b/arch/arm/include/asm/arch-tegra30/tegra.h
@@ -17,6 +17,8 @@
 #ifndef _TEGRA30_H_
 #define _TEGRA30_H_
 
+#define CONFIG_TEGRA30
+
 #define NV_PA_SDRAM_BASE	0x80000000	/* 0x80000000 for real T30 */
 
 #include <asm/arch-tegra/tegra.h>
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
index a4e8a5f5eb53..1bf5af5b3830 100644
--- a/include/configs/tegra114-common.h
+++ b/include/configs/tegra114-common.h
@@ -26,11 +26,6 @@
  */
 #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA114			/* in a NVidia Tegra114 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
 
diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h
index 0a4541bd20e6..4568bc761ecd 100644
--- a/include/configs/tegra124-common.h
+++ b/include/configs/tegra124-common.h
@@ -18,11 +18,6 @@
  */
 #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA124			/* is an NVIDIA Tegra124 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
 
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index b009a316b14c..d2c45321b46a 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -24,11 +24,6 @@
  */
 #define V_NS16550_CLK		216000000	/* 216MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA20				/* in a NVidia Tegra20 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR		0x00408000	/* def. location for kernel */
 
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index b5550d7d099c..edb930e032bc 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -23,11 +23,6 @@
  */
 #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA30			/* in a NVidia Tegra30 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
 
-- 
1.8.1.5

[U-Boot] [PATCH 2/4] ARM: tegra: fix pmc_pwrgate_timer_mult register definition

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Register pmc_pwrgate_timer_mult has a different layout on Tegra114 and
Tegra124. Reflect this in pmc.h.

Also, simply write the whole of the register in start_cpu() rather than
doing a read-modify-write; the register is simple enough that the code
can easily construct the entire desired value.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 arch/arm/cpu/arm720t/tegra124/cpu.c   |  4 ++--
 arch/arm/include/asm/arch-tegra/pmc.h | 11 +++++++++++
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/arm720t/tegra124/cpu.c b/arch/arm/cpu/arm720t/tegra124/cpu.c
index c03aaf17e945..97f5928bd7da 100644
--- a/arch/arm/cpu/arm720t/tegra124/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra124/cpu.c
@@ -252,8 +252,8 @@ void start_cpu(u32 reset_vector)
 	tegra124_init_clocks();
 
 	/* Set power-gating timer multiplier */
-	clrbits_le32(&pmc->pmc_pwrgate_timer_mult, TIMER_MULT_MASK);
-	setbits_le32(&pmc->pmc_pwrgate_timer_mult, MULT_8);
+	writel((MULT_8 << TIMER_MULT_SHIFT) | (MULT_8 << TIMER_MULT_CPU_SHIFT),
+	       &pmc->pmc_pwrgate_timer_mult);
 
 	enable_cpu_power_rail();
 	enable_cpu_clocks();
diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h
index 4c3264b3859b..1dd3154fbccb 100644
--- a/arch/arm/include/asm/arch-tegra/pmc.h
+++ b/arch/arm/include/asm/arch-tegra/pmc.h
@@ -298,14 +298,25 @@ struct pmc_ctlr {
 #define PMC_XOFS_SHIFT	1
 #define PMC_XOFS_MASK	(0x3F << PMC_XOFS_SHIFT)
 
+#if defined(CONFIG_TEGRA114)
 #define TIMER_MULT_SHIFT	0
 #define TIMER_MULT_MASK		(3 << TIMER_MULT_SHIFT)
 #define TIMER_MULT_CPU_SHIFT	2
 #define TIMER_MULT_CPU_MASK	(3 << TIMER_MULT_CPU_SHIFT)
+#elif defined(CONFIG_TEGRA124)
+#define TIMER_MULT_SHIFT	0
+#define TIMER_MULT_MASK		(7 << TIMER_MULT_SHIFT)
+#define TIMER_MULT_CPU_SHIFT	3
+#define TIMER_MULT_CPU_MASK	(7 << TIMER_MULT_CPU_SHIFT)
+#endif
+
 #define MULT_1			0
 #define MULT_2			1
 #define MULT_4			2
 #define MULT_8			3
+#if defined(CONFIG_TEGRA124)
+#define MULT_16			4
+#endif
 
 #define AMAP_WRITE_SHIFT	20
 #define AMAP_WRITE_ON		(1 << AMAP_WRITE_SHIFT)
-- 
1.8.1.5

[U-Boot] [PATCH 3/4] ARM: tegra: fix NV_PA_CSITE_BASE for Tegra124

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Tegra124 moved the CSITE block's base address. Fix U-Boot to use
the correct address.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 arch/arm/include/asm/arch-tegra/tegra.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index 5fe19ae1ac13..d63af0e5fd9c 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -34,7 +34,12 @@
 #define NV_PA_PMC_BASE		(NV_PA_APB_MISC_BASE + 0xE400)
 #define NV_PA_EMC_BASE		(NV_PA_APB_MISC_BASE + 0xF400)
 #define NV_PA_FUSE_BASE		(NV_PA_APB_MISC_BASE + 0xF800)
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
+	defined(CONFIG_TEGRA114)
 #define NV_PA_CSITE_BASE	0x70040000
+#else
+#define NV_PA_CSITE_BASE	0x70800000
+#endif
 #define TEGRA_USB_ADDR_MASK	0xFFFFC000
 
 #define NV_PA_SDRC_CS0		NV_PA_SDRAM_BASE
-- 
1.8.1.5

[U-Boot] [PATCH 3/4] ARM: tegra: fix NV_PA_CSITE_BASE for Tegra124

[Tom Warren]

Nice catch, fortunately I don't see this base addr used anywhere (yet) in T124.

> -----Original Message-----
> From: Stephen Warren [mailto:swarren at wwwdotorg.org]
> Sent: Monday, February 03, 2014 2:03 PM
> To: u-boot at lists.denx.de; Simon Glass; Tom Warren; Stephen Warren
> Subject: [PATCH 3/4] ARM: tegra: fix NV_PA_CSITE_BASE for Tegra124
> 
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra124 moved the CSITE block's base address. Fix U-Boot to use the correct
> address.
> 
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
>  arch/arm/include/asm/arch-tegra/tegra.h | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-tegra/tegra.h
> b/arch/arm/include/asm/arch-tegra/tegra.h
> index 5fe19ae1ac13..d63af0e5fd9c 100644
> --- a/arch/arm/include/asm/arch-tegra/tegra.h
> +++ b/arch/arm/include/asm/arch-tegra/tegra.h
> @@ -34,7 +34,12 @@
>  #define NV_PA_PMC_BASE		(NV_PA_APB_MISC_BASE + 0xE400)
>  #define NV_PA_EMC_BASE		(NV_PA_APB_MISC_BASE + 0xF400)
>  #define NV_PA_FUSE_BASE		(NV_PA_APB_MISC_BASE + 0xF800)
> +#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
> +	defined(CONFIG_TEGRA114)
>  #define NV_PA_CSITE_BASE	0x70040000
> +#else
> +#define NV_PA_CSITE_BASE	0x70800000
> +#endif
>  #define TEGRA_USB_ADDR_MASK	0xFFFFC000
> 
>  #define NV_PA_SDRC_CS0		NV_PA_SDRAM_BASE
> --
> 1.8.1.5
--
nvpublic

[U-Boot] [PATCH 3/4] ARM: tegra: fix NV_PA_CSITE_BASE for Tegra124

[Stephen Warren]

On 02/03/2014 02:18 PM, Tom Warren wrote:
> Nice catch, fortunately I don't see this base addr used anywhere (yet) in T124.

It's used to define CSITE_CPU_DBG*_LAR, and those are used in code.

(The internal Tegra simulator I'm running complains about the incorrect
register accesses when booting U-boot)

> 
>> -----Original Message-----
>> From: Stephen Warren [mailto:swarren at wwwdotorg.org]
>> Sent: Monday, February 03, 2014 2:03 PM
>> To: u-boot at lists.denx.de; Simon Glass; Tom Warren; Stephen Warren
>> Subject: [PATCH 3/4] ARM: tegra: fix NV_PA_CSITE_BASE for Tegra124
>>
>> From: Stephen Warren <swarren@nvidia.com>
>>
>> Tegra124 moved the CSITE block's base address. Fix U-Boot to use the correct
>> address.
>>
>> Signed-off-by: Stephen Warren <swarren@nvidia.com>
>> ---
>>  arch/arm/include/asm/arch-tegra/tegra.h | 5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm/include/asm/arch-tegra/tegra.h
>> b/arch/arm/include/asm/arch-tegra/tegra.h
>> index 5fe19ae1ac13..d63af0e5fd9c 100644
>> --- a/arch/arm/include/asm/arch-tegra/tegra.h
>> +++ b/arch/arm/include/asm/arch-tegra/tegra.h
>> @@ -34,7 +34,12 @@
>>  #define NV_PA_PMC_BASE		(NV_PA_APB_MISC_BASE + 0xE400)
>>  #define NV_PA_EMC_BASE		(NV_PA_APB_MISC_BASE + 0xF400)
>>  #define NV_PA_FUSE_BASE		(NV_PA_APB_MISC_BASE + 0xF800)
>> +#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
>> +	defined(CONFIG_TEGRA114)
>>  #define NV_PA_CSITE_BASE	0x70040000
>> +#else
>> +#define NV_PA_CSITE_BASE	0x70800000
>> +#endif
>>  #define TEGRA_USB_ADDR_MASK	0xFFFFC000
>>
>>  #define NV_PA_SDRC_CS0		NV_PA_SDRAM_BASE
>> --
>> 1.8.1.5
> --
> nvpublic
> 

[U-Boot] [PATCH 4/4] ARM: tegra: simplify halt_avp()

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

In order to completely halt the AVP processor, we should simply write
FLOW_MODE_STOP without any extra options that allow wakeup. Amend the
code to do this.

I believe that enabling FIQ_1 and IRQ_1 allow the CPU to be awoken by
interrupts. We don't want this; if later SW wishes to use the AVP, it
should be reset and booted from scratch.

Related, the bits that were previously IRQ_1 and FIQ_1 have a slightly
different definition starting with Tegra114, so the values we're
writing don't entirely make sense there anyway.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 arch/arm/cpu/arm720t/tegra-common/cpu.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index 2c5cd63917d3..168f525ec7c8 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -378,8 +378,7 @@ void clock_enable_coresight(int enable)
 void halt_avp(void)
 {
 	for (;;) {
-		writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
-			| HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
-			FLOW_CTLR_HALT_COP_EVENTS);
+		writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
+		       FLOW_CTLR_HALT_COP_EVENTS);
 	}
 }
-- 
1.8.1.5

[U-Boot] [PATCH 4/4] ARM: tegra: simplify halt_avp()

[Stephen Warren]

On 02/03/2014 02:03 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
> 
> In order to completely halt the AVP processor, we should simply write
> FLOW_MODE_STOP without any extra options that allow wakeup. Amend the
> code to do this.
> 
> I believe that enabling FIQ_1 and IRQ_1 allow the CPU to be awoken by
> interrupts. We don't want this; if later SW wishes to use the AVP, it
> should be reset and booted from scratch.
> 
> Related, the bits that were previously IRQ_1 and FIQ_1 have a slightly
> different definition starting with Tegra114, so the values we're
> writing don't entirely make sense there anyway.

Tom, does this series look good? I'd really like to get these fixes into
2014.04 so that it can boot on our simulator without any local patches.
Thanks.