From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jaehoon Chung Date: Thu, 06 Feb 2014 14:20:10 +0900 Subject: [U-Boot] [PATCH 1/2] exynos: clock: fixed that cfg is set to wrong value. Message-ID: <52F31B8A.6010002@samsung.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Inha Song This patch fixed that cfg value is set to wrong value. Because it didn't read the related register. (Based on Inha's patch : "arm:exynos:add missing readl") Signed-off-by: Inha Song Signed-off-by: Jaehoon Chung --- arch/arm/cpu/armv7/exynos/clock.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 6807ff3..61cd8cf 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -1114,6 +1114,7 @@ void exynos4_set_lcd_clk(void) * MIPI0_PRE_RATIO [23:20] * set fimd ratio */ + cfg = readl(&clk->div_lcd0); cfg &= ~(0xf); cfg |= 0x1; writel(cfg, &clk->div_lcd0); @@ -1176,6 +1177,7 @@ void exynos5_set_lcd_clk(void) * MIPI0_PRE_RATIO [23:20] * set fimd ratio */ + cfg = readl(&clk->div_disp1_0); cfg &= ~(0xf); cfg |= 0x0; writel(cfg, &clk->div_disp1_0); @@ -1236,6 +1238,7 @@ void exynos4_set_mipi_clk(void) * MIPI0_PRE_RATIO [23:20] * set mipi ratio */ + cfg = readl(&clk->div_lcd0); cfg &= ~(0xf << 16); cfg |= (0x1 << 16); writel(cfg, &clk->div_lcd0); -- 1.7.9.5