[U-Boot] [PATCH 1/2] imx6: ensure AHB clock is 132MHz in low freq boot mode

[U-Boot] [PATCH 1/2] imx6: ensure AHB clock is 132MHz in low freq boot mode

[Anson Huang]

For low freq boot mode(ARM boot up with 396MHz), ROM
will not set AHB clock to 132MHz, and the reset value of
AHB divider is incorrect which will lead to wrong AHB
rate, need to correct it. To enable low freq boot mode,
need to set BOOT_CFG2[2] to high, tested on i.MX6Q/DL
SabreSD board and i.MX6SL EVK board.

Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Anson Huang <b20788@freescale.com>
---
 arch/arm/cpu/armv7/mx6/soc.c |   20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 0208cba..33a2939 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -177,10 +177,30 @@ static void imx_set_wdog_powerdown(bool enable)
 	writew(enable, &wdog2->wmcr);
 }
 
+static void set_ahb_rate(u32 val)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	u32 reg, div;
+
+	div = get_periph_clk() / val - 1;
+	reg = readl(&mxc_ccm->cbcdr);
+
+	writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
+		(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
+}
+
 int arch_cpu_init(void)
 {
 	init_aips();
 
+	/*
+	 * When low freq boot is enabled, ROM will not set AHB
+	 * freq, so we need to ensure AHB freq is 132MHz in such
+	 * scenario.
+	 */
+	if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
+		set_ahb_rate(132000000);
+
 	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
 
 #ifdef CONFIG_APBH_DMA
-- 
1.7.9.5

[U-Boot] [PATCH 2/2] imx6: make sure MMDC_CHx_MASK is clear to avoid warm reset failure

[Anson Huang]

Boot ROM may mask MMDC_CHx_MASK in CCM_CCDR(such as i.MX6SL TO1.2),
it will cause warm reset fail, need to clear this MMDC_CHx_MASK field
to make sure all the i.MX6 series SOCs reset function work. Otherwise,
uboot "reset" command will fail, tested on i.MX6SL EVK board with TO1.2.

Signed-off-by: Anson Huang <b20788@freescale.com>
---
 arch/arm/cpu/armv7/mx6/soc.c |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 33a2939..2b162c2 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -189,10 +189,21 @@ static void set_ahb_rate(u32 val)
 		(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
 }
 
+static void clear_mmdc_ch_mask()
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* Clear MMDC channel mask */
+	writel(0, &mxc_ccm->ccdr);
+}
+
 int arch_cpu_init(void)
 {
 	init_aips();
 
+	/* Need to clear MMDC_CHx_MASK to make warm reset work. */
+	clear_mmdc_ch_mask();
+
 	/*
 	 * When low freq boot is enabled, ROM will not set AHB
 	 * freq, so we need to ensure AHB freq is 132MHz in such
-- 
1.7.9.5

[U-Boot] [PATCH 1/2] imx6: ensure AHB clock is 132MHz in low freq boot mode

[Stefano Babic]

On 23/01/2014 07:00, Anson Huang wrote:
> For low freq boot mode(ARM boot up with 396MHz), ROM
> will not set AHB clock to 132MHz, and the reset value of
> AHB divider is incorrect which will lead to wrong AHB
> rate, need to correct it. To enable low freq boot mode,
> need to set BOOT_CFG2[2] to high, tested on i.MX6Q/DL
> SabreSD board and i.MX6SL EVK board.
> 
> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
> Signed-off-by: Anson Huang <b20788@freescale.com>
> ---


Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic



-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 2/2] imx6: make sure MMDC_CHx_MASK is clear to avoid warm reset failure

[Stefano Babic]

On 23/01/2014 07:00, Anson Huang wrote:
> Boot ROM may mask MMDC_CHx_MASK in CCM_CCDR(such as i.MX6SL TO1.2),
> it will cause warm reset fail, need to clear this MMDC_CHx_MASK field
> to make sure all the i.MX6 series SOCs reset function work. Otherwise,
> uboot "reset" command will fail, tested on i.MX6SL EVK board with TO1.2.
> 
> Signed-off-by: Anson Huang <b20788@freescale.com>
> ---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================