* [U-Boot] [PATCH v2] usb: tegra: Fix PHY configuration for Tegra 3
@ 2014-02-14 22:45 Stefan Agner
2014-02-14 22:52 ` Stefan Agner
0 siblings, 1 reply; 4+ messages in thread
From: Stefan Agner @ 2014-02-14 22:45 UTC (permalink / raw)
To: u-boot
On Tegra 3, the PTS (parallel transceiver select) and STS (serial
transceiver select) are part of the HOSTPC1_DEVLC_0 register rather
than PORTSC1_0 register. Since the reset configuration usually
matches the configured registers, this error did not show up on
Tegra 3 devices.
Also clear the forced powerdown bit in the UTMIP_PLL_CFG2_0 register
which brings USB2 in UTMI mode to work. This was clearly missing
since the forced powerdown bit is set in reset by default for all
USB ports.
Also use the slightly different bit fields of first USB, (USBD)
on Tegra 2.
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
drivers/usb/host/ehci-tegra.c | 28 ++++++++++++++++++++++++----
1 file changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 0b42aa5..bd99bce 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -461,6 +461,9 @@ static int init_utmi_usb_controller(struct fdt_usb *config)
if (config->periph_id == PERIPH_ID_USBD)
clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
UTMIP_FORCE_PD_SAMP_A_POWERDOWN);
+ if (config->periph_id == PERIPH_ID_USB2)
+ clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
+ UTMIP_FORCE_PD_SAMP_B_POWERDOWN);
if (config->periph_id == PERIPH_ID_USB3)
clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
UTMIP_FORCE_PD_SAMP_C_POWERDOWN);
@@ -483,9 +486,21 @@ static int init_utmi_usb_controller(struct fdt_usb *config)
clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
/* Select UTMI parallel interface */
- clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
- PTS_UTMI << PTS_SHIFT);
- clrbits_le32(&usbctlr->port_sc1, STS);
+ if (!controller->has_hostpc) {
+ if (config->periph_id == PERIPH_ID_USBD) {
+ clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK,
+ PTS_UTMI << PTS1_SHIFT);
+ clrbits_le32(&usbctlr->port_sc1, STS1);
+ } else {
+ clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
+ PTS_UTMI << PTS_SHIFT);
+ clrbits_le32(&usbctlr->port_sc1, STS);
+ }
+ } else {
+ clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
+ PTS_UTMI << PTS_SHIFT);
+ clrbits_le32(&usbctlr->hostpc1_devlc, STS);
+ }
/* Deassert power down state */
clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
@@ -543,7 +558,12 @@ static int init_ulpi_usb_controller(struct fdt_usb *config)
ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
/* Select ULPI parallel interface */
- clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
+ if (!controller->has_hostpc) {
+ clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
+ PTS_ULPI << PTS_SHIFT);
+ else
+ clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
+ PTS_ULPI << PTS_SHIFT);
/* enable ULPI transceiver */
setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
--
1.8.5.4
^ permalink raw reply related [flat|nested] 4+ messages in thread* [U-Boot] [PATCH v2] usb: tegra: Fix PHY configuration for Tegra 3
2014-02-14 22:45 [U-Boot] [PATCH v2] usb: tegra: Fix PHY configuration for Tegra 3 Stefan Agner
@ 2014-02-14 22:52 ` Stefan Agner
2014-02-15 4:47 ` Jim Lin
0 siblings, 1 reply; 4+ messages in thread
From: Stefan Agner @ 2014-02-14 22:52 UTC (permalink / raw)
To: u-boot
Am 2014-02-14 23:45, schrieb Stefan Agner:
> /* Select ULPI parallel interface */
> - clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
> + if (!controller->has_hostpc) {
> + clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
> + PTS_ULPI << PTS_SHIFT);
> + else
> + clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
> + PTS_ULPI << PTS_SHIFT);
>
> /* enable ULPI transceiver */
> setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
Ok, just noticed that we need to address the different USBD register
layout on Tegra 2 here too.
Furthermore, the code does not compile with Tegra 2 header file since
the hostpc1_devlc field is missing there. The function
ehci_get_port_speed uses a define and some calculation to work around
this issue. Another solution would be to create a dummy field in the
Tegra 2 USB register header file... Any thoughts on that?
^ permalink raw reply [flat|nested] 4+ messages in thread* [U-Boot] [PATCH v2] usb: tegra: Fix PHY configuration for Tegra 3
2014-02-14 22:52 ` Stefan Agner
@ 2014-02-15 4:47 ` Jim Lin
2014-02-15 6:38 ` Stephen Warren
0 siblings, 1 reply; 4+ messages in thread
From: Jim Lin @ 2014-02-15 4:47 UTC (permalink / raw)
To: u-boot
________________________________________
???: Stefan Agner [stefan at agner.ch]
????: 2014?2?15? ?? 06:52
???: u-boot at lists.denx.de; Jim Lin; Tom Warren; swarren at wwwdotorg.org; sjg at chromium.org; dev at lynxeye.de
??: Re: [PATCH v2] usb: tegra: Fix PHY configuration for Tegra 3
Am 2014-02-14 23:45, schrieb Stefan Agner:
> /* Select ULPI parallel interface */
> - clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
> + if (!controller->has_hostpc) {
> + clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
> + PTS_ULPI << PTS_SHIFT);
> + else
> + clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
> + PTS_ULPI << PTS_SHIFT);
>
> /* enable ULPI transceiver */
> setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
Ok, just noticed that we need to address the different USBD register
layout on Tegra 2 here too.
Furthermore, the code does not compile with Tegra 2 header file since
the hostpc1_devlc field is missing there. The function
ehci_get_port_speed uses a define and some calculation to work around
this issue. Another solution would be to create a dummy field in the
Tegra 2 USB register header file... Any thoughts on that?
[Jim} Try use
usbctlr->usb_cmd + HOSTPC1_DEVLC
instead of usbctlr->hostpc1_devlc
--nvpublic
^ permalink raw reply [flat|nested] 4+ messages in thread* [U-Boot] [PATCH v2] usb: tegra: Fix PHY configuration for Tegra 3
2014-02-15 4:47 ` Jim Lin
@ 2014-02-15 6:38 ` Stephen Warren
0 siblings, 0 replies; 4+ messages in thread
From: Stephen Warren @ 2014-02-15 6:38 UTC (permalink / raw)
To: u-boot
On 02/14/2014 09:47 PM, Jim Lin wrote:
>
> ________________________________________
> ???: Stefan Agner [stefan at agner.ch]
> ????: 2014?2?15? ?? 06:52
> ???: u-boot at lists.denx.de; Jim Lin; Tom Warren; swarren at wwwdotorg.org; sjg at chromium.org; dev at lynxeye.de
> ??: Re: [PATCH v2] usb: tegra: Fix PHY configuration for Tegra 3
>
> Am 2014-02-14 23:45, schrieb Stefan Agner:
>> /* Select ULPI parallel interface */
>> - clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
>> + if (!controller->has_hostpc) {
>> + clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
>> + PTS_ULPI << PTS_SHIFT);
>> + else
>> + clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
>> + PTS_ULPI << PTS_SHIFT);
>>
>> /* enable ULPI transceiver */
>> setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
>
> Ok, just noticed that we need to address the different USBD register
> layout on Tegra 2 here too.
>
> Furthermore, the code does not compile with Tegra 2 header file since
> the hostpc1_devlc field is missing there. The function
> ehci_get_port_speed uses a define and some calculation to work around
> this issue. Another solution would be to create a dummy field in the
> Tegra 2 USB register header file... Any thoughts on that?
>
> [Jim} Try use
> usbctlr->usb_cmd + HOSTPC1_DEVLC
> instead of usbctlr->hostpc1_devlc
I don't think we should mix register access styles. Either ifdef the
driver so that only fields appropriate for the SoC being compiled for
are accessed, or if the newer SoCs are just supersets of the earlier
ones, mere the USB headers together so we don't need to split it up per
SoC (and probably add comments indicating which fields are relevant for
which SoCs). Actually, you could probably merge the headers even if you
go down the ifdef route, to avoid duplicating 99% of the header for each
SoC.
^ permalink raw reply [flat|nested] 4+ messages in thread
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2014-02-14 22:45 [U-Boot] [PATCH v2] usb: tegra: Fix PHY configuration for Tegra 3 Stefan Agner
2014-02-14 22:52 ` Stefan Agner
2014-02-15 4:47 ` Jim Lin
2014-02-15 6:38 ` Stephen Warren
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