[U-Boot] [PATCH v3 1/2] watchdog/denali: Adding DesignWare watchdog driver support

[Michal Simek <monstr@monstr.eu>]

On 02/21/2014 09:57 PM, Chin Liang See wrote:
> To add the DesignWare watchdog driver support. It required
> information such as register base address and clock info from
> configuration header file  within include/configs folder.
> 
> Signed-off-by: Chin Liang See <clsee@altera.com>
> Cc: Anatolij Gustschin <agust@denx.de>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Heiko Schocher <hs@denx.de>
> Cc: Tom Rini <trini@ti.com>
> ---
> Changes for v3
> - Split to 2 series patch
> Changes for v2
> - Enable this driver at socfpga_cyclone5 board
> ---
>  drivers/watchdog/Makefile         |    1 +
>  drivers/watchdog/designware_wdt.c |   73 +++++++++++++++++++++++++++++++++++++
>  2 files changed, 74 insertions(+)
>  create mode 100644 drivers/watchdog/designware_wdt.c
> 

Checkpatch.
total: 0 errors, 1 warnings, 1 checks, 77 lines checked


> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> index 06ced10..0276a10 100644
> --- a/drivers/watchdog/Makefile
> +++ b/drivers/watchdog/Makefile
> @@ -15,3 +15,4 @@ obj-$(CONFIG_S5P)               += s5p_wdt.o
>  obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
>  obj-$(CONFIG_BFIN_WATCHDOG)  += bfin_wdt.o
>  obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
> +obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
> diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c
> new file mode 100644
> index 0000000..cb88844
> --- /dev/null
> +++ b/drivers/watchdog/designware_wdt.c
> @@ -0,0 +1,73 @@
> +/*
> + * Copyright (C) 2013 Altera Corporation <www.altera.com>

2014?


> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <watchdog.h>
> +#include <asm/io.h>
> +#include <asm/utils.h>
> +
> +#define DW_WDT_CR	0x00
> +#define DW_WDT_TORR	0x04
> +#define DW_WDT_CRR	0x0C
> +
> +#define DW_WDT_CR_EN_OFFSET	0x00
> +#define DW_WDT_CR_RMOD_OFFSET	0x01
> +#define DW_WDT_CR_RMOD_VAL	0x00
> +#define DW_WDT_CRR_RESTART_VAL	0x76
> +
> +/*
> + * Set the watchdog time interval.
> + * Counter is 32 bit.
> + */
> +int designware_wdt_settimeout(unsigned int timeout)
> +{
> +	signed int i;

you should separate variables from code.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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