From: Michal Simek <monstr@monstr.eu>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 2/2] socfpga: Adding DesignWare watchdog support
Date: Mon, 24 Feb 2014 08:52:52 +0100 [thread overview]
Message-ID: <530AFA54.2070401@monstr.eu> (raw)
In-Reply-To: <1393016264-8092-1-git-send-email-clsee@altera.com>
On 02/21/2014 09:57 PM, Chin Liang See wrote:
> To enable the DesignWare watchdog support at SOCFPGA Cyclone V
> dev kit.
>
> Signed-off-by: Chin Liang See <clsee@altera.com>
> Cc: Anatolij Gustschin <agust@denx.de>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Heiko Schocher <hs@denx.de>
> Cc: Tom Rini <trini@ti.com>
> ---
> Changes for v3
> - Split to 2 series patch
> Changes for v2
> - Enable this driver at socfpga_cyclone5 board
> ---
> .../include/asm/arch-socfpga/socfpga_base_addrs.h | 1 +
> include/configs/socfpga_cyclone5.h | 13 +++++++++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
> index 20f12e0..5f73824 100644
> --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
> +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
> @@ -11,6 +11,7 @@
> #define SOCFPGA_UART0_ADDRESS 0xffc02000
> #define SOCFPGA_UART1_ADDRESS 0xffc03000
> #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
> +#define SOCFPGA_L4WD0_ADDRESS 0xffd02000
> #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
> #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
> #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
> diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
> index fc921ee..1b78ccb 100644
> --- a/include/configs/socfpga_cyclone5.h
> +++ b/include/configs/socfpga_cyclone5.h
> @@ -207,6 +207,16 @@
> #define CONFIG_ENV_IS_NOWHERE
>
> /*
> + * L4 Watchdog
> + */
Why multiline comment here?
> +#define CONFIG_HW_WATCHDOG
> +#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000
> +#define CONFIG_DESIGNWARE_WATCHDOG
> +#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
Why not just use SOCFPGA_L4WD0_ADDRESS directly?
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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next prev parent reply other threads:[~2014-02-24 7:52 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-21 20:57 [U-Boot] [PATCH v3 2/2] socfpga: Adding DesignWare watchdog support Chin Liang See
2014-02-24 7:52 ` Michal Simek [this message]
2014-02-27 19:55 ` Chin Liang See
2014-02-28 10:31 ` Michal Simek
2014-03-04 23:49 ` Chin Liang See
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