From mboxrd@z Thu Jan  1 00:00:00 1970
From: Olliver Schinagl <oliver@schinagl.nl>
Date: Mon, 24 Mar 2014 23:42:17 +0100
Subject: [U-Boot] [PATCH v2 1/9] sunxi: initial sun7i clocks and timer
 support.
In-Reply-To: <201403242152.38910.marex@denx.de>
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	<1395438866-1193-1-git-send-email-ijc@hellion.org.uk>
	<201403242152.38910.marex@denx.de>
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On 03/24/2014 09:52 PM, Marek Vasut wrote:
> On Friday, March 21, 2014 at 10:54:18 PM, Ian Campbell wrote:
>> This has been stripped back for mainlining and supports only sun7i. These
>> changes are not useful by themselves but are split out to make the patch
>> sizes more manageable.
> [...]
>
>> +int clock_init(void)
>> +{
>> +	struct sunxi_ccm_reg *const ccm =
>> +		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>> +
>> +#ifdef CONFIG_SPL_BUILD
>> +	clock_init_safe();
>> +#endif
>> +
>> +	/* uart clock source is apb1 */
>> +	sr32(&ccm->apb1_clk_div_cfg, 24, 2, APB1_CLK_SRC_OSC24M);
>> +	sr32(&ccm->apb1_clk_div_cfg, 16, 2, APB1_FACTOR_N);
>> +	sr32(&ccm->apb1_clk_div_cfg, 0, 5, APB1_FACTOR_M);
>
> sr32() is not defined anywhere.
it should be defined in
arch/arm/include/asm/arch-sunxi/sys_proto.h
and comes from
arch/arm/cpu/armv7/syslib.c

it was added for the ti omap's

I've got a local cleanup patch set where I fixed this already to 
clrsetbits_le32
>
>> +	/* open the clock for uart */
>> +	sr32(&ccm->apb1_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN);
>> +
>> +	return 0;
>> +}
>> +
>> +/* Return PLL5 frequency in Hz
>> + * Note: Assumes PLL5 reference is 24MHz clock
>> + */
>> +unsigned int clock_get_pll5(void)
>> +{
>> +	struct sunxi_ccm_reg *const ccm =
>> +		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>> +	uint32_t rval = readl(&ccm->pll5_cfg);
>> +	int n = (rval >> 8) & 0x1f;
>> +	int k = ((rval >> 4) & 3) + 1;
>> +	int p = 1 << ((rval >> 16) & 3);
>> +	return 24000000 * n * k / p;
> Please fix the magic values here.
> [...]
Same here, got that in my local tree too
>
>> +#ifdef CONFIG_SPL_BUILD
>> +#define PLL1_CFG(N, K, M, P)	(1 << 31 | 0 << 30 | 8 << 26 | 0 << 25 |
> \
>> +				 16 << 20 | (P) << 16 | 2 << 13 | (N) << 8 | \
>> +				 (K) << 4 | 0 << 3 | 0 << 2 | (M) << 0)
> Here is well.
dito :)
>
>> +#define RDIV(a, b)		((a + (b) - 1) / (b))
> This is some kind of DIV_ROUND_UP() from include/common.h ?
>
> [...]
That one i didn't have;

Ian, I guess you can verify that generic macro works for here?
>
>> +	/* Map divisors to register values */
>> +	axi = axi - 1;
>> +	if (ahb > 4)
>> +		ahb = 3;
>> +	else if (ahb > 2)
>> +		ahb = 2;
>> +	else if (ahb > 1)
>> +		ahb = 1;
>> +	else
>> +		ahb = 0;
>> +
>> +	apb0 = apb0 - 1;
>> +
>> +	/* Switch to 24MHz clock while changing PLL1 */
>> +	writel(AXI_DIV_1 << AXI_DIV_SHIFT |
>> +	       AHB_DIV_2 << AHB_DIV_SHIFT |
>> +	       APB0_DIV_1 << APB0_DIV_SHIFT |
>> +	       CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
>> +	       &ccm->cpu_ahb_apb0_cfg);
>> +	sdelay(20);
> What is sdelay() function all about ?
It also is from
arch/arm/include/asm/arch-sunxi/sys_proto.h
and I thought all where replaced with udelays

With the sr32 and sdelays gone everywhere, sunxi/sys_proto.h can even go!
>
> [...]
>
>> +static struct sunxi_timer *timer_base =
>> +	&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->timer[TIMER_NUM];
>> +
>> +/* macro to read the 32 bit timer: since it decrements, we invert read
>> value */ +#define READ_TIMER() (~readl(&timer_base->val))
> This macro has to go, just use ~readl() in place. But still, why do you use that
> negation in "~readl()" anyway ?
>
> [...]
Olliver