[U-Boot] [PATCH 0/3] Add workaround for Cortex-A9 errata

[U-Boot] [PATCH 0/3] Add workaround for Cortex-A9 errata

[nitin.garg at freescale.com]

From: Nitin Garg <nitin.garg@freescale.com>

These patches implement workaround for 2 Cortex-A9 erratas.
Enable these errata workaround for MX6.

Nitin Garg (3):
  ARM: Add workaround for Cortex-A9 errata 794072
  ARM: Add workaround for Cortex-A9 errata 761320
  MX6: Enable ARM errata workaround 794072 and 761320

 README                       |    2 ++
 arch/arm/cpu/armv7/start.S   |    7 ++++++-
 include/configs/mx6_common.h |    2 ++
 3 files changed, 10 insertions(+), 1 deletions(-)

-- 
1.7.4.1

[U-Boot] [PATCH 1/3] ARM: Add workaround for Cortex-A9 errata 794072

[nitin.garg at freescale.com]

From: Nitin Garg <nitin.garg@freescale.com>

A short loop including a DMB instruction might cause a denial of
service on another processor which executes a CP15 broadcast operation.
Exists on r1, r2, r3, r4 revisions.

Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
---
 README                     |    1 +
 arch/arm/cpu/armv7/start.S |    2 +-
 2 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/README b/README
index 7cb7c4f..a496c65 100644
--- a/README
+++ b/README
@@ -566,6 +566,7 @@ The following options need to be configured:
 		CONFIG_ARM_ERRATA_742230
 		CONFIG_ARM_ERRATA_743622
 		CONFIG_ARM_ERRATA_751472
+		CONFIG_ARM_ERRATA_794072
 
 		If set, the workarounds for these ARM errata are applied early
 		during U-Boot startup. Note that these options force the
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index ac1e55a..f3830c8 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -205,7 +205,7 @@ ENTRY(cpu_init_cp15)
 	mcr	p15, 0, r0, c1, c0, 0	@ write system control register
 #endif
 
-#ifdef CONFIG_ARM_ERRATA_742230
+#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
 	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
 	orr	r0, r0, #1 << 4		@ set bit #4
 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
-- 
1.7.4.1

[U-Boot] [PATCH 2/3] ARM: Add workaround for Cortex-A9 errata 761320

[nitin.garg at freescale.com]

From: Nitin Garg <nitin.garg@freescale.com>

Full cache line writes to the same memory region from at least two
processors might deadlock the processor. Exists on r1, r2, r3
revisions.

Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
---
 README                     |    1 +
 arch/arm/cpu/armv7/start.S |    5 +++++
 2 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/README b/README
index a496c65..b7c0f68 100644
--- a/README
+++ b/README
@@ -567,6 +567,7 @@ The following options need to be configured:
 		CONFIG_ARM_ERRATA_743622
 		CONFIG_ARM_ERRATA_751472
 		CONFIG_ARM_ERRATA_794072
+		CONFIG_ARM_ERRATA_761320
 
 		If set, the workarounds for these ARM errata are applied early
 		during U-Boot startup. Note that these options force the
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index f3830c8..27be451 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15)
 	orr	r0, r0, #1 << 11	@ set bit #11
 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
 #endif
+#ifdef CONFIG_ARM_ERRATA_761320
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 21	@ set bit #21
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif
 
 	mov	pc, lr			@ back to my caller
 ENDPROC(cpu_init_cp15)
-- 
1.7.4.1

[U-Boot] [PATCH 3/3] MX6: Enable ARM errata workaround 794072 and 761320

[nitin.garg at freescale.com]

From: Nitin Garg <nitin.garg@freescale.com>

Since MX6 is Cortex-A9 r2p10, enable software workaround
for errata 794072 and 761320.

Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
---
 include/configs/mx6_common.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index eb107d3..8a8920f 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -20,6 +20,8 @@
 #define CONFIG_ARM_ERRATA_742230
 #define CONFIG_ARM_ERRATA_743622
 #define CONFIG_ARM_ERRATA_751472
+#define CONFIG_ARM_ERRATA_794072
+#define CONFIG_ARM_ERRATA_761320
 #define CONFIG_BOARD_POSTCLK_INIT
 
 #ifndef CONFIG_SYS_L2CACHE_OFF
-- 
1.7.4.1

[U-Boot] [PATCH 1/3] ARM: Add workaround for Cortex-A9 errata 794072

[Dirk Behme]

On 02.04.2014 14:58, nitin.garg at freescale.com wrote:
> From: Nitin Garg <nitin.garg@freescale.com>
>
> A short loop including a DMB instruction might cause a denial of
> service on another processor which executes a CP15 broadcast operation.
> Exists on r1, r2, r3, r4 revisions.
>
> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
> ---
>   README                     |    1 +
>   arch/arm/cpu/armv7/start.S |    2 +-
>   2 files changed, 2 insertions(+), 1 deletions(-)
>
> diff --git a/README b/README
> index 7cb7c4f..a496c65 100644
> --- a/README
> +++ b/README
> @@ -566,6 +566,7 @@ The following options need to be configured:
>   		CONFIG_ARM_ERRATA_742230
>   		CONFIG_ARM_ERRATA_743622
>   		CONFIG_ARM_ERRATA_751472
> +		CONFIG_ARM_ERRATA_794072
>
>   		If set, the workarounds for these ARM errata are applied early
>   		during U-Boot startup. Note that these options force the
> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
> index ac1e55a..f3830c8 100644
> --- a/arch/arm/cpu/armv7/start.S
> +++ b/arch/arm/cpu/armv7/start.S
> @@ -205,7 +205,7 @@ ENTRY(cpu_init_cp15)
>   	mcr	p15, 0, r0, c1, c0, 0	@ write system control register
>   #endif
>
> -#ifdef CONFIG_ARM_ERRATA_742230
> +#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
>   	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
>   	orr	r0, r0, #1 << 4		@ set bit #4
>   	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
>

Acked-by: Dirk Behme <dirk.behme@de.bosch.com>

Best regards

Dirk