* [PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings
@ 2022-02-26 3:37 Marek Vasut
2022-02-26 3:37 ` [PATCH 2/2] imx8m: ddrphy_utils: Add 3732 MT/s mode Marek Vasut
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Marek Vasut @ 2022-02-26 3:37 UTC (permalink / raw)
To: u-boot; +Cc: Marek Vasut, Fabio Estevam, Peng Fan, Stefano Babic
Add settings for operating PLL at 933 MHz. This setting is useful in
case the LPDDR4 DRAM should operate at 1866 MHz or 3733 MT/s.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
arch/arm/mach-imx/imx8m/clock_imx8mm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 76132defc21..4db55f86081 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -48,6 +48,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
#ifdef CONFIG_SPL_BUILD
static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
+ PLL_1443X_RATE(933000000U, 311, 4, 1, 0),
PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/2] imx8m: ddrphy_utils: Add 3732 MT/s mode
2022-02-26 3:37 [PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings Marek Vasut
@ 2022-02-26 3:37 ` Marek Vasut
2022-02-26 12:56 ` Fabio Estevam
2022-04-12 18:47 ` sbabic
2022-02-26 12:55 ` [PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings Fabio Estevam
` (2 subsequent siblings)
3 siblings, 2 replies; 8+ messages in thread
From: Marek Vasut @ 2022-02-26 3:37 UTC (permalink / raw)
To: u-boot; +Cc: Marek Vasut, Fabio Estevam, Peng Fan, Stefano Babic
Add entry for 3732 MT/s mode of operation of the LPDDR4, in
which case the DDR PLL has to be configured in 933 MHz mode.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
drivers/ddr/imx/imx8m/ddrphy_utils.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c
index 0f8baefb1f8..a54449e5f14 100644
--- a/drivers/ddr/imx/imx8m/ddrphy_utils.c
+++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c
@@ -117,6 +117,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate)
dram_pll_init(MHZ(1000));
dram_disable_bypass();
break;
+ case 3732:
+ dram_pll_init(MHZ(933));
+ dram_disable_bypass();
+ break;
case 3200:
dram_pll_init(MHZ(800));
dram_disable_bypass();
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 2/2] imx8m: ddrphy_utils: Add 3732 MT/s mode
2022-02-26 3:37 ` [PATCH 2/2] imx8m: ddrphy_utils: Add 3732 MT/s mode Marek Vasut
@ 2022-02-26 12:56 ` Fabio Estevam
2022-04-12 18:47 ` sbabic
1 sibling, 0 replies; 8+ messages in thread
From: Fabio Estevam @ 2022-02-26 12:56 UTC (permalink / raw)
To: Marek Vasut; +Cc: u-boot, Peng Fan, Stefano Babic
On 26/02/2022 00:37, Marek Vasut wrote:
> Add entry for 3732 MT/s mode of operation of the LPDDR4, in
> which case the DDR PLL has to be configured in 933 MHz mode.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/2] imx8m: ddrphy_utils: Add 3732 MT/s mode
2022-02-26 3:37 ` [PATCH 2/2] imx8m: ddrphy_utils: Add 3732 MT/s mode Marek Vasut
2022-02-26 12:56 ` Fabio Estevam
@ 2022-04-12 18:47 ` sbabic
1 sibling, 0 replies; 8+ messages in thread
From: sbabic @ 2022-04-12 18:47 UTC (permalink / raw)
To: Marek Vasut, u-boot
> Add entry for 3732 MT/s mode of operation of the LPDDR4, in
> which case the DDR PLL has to be configured in 933 MHz mode.
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Reviewed-by: Fabio Estevam <festevam@denx.de>
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings
2022-02-26 3:37 [PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings Marek Vasut
2022-02-26 3:37 ` [PATCH 2/2] imx8m: ddrphy_utils: Add 3732 MT/s mode Marek Vasut
@ 2022-02-26 12:55 ` Fabio Estevam
2022-03-21 2:48 ` Peng Fan (OSS)
2022-04-12 18:42 ` sbabic
3 siblings, 0 replies; 8+ messages in thread
From: Fabio Estevam @ 2022-02-26 12:55 UTC (permalink / raw)
To: Marek Vasut; +Cc: u-boot, Peng Fan, Stefano Babic
On 26/02/2022 00:37, Marek Vasut wrote:
> Add settings for operating PLL at 933 MHz. This setting is useful in
> case the LPDDR4 DRAM should operate at 1866 MHz or 3733 MT/s.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings
2022-02-26 3:37 [PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings Marek Vasut
2022-02-26 3:37 ` [PATCH 2/2] imx8m: ddrphy_utils: Add 3732 MT/s mode Marek Vasut
2022-02-26 12:55 ` [PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings Fabio Estevam
@ 2022-03-21 2:48 ` Peng Fan (OSS)
2022-03-21 3:03 ` Marek Vasut
2022-04-12 18:42 ` sbabic
3 siblings, 1 reply; 8+ messages in thread
From: Peng Fan (OSS) @ 2022-03-21 2:48 UTC (permalink / raw)
To: Marek Vasut, u-boot@lists.denx.de; +Cc: Fabio Estevam, Peng Fan, Stefano Babic
On 2022/2/26 11:37, Marek Vasut wrote:
> Add settings for operating PLL at 933 MHz. This setting is useful in
> case the LPDDR4 DRAM should operate at 1866 MHz or 3733 MT/s.
Is the DDR operation value get from NXP DDR TOOL?
Thanks,
Peng.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> arch/arm/mach-imx/imx8m/clock_imx8mm.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> index 76132defc21..4db55f86081 100644
> --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> @@ -48,6 +48,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
> #ifdef CONFIG_SPL_BUILD
> static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
> PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
> + PLL_1443X_RATE(933000000U, 311, 4, 1, 0),
> PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
> PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
> PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
>
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings
2022-03-21 2:48 ` Peng Fan (OSS)
@ 2022-03-21 3:03 ` Marek Vasut
0 siblings, 0 replies; 8+ messages in thread
From: Marek Vasut @ 2022-03-21 3:03 UTC (permalink / raw)
To: Peng Fan (OSS), u-boot@lists.denx.de
Cc: Fabio Estevam, Peng Fan, Stefano Babic
On 3/21/22 03:48, Peng Fan (OSS) wrote:
>
>
> On 2022/2/26 11:37, Marek Vasut wrote:
>> Add settings for operating PLL at 933 MHz. This setting is useful in
>> case the LPDDR4 DRAM should operate at 1866 MHz or 3733 MT/s.
>
> Is the DDR operation value get from NXP DDR TOOL?
No, the DDR RPA supports like two PLL settings, it is very limited.
I had to derive the PLL settings myself and been using those since.
Do you expect any stability issues ? I don't observe any so far, and I
tested it including LCDIFv3 and GPU (etnaviv), no funny behavior was
observed.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings
2022-02-26 3:37 [PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings Marek Vasut
` (2 preceding siblings ...)
2022-03-21 2:48 ` Peng Fan (OSS)
@ 2022-04-12 18:42 ` sbabic
3 siblings, 0 replies; 8+ messages in thread
From: sbabic @ 2022-04-12 18:42 UTC (permalink / raw)
To: Marek Vasut, u-boot
> Add settings for operating PLL at 933 MHz. This setting is useful in
> case the LPDDR4 DRAM should operate at 1866 MHz or 3733 MT/s.
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Reviewed-by: Fabio Estevam <festevam@denx.de>
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-04-12 19:01 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
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2022-02-26 3:37 [PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings Marek Vasut
2022-02-26 3:37 ` [PATCH 2/2] imx8m: ddrphy_utils: Add 3732 MT/s mode Marek Vasut
2022-02-26 12:56 ` Fabio Estevam
2022-04-12 18:47 ` sbabic
2022-02-26 12:55 ` [PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings Fabio Estevam
2022-03-21 2:48 ` Peng Fan (OSS)
2022-03-21 3:03 ` Marek Vasut
2022-04-12 18:42 ` sbabic
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