[U-Boot] [PATCH 04/11] MX6: add common SPL configuration

Nikita Kiryanov
2014-04-10T14:37:56Z

On 04/09/2014 06:32 PM, Tim Harvey wrote:
> On Wed, Apr 9, 2014 at 7:55 AM, Nikita Kiryanov <nikita@compulab.co.il> wrote:
>> Hi Tim,
>>
>> On 04/03/2014 09:01 AM, Tim Harvey wrote:> Add a common header which can
>> hopefully be shared among imx6 SPL users
>>
>>>
>>> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
>>> ---
>>> include/configs/imx6_spl.h | 64
>>
>> ++++++++++++++++++++++++++++++++++++++++++++++
>>>
>>> 1 file changed, 64 insertions(+)
>>> create mode 100644 include/configs/imx6_spl.h
>>>
>>> diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
>>> new file mode 100644
>>> index 0000000..f9bdf55
>>> --- /dev/null
>>> +++ b/include/configs/imx6_spl.h
>>> @@ -0,0 +1,64 @@
>>> +/*
>>> + * Author: Tim Harvey <tharvey@gateworks.com>
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0+
>>> + */
>>> +#ifndef __IMX6_SPL_CONFIG_H
>>> +#define __IMX6_SPL_CONFIG_H
>>> +
>>> +#ifdef CONFIG_SPL
>>> +
>>> +#define CONFIG_SPL_FRAMEWORK
>>> +
>>> +/*
>>> + * IMX6 OCRAM (IRAM) is from 0x00907000 to 0x0093FFFF
>>
>>
>> That's not true for all IMX6 SoCs. On i.MX6 Solo and DualLite it's
>> 0x00907000 to 0x0091FFFF.
>>
>>
>>> + * - we start at 0x00908000 so as to leave some room for IVT/DCD
>>> + * - recommended stack (from IMX6DQRM Figure 8-3) is at 0x0093FFB8
>>> + * - this leaves about 224K for SPL image and stack
>>> + */
>>> +#define CONFIG_SPL_LDSCRIPT
>>> "arch/arm/cpu/armv7/mx6/u-boot-spl.lds"
>>> +#define CONFIG_SPL_TEXT_BASE 0x00908000
>>> +#define CONFIG_SPL_MAX_SIZE (128 * 1024)
>>
>>
>> This should be a smaller value if we want this config to apply for
>> i.MX6 Solo and DualLite, which have a 68KB OCRAM free area.
>
> Hi Nikita,
>
> Agreed - I just discovered this yesterday. I had tested on an
> IMX6DL/SOLO via boot from OTG, but I had not tested those combinations
> when booting from flash and indeed they failed.
>
> The 68KB OCRAM free area also assumes that you start at 0x00907000 and
> as we start at 0x00908000 to leave room for the IVT+DCD this becomes
> 65KB
>
>>
>>
>>> +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7"
>>> +#define CONFIG_SPL_STACK 0x0093FFB8
>>
>>
>> For i.MX6 Solo and DualLite this address should be lower (recommended
>> address is 0x0091FFB8).
>
> Agreed
>
>>
>>
>>> +#define CONFIG_SPL_LIBCOMMON_SUPPORT
>>> +#define CONFIG_SPL_LIBGENERIC_SUPPORT
>>> +#define CONFIG_SPL_SERIAL_SUPPORT
>>> +#define CONFIG_SPL_I2C_SUPPORT
>>> +#define CONFIG_SPL_GPIO_SUPPORT
>>> +
>>> +/* NAND support */
>>> +#if defined(CONFIG_SPL_NAND_SUPPORT)
>>> +#define CONFIG_SPL_NAND_MXS
>>> +#define CONFIG_SPL_NAND_BASE
>>> +#define CONFIG_SPL_DMA_SUPPORT
>>> +#endif
>>
>>
>>
>> --
>> Regards,
>> Nikita.
>
> This presents another challenge for SPL NAND as currently my SPL is
> ~70K. There is a lot of unnecessary code in the mtd nand layer that
> I'm including because that layer includes support for both read and
> write (I don't need write for SPL) as well as various NAND types (and
> I only need BCH).
>
> I'm not sure yet what the best approach is to resolve that. I can either:
> a) add a lot of ifdef's around functions in
> drivers/mtd/nand/{nand_base.c,nand_bbt.c} to remove NAND write and non
> BCH support for CONFIG_SPL_BUILD
> b) re-write the necessary functionality (code duplication) into
> drivers/mtd/nand/mxs_nand_spl.c
>
> Thanks for the review!

You're welcome. Let's see if the NAND maintainer can offer some
suggestions.

Cc-ing Scott Wood

>
> Tim
>

--
Regards,
Nikita.