[U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature

[U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature

[Akshay Saraswat]

From: Rajeshwari Shinde <rajeshwari.s@samsung.com>

This patch adds gpio pin numbering support for EXYNOS 5250 & 5420.
To have consistent 0..n-1 GPIO numbering the banks are divided
into different parts where ever they have holes in them.

Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
---
 arch/arm/cpu/armv7/exynos/pinmux.c      | 287 +++++-------
 arch/arm/include/asm/arch-exynos/cpu.h  |  17 +-
 arch/arm/include/asm/arch-exynos/gpio.h | 742 +++++++++++++++++++++++++++++++-
 board/samsung/smdk5250/exynos5-dt.c     |  20 +-
 board/samsung/smdk5250/smdk5250.c       |  19 +-
 board/samsung/smdk5420/smdk5420.c       |  15 +-
 drivers/gpio/s5p_gpio.c                 |  44 +-
 7 files changed, 923 insertions(+), 221 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index 9edb475..34c24cd 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -13,30 +13,23 @@
 
 static void exynos5_uart_config(int peripheral)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-	struct s5p_gpio_bank *bank;
 	int i, start, count;
 
 	switch (peripheral) {
 	case PERIPH_ID_UART0:
-		bank = &gpio1->a0;
-		start = 0;
+		start = EXYNOS5_GPIO_A00;
 		count = 4;
 		break;
 	case PERIPH_ID_UART1:
-		bank = &gpio1->d0;
-		start = 0;
+		start = EXYNOS5_GPIO_D00;
 		count = 4;
 		break;
 	case PERIPH_ID_UART2:
-		bank = &gpio1->a1;
-		start = 0;
+		start = EXYNOS5_GPIO_A10;
 		count = 4;
 		break;
 	case PERIPH_ID_UART3:
-		bank = &gpio1->a1;
-		start = 4;
+		start = EXYNOS5_GPIO_A14;
 		count = 2;
 		break;
 	default:
@@ -44,37 +37,30 @@ static void exynos5_uart_config(int peripheral)
 		return;
 	}
 	for (i = start; i < start + count; i++) {
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+		gpio_set_pull(i, GPIO_PULL_NONE);
+		gpio_cfg_pin(i, GPIO_FUNC(0x2));
 	}
 }
 
 static void exynos5420_uart_config(int peripheral)
 {
-	struct exynos5420_gpio_part1 *gpio1 =
-		(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
-	struct s5p_gpio_bank *bank;
 	int i, start, count;
 
 	switch (peripheral) {
 	case PERIPH_ID_UART0:
-		bank = &gpio1->a0;
-		start = 0;
+		start = EXYNOS5420_GPIO_A00;
 		count = 4;
 		break;
 	case PERIPH_ID_UART1:
-		bank = &gpio1->a0;
-		start = 4;
+		start = EXYNOS5420_GPIO_A04;
 		count = 4;
 		break;
 	case PERIPH_ID_UART2:
-		bank = &gpio1->a1;
-		start = 0;
+		start = EXYNOS5420_GPIO_A10;
 		count = 4;
 		break;
 	case PERIPH_ID_UART3:
-		bank = &gpio1->a1;
-		start = 4;
+		start = EXYNOS5420_GPIO_A14;
 		count = 2;
 		break;
 	default:
@@ -83,64 +69,59 @@ static void exynos5420_uart_config(int peripheral)
 	}
 
 	for (i = start; i < start + count; i++) {
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+		gpio_set_pull(i, GPIO_PULL_NONE);
+		gpio_cfg_pin(i, GPIO_FUNC(0x2));
 	}
 }
 
 static int exynos5_mmc_config(int peripheral, int flags)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-	struct s5p_gpio_bank *bank, *bank_ext;
-	int i, start = 0, gpio_func = 0;
+	int i, start, start_ext, gpio_func = 0;
 
 	switch (peripheral) {
 	case PERIPH_ID_SDMMC0:
-		bank = &gpio1->c0;
-		bank_ext = &gpio1->c1;
-		start = 0;
+		start = EXYNOS5_GPIO_C00;
+		start_ext = EXYNOS5_GPIO_C10;
 		gpio_func = GPIO_FUNC(0x2);
 		break;
 	case PERIPH_ID_SDMMC1:
-		bank = &gpio1->c2;
-		bank_ext = NULL;
+		start = EXYNOS5_GPIO_C20;
+		start_ext = 0;
 		break;
 	case PERIPH_ID_SDMMC2:
-		bank = &gpio1->c3;
-		bank_ext = &gpio1->c4;
-		start = 3;
+		start = EXYNOS5_GPIO_C30;
+		start_ext = EXYNOS5_GPIO_C43;
 		gpio_func = GPIO_FUNC(0x3);
 		break;
 	case PERIPH_ID_SDMMC3:
-		bank = &gpio1->c4;
-		bank_ext = NULL;
+		start = EXYNOS5_GPIO_C40;
+		start_ext = 0;
 		break;
 	default:
 		debug("%s: invalid peripheral %d", __func__, peripheral);
 		return -1;
 	}
-	if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+	if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
 		debug("SDMMC device %d does not support 8bit mode",
 				peripheral);
 		return -1;
 	}
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
-		for (i = start; i <= (start + 3); i++) {
-			s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
-			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
-			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+		for (i = start_ext; i <= (start_ext + 3); i++) {
+			gpio_cfg_pin(i, gpio_func);
+			gpio_set_pull(i, GPIO_PULL_UP);
+			gpio_set_drv(i, GPIO_DRV_4X);
 		}
 	}
 	for (i = 0; i < 2; i++) {
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+		gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
+		gpio_set_pull(start + i, GPIO_PULL_NONE);
+		gpio_set_drv(start + i, GPIO_DRV_4X);
 	}
 	for (i = 3; i <= 6; i++) {
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+		gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
+		gpio_set_pull(start + i, GPIO_PULL_UP);
+		gpio_set_drv(start + i, GPIO_DRV_4X);
 	}
 
 	return 0;
@@ -148,25 +129,22 @@ static int exynos5_mmc_config(int peripheral, int flags)
 
 static int exynos5420_mmc_config(int peripheral, int flags)
 {
-	struct exynos5420_gpio_part3 *gpio3 =
-		(struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3();
-	struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL;
-	int i, start;
+	int i, start = 0, start_ext = 0;
 
 	switch (peripheral) {
 	case PERIPH_ID_SDMMC0:
-		bank = &gpio3->c0;
-		bank_ext = &gpio3->c3;
+		start = EXYNOS5420_GPIO_C00;
+		start_ext = EXYNOS5420_GPIO_C30;
 		start = 0;
 		break;
 	case PERIPH_ID_SDMMC1:
-		bank = &gpio3->c1;
-		bank_ext = &gpio3->d1;
+		start = EXYNOS5420_GPIO_C10;
+		start_ext = EXYNOS5420_GPIO_D14;
 		start = 4;
 		break;
 	case PERIPH_ID_SDMMC2:
-		bank = &gpio3->c2;
-		bank_ext = NULL;
+		start = EXYNOS5420_GPIO_C20;
+		start_ext = 0;
 		start = 0;
 		break;
 	default:
@@ -175,7 +153,7 @@ static int exynos5420_mmc_config(int peripheral, int flags)
 		return -1;
 	}
 
-	if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+	if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
 		debug("SDMMC device %d does not support 8bit mode",
 		      peripheral);
 		return -1;
@@ -183,9 +161,9 @@ static int exynos5420_mmc_config(int peripheral, int flags)
 
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
 		for (i = start; i <= (start + 3); i++) {
-			s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x2));
-			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
-			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+			gpio_cfg_pin(i, GPIO_FUNC(0x2));
+			gpio_set_pull(i, GPIO_PULL_UP);
+			gpio_set_drv(i, GPIO_DRV_4X);
 		}
 	}
 
@@ -197,19 +175,19 @@ static int exynos5420_mmc_config(int peripheral, int flags)
 		 * this same assumption.
 		 */
 		if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) {
-			s5p_gpio_set_value(bank, i, 1);
-			s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT);
+			gpio_set_value(i, 1);
+			gpio_cfg_pin(i, GPIO_OUTPUT);
 		} else {
-			s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+			gpio_cfg_pin(i, GPIO_FUNC(0x2));
 		}
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+		gpio_set_pull(i, GPIO_PULL_NONE);
+		gpio_set_drv(i, GPIO_DRV_4X);
 	}
 
 	for (i = 3; i <= 6; i++) {
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+		gpio_cfg_pin(i, GPIO_FUNC(0x2));
+		gpio_set_pull(i, GPIO_PULL_UP);
+		gpio_set_drv(i, GPIO_DRV_4X);
 	}
 
 	return 0;
@@ -217,8 +195,6 @@ static int exynos5420_mmc_config(int peripheral, int flags)
 
 static void exynos5_sromc_config(int flags)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 	int i;
 
 	/*
@@ -236,13 +212,13 @@ static void exynos5_sromc_config(int flags)
 	 * GPY1[2]	SROM_WAIT(2)
 	 * GPY1[3]	EBI_DATA_RDn(2)
 	 */
-	s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK),
-				GPIO_FUNC(2));
-	s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
-	s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
+	gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK),
+		     GPIO_FUNC(2));
+	gpio_cfg_pin(EXYNOS5_GPIO_Y04, GPIO_FUNC(2));
+	gpio_cfg_pin(EXYNOS5_GPIO_Y05, GPIO_FUNC(2));
 
 	for (i = 0; i < 4; i++)
-		s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
+		gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, GPIO_FUNC(2));
 
 	/*
 	 * EBI: 8 Addrss Lines
@@ -277,108 +253,101 @@ static void exynos5_sromc_config(int flags)
 	 * GPY6[7]	EBI_DATA[15](2)
 	 */
 	for (i = 0; i < 8; i++) {
-		s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
-		s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y30 + i, GPIO_PULL_UP);
 
-		s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
-		s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y50 + i, GPIO_PULL_UP);
 
-		s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
-		s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y60 + i, GPIO_PULL_UP);
 	}
 }
 
 static void exynos5_i2c_config(int peripheral, int flags)
 {
-
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-
 	switch (peripheral) {
 	case PERIPH_ID_I2C0:
-		s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B30, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B31, GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C1:
-		s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B32, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B33, GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C2:
-		s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A06, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A07, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C3:
-		s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A12, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A13, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C4:
-		s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A20, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A21, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C5:
-		s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A22, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A23, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C6:
-		s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
-		s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5_GPIO_B13, GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5_GPIO_B14, GPIO_FUNC(0x4));
 		break;
 	case PERIPH_ID_I2C7:
-		s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_B22, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_B23, GPIO_FUNC(0x3));
 		break;
 	}
 }
 
 static void exynos5420_i2c_config(int peripheral)
 {
-	struct exynos5420_gpio_part1 *gpio1 =
-		(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
-
 	switch (peripheral) {
 	case PERIPH_ID_I2C0:
-		s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B30, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B31, GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C1:
-		s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B32, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B33, GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C2:
-		s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A06, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A07, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C3:
-		s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A12, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A13, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C4:
-		s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A20, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A21, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C5:
-		s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A22, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A23, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C6:
-		s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
-		s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B13, GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B14, GPIO_FUNC(0x4));
 		break;
 	case PERIPH_ID_I2C7:
-		s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B22, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B23, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C8:
-		s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B34, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B35, GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C9:
-		s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B36, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B37, GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C10:
-		s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B40, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B41, GPIO_FUNC(0x2));
 		break;
 	}
 }
@@ -386,19 +355,15 @@ static void exynos5420_i2c_config(int peripheral)
 static void exynos5_i2s_config(int peripheral)
 {
 	int i;
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
-	struct exynos5_gpio_part4 *gpio4 =
-		(struct exynos5_gpio_part4 *)samsung_get_base_gpio_part4();
 
 	switch (peripheral) {
 	case PERIPH_ID_I2S0:
 		for (i = 0; i < 5; i++)
-			s5p_gpio_cfg_pin(&gpio4->z, i, GPIO_FUNC(0x02));
+			gpio_cfg_pin(EXYNOS5_GPIO_Z0+i, GPIO_FUNC(0x02));
 		break;
 	case PERIPH_ID_I2S1:
 		for (i = 0; i < 5; i++)
-			s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
+			gpio_cfg_pin(EXYNOS5_GPIO_B00+i, GPIO_FUNC(0x02));
 		break;
 	}
 }
@@ -406,75 +371,57 @@ static void exynos5_i2s_config(int peripheral)
 void exynos5_spi_config(int peripheral)
 {
 	int cfg = 0, pin = 0, i;
-	struct s5p_gpio_bank *bank = NULL;
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-	struct exynos5_gpio_part2 *gpio2 =
-		(struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
 
 	switch (peripheral) {
 	case PERIPH_ID_SPI0:
-		bank = &gpio1->a2;
 		cfg = GPIO_FUNC(0x2);
-		pin = 0;
+		pin = EXYNOS5_GPIO_A20;
 		break;
 	case PERIPH_ID_SPI1:
-		bank = &gpio1->a2;
 		cfg = GPIO_FUNC(0x2);
-		pin = 4;
+		pin = EXYNOS5_GPIO_A24;
 		break;
 	case PERIPH_ID_SPI2:
-		bank = &gpio1->b1;
 		cfg = GPIO_FUNC(0x5);
-		pin = 1;
+		pin = EXYNOS5_GPIO_B11;
 		break;
 	case PERIPH_ID_SPI3:
-		bank = &gpio2->f1;
 		cfg = GPIO_FUNC(0x2);
-		pin = 0;
+		pin = EXYNOS5_GPIO_F10;
 		break;
 	case PERIPH_ID_SPI4:
 		for (i = 0; i < 2; i++) {
-			s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
-			s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
+			gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, GPIO_FUNC(0x4));
+			gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, GPIO_FUNC(0x4));
 		}
 		break;
 	}
 	if (peripheral != PERIPH_ID_SPI4) {
 		for (i = pin; i < pin + 4; i++)
-			s5p_gpio_cfg_pin(bank, i, cfg);
+			gpio_cfg_pin(i, cfg);
 	}
 }
 
 void exynos5420_spi_config(int peripheral)
 {
 	int cfg, pin, i;
-	struct s5p_gpio_bank *bank = NULL;
-	struct exynos5420_gpio_part1 *gpio1 =
-		(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
-	struct exynos5420_gpio_part4 *gpio4 =
-		(struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4();
 
 	switch (peripheral) {
 	case PERIPH_ID_SPI0:
-		bank = &gpio1->a2;
+		pin = EXYNOS5420_GPIO_A20;
 		cfg = GPIO_FUNC(0x2);
-		pin = 0;
 		break;
 	case PERIPH_ID_SPI1:
-		bank = &gpio1->a2;
+		pin = EXYNOS5420_GPIO_A24;
 		cfg = GPIO_FUNC(0x2);
-		pin = 4;
 		break;
 	case PERIPH_ID_SPI2:
-		bank = &gpio1->b1;
+		pin = EXYNOS5420_GPIO_B11;
 		cfg = GPIO_FUNC(0x5);
-		pin = 1;
 		break;
 	case PERIPH_ID_SPI3:
-		bank = &gpio4->f1;
+		pin = EXYNOS5420_GPIO_F10;
 		cfg = GPIO_FUNC(0x2);
-		pin = 0;
 		break;
 	case PERIPH_ID_SPI4:
 		cfg = 0;
@@ -489,11 +436,13 @@ void exynos5420_spi_config(int peripheral)
 
 	if (peripheral != PERIPH_ID_SPI4) {
 		for (i = pin; i < pin + 4; i++)
-			s5p_gpio_cfg_pin(bank, i, cfg);
+			gpio_cfg_pin(i, cfg);
 	} else {
 		for (i = 0; i < 2; i++) {
-			s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4));
-			s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4));
+			gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i,
+				     GPIO_FUNC(0x4));
+			gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i,
+				     GPIO_FUNC(0x4));
 		}
 	}
 }
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index fdf73b5..ba71714 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -98,7 +98,7 @@
 #define EXYNOS5_I2C_SPACING		0x10000
 
 #define EXYNOS5_AUDIOSS_BASE		0x03810000
-#define EXYNOS5_GPIO_PART4_BASE		0x03860000
+#define EXYNOS5_GPIO_PART8_BASE		0x03860000
 #define EXYNOS5_PRO_ID			0x10000000
 #define EXYNOS5_CLOCK_BASE		0x10010000
 #define EXYNOS5_POWER_BASE		0x10040000
@@ -108,9 +108,13 @@
 #define EXYNOS5_WATCHDOG_BASE		0x101D0000
 #define EXYNOS5_ACE_SFR_BASE		0x10830000
 #define EXYNOS5_DMC_PHY_BASE		0x10C00000
-#define EXYNOS5_GPIO_PART3_BASE		0x10D10000
+#define EXYNOS5_GPIO_PART5_BASE		0x10D10000
+#define EXYNOS5_GPIO_PART6_BASE		0x10D10060
+#define EXYNOS5_GPIO_PART7_BASE		0x10D100C0
 #define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
 #define EXYNOS5_GPIO_PART1_BASE		0x11400000
+#define EXYNOS5_GPIO_PART2_BASE		0x114002E0
+#define EXYNOS5_GPIO_PART3_BASE		0x11400C00
 #define EXYNOS5_MIPI_DSIM_BASE		0x11D00000
 #define EXYNOS5_USB_HOST_XHCI_BASE	0x12000000
 #define EXYNOS5_USB3PHY_BASE		0x12100000
@@ -125,7 +129,7 @@
 #define EXYNOS5_I2S_BASE		0x12D60000
 #define EXYNOS5_PWMTIMER_BASE		0x12DD0000
 #define EXYNOS5_SPI_ISP_BASE		0x131A0000
-#define EXYNOS5_GPIO_PART2_BASE		0x13400000
+#define EXYNOS5_GPIO_PART4_BASE		0x13400000
 #define EXYNOS5_FIMD_BASE		0x14400000
 #define EXYNOS5_DP_BASE			0x145B0000
 
@@ -135,7 +139,7 @@
 
 /* EXYNOS5420 */
 #define EXYNOS5420_AUDIOSS_BASE		0x03810000
-#define EXYNOS5420_GPIO_PART5_BASE	0x03860000
+#define EXYNOS5420_GPIO_PART6_BASE	0x03860000
 #define EXYNOS5420_PRO_ID		0x10000000
 #define EXYNOS5420_CLOCK_BASE		0x10010000
 #define EXYNOS5420_POWER_BASE		0x10040000
@@ -158,8 +162,9 @@
 #define EXYNOS5420_PWMTIMER_BASE	0x12DD0000
 #define EXYNOS5420_SPI_ISP_BASE		0x131A0000
 #define EXYNOS5420_GPIO_PART2_BASE	0x13400000
-#define EXYNOS5420_GPIO_PART3_BASE	0x13410000
-#define EXYNOS5420_GPIO_PART4_BASE	0x14000000
+#define EXYNOS5420_GPIO_PART3_BASE	0x13400C00
+#define EXYNOS5420_GPIO_PART4_BASE	0x13410000
+#define EXYNOS5420_GPIO_PART5_BASE	0x14000000
 #define EXYNOS5420_GPIO_PART1_BASE	0x14010000
 #define EXYNOS5420_MIPI_DSIM_BASE	0x14500000
 #define EXYNOS5420_DP_BASE		0x145B0000
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index d6868fa..211383d 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -141,14 +141,16 @@ struct exynos5420_gpio_part1 {
 
 struct exynos5420_gpio_part2 {
 	struct s5p_gpio_bank y7; /* 0x1340_0000 */
-	struct s5p_gpio_bank res[0x5f]; /*  */
+};
+
+struct exynos5420_gpio_part3 {
 	struct s5p_gpio_bank x0; /* 0x1340_0C00 */
 	struct s5p_gpio_bank x1; /* 0x1340_0C20 */
 	struct s5p_gpio_bank x2; /* 0x1340_0C40 */
 	struct s5p_gpio_bank x3; /* 0x1340_0C60 */
 };
 
-struct exynos5420_gpio_part3 {
+struct exynos5420_gpio_part4 {
 	struct s5p_gpio_bank c0;
 	struct s5p_gpio_bank c1;
 	struct s5p_gpio_bank c2;
@@ -164,7 +166,7 @@ struct exynos5420_gpio_part3 {
 	struct s5p_gpio_bank y6;
 };
 
-struct exynos5420_gpio_part4 {
+struct exynos5420_gpio_part5 {
 	struct s5p_gpio_bank e0; /* 0x1400_0000 */
 	struct s5p_gpio_bank e1; /* 0x1400_0020 */
 	struct s5p_gpio_bank f0; /* 0x1400_0040 */
@@ -175,7 +177,7 @@ struct exynos5420_gpio_part4 {
 	struct s5p_gpio_bank j4; /* 0x1400_00E0 */
 };
 
-struct exynos5420_gpio_part5 {
+struct exynos5420_gpio_part6 {
 	struct s5p_gpio_bank z0; /* 0x0386_0000 */
 };
 
@@ -200,16 +202,20 @@ struct exynos5_gpio_part1 {
 	struct s5p_gpio_bank y4;
 	struct s5p_gpio_bank y5;
 	struct s5p_gpio_bank y6;
-	struct s5p_gpio_bank res1[0x3];
+};
+
+struct exynos5_gpio_part2 {
 	struct s5p_gpio_bank c4;
-	struct s5p_gpio_bank res2[0x48];
+};
+
+struct exynos5_gpio_part3 {
 	struct s5p_gpio_bank x0;
 	struct s5p_gpio_bank x1;
 	struct s5p_gpio_bank x2;
 	struct s5p_gpio_bank x3;
 };
 
-struct exynos5_gpio_part2 {
+struct exynos5_gpio_part4 {
 	struct s5p_gpio_bank e0;
 	struct s5p_gpio_bank e1;
 	struct s5p_gpio_bank f0;
@@ -221,20 +227,25 @@ struct exynos5_gpio_part2 {
 	struct s5p_gpio_bank h1;
 };
 
-struct exynos5_gpio_part3 {
+struct exynos5_gpio_part5 {
 	struct s5p_gpio_bank v0;
 	struct s5p_gpio_bank v1;
-	struct s5p_gpio_bank res1[0x1];
+};
+
+struct exynos5_gpio_part6 {
 	struct s5p_gpio_bank v2;
 	struct s5p_gpio_bank v3;
-	struct s5p_gpio_bank res2[0x1];
+};
+
+struct exynos5_gpio_part7 {
 	struct s5p_gpio_bank v4;
 };
 
-struct exynos5_gpio_part4 {
+struct exynos5_gpio_part8 {
 	struct s5p_gpio_bank z;
 };
 
+
 /* functions */
 void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
 void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
@@ -323,6 +334,715 @@ static inline unsigned int s5p_gpio_base(int gpio)
 		return 0;
 	}
 }
+
+/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */
+enum exynos5_gpio_pin {
+	/* GPIO_PART1_STARTS */
+	EXYNOS5_GPIO_A00,	/* 0 */
+	EXYNOS5_GPIO_A01,
+	EXYNOS5_GPIO_A02,
+	EXYNOS5_GPIO_A03,
+	EXYNOS5_GPIO_A04,
+	EXYNOS5_GPIO_A05,
+	EXYNOS5_GPIO_A06,
+	EXYNOS5_GPIO_A07,
+	EXYNOS5_GPIO_A10,	/* 8 */
+	EXYNOS5_GPIO_A11,
+	EXYNOS5_GPIO_A12,
+	EXYNOS5_GPIO_A13,
+	EXYNOS5_GPIO_A14,
+	EXYNOS5_GPIO_A15,
+	EXYNOS5_GPIO_A16,
+	EXYNOS5_GPIO_A17,
+	EXYNOS5_GPIO_A20,	/* 16 0x10 */
+	EXYNOS5_GPIO_A21,
+	EXYNOS5_GPIO_A22,
+	EXYNOS5_GPIO_A23,
+	EXYNOS5_GPIO_A24,
+	EXYNOS5_GPIO_A25,
+	EXYNOS5_GPIO_A26,
+	EXYNOS5_GPIO_A27,
+	EXYNOS5_GPIO_B00,	/* 24 0x18 */
+	EXYNOS5_GPIO_B01,
+	EXYNOS5_GPIO_B02,
+	EXYNOS5_GPIO_B03,
+	EXYNOS5_GPIO_B04,
+	EXYNOS5_GPIO_B05,
+	EXYNOS5_GPIO_B06,
+	EXYNOS5_GPIO_B07,
+	EXYNOS5_GPIO_B10,	/* 32 0x20 */
+	EXYNOS5_GPIO_B11,
+	EXYNOS5_GPIO_B12,
+	EXYNOS5_GPIO_B13,
+	EXYNOS5_GPIO_B14,
+	EXYNOS5_GPIO_B15,
+	EXYNOS5_GPIO_B16,
+	EXYNOS5_GPIO_B17,
+	EXYNOS5_GPIO_B20,	/* 40 0x28 */
+	EXYNOS5_GPIO_B21,
+	EXYNOS5_GPIO_B22,
+	EXYNOS5_GPIO_B23,
+	EXYNOS5_GPIO_B24,
+	EXYNOS5_GPIO_B25,
+	EXYNOS5_GPIO_B26,
+	EXYNOS5_GPIO_B27,
+	EXYNOS5_GPIO_B30,	/* 48 0x39 */
+	EXYNOS5_GPIO_B31,
+	EXYNOS5_GPIO_B32,
+	EXYNOS5_GPIO_B33,
+	EXYNOS5_GPIO_B34,
+	EXYNOS5_GPIO_B35,
+	EXYNOS5_GPIO_B36,
+	EXYNOS5_GPIO_B37,
+	EXYNOS5_GPIO_C00,	/* 56 0x38 */
+	EXYNOS5_GPIO_C01,
+	EXYNOS5_GPIO_C02,
+	EXYNOS5_GPIO_C03,
+	EXYNOS5_GPIO_C04,
+	EXYNOS5_GPIO_C05,
+	EXYNOS5_GPIO_C06,
+	EXYNOS5_GPIO_C07,
+	EXYNOS5_GPIO_C10,	/* 64 0x40 */
+	EXYNOS5_GPIO_C11,
+	EXYNOS5_GPIO_C12,
+	EXYNOS5_GPIO_C13,
+	EXYNOS5_GPIO_C14,
+	EXYNOS5_GPIO_C15,
+	EXYNOS5_GPIO_C16,
+	EXYNOS5_GPIO_C17,
+	EXYNOS5_GPIO_C20,	/* 72 0x48 */
+	EXYNOS5_GPIO_C21,
+	EXYNOS5_GPIO_C22,
+	EXYNOS5_GPIO_C23,
+	EXYNOS5_GPIO_C24,
+	EXYNOS5_GPIO_C25,
+	EXYNOS5_GPIO_C26,
+	EXYNOS5_GPIO_C27,
+	EXYNOS5_GPIO_C30,	/* 80 0x50 */
+	EXYNOS5_GPIO_C31,
+	EXYNOS5_GPIO_C32,
+	EXYNOS5_GPIO_C33,
+	EXYNOS5_GPIO_C34,
+	EXYNOS5_GPIO_C35,
+	EXYNOS5_GPIO_C36,
+	EXYNOS5_GPIO_C37,
+	EXYNOS5_GPIO_D00,	/* 88 0x58 */
+	EXYNOS5_GPIO_D01,
+	EXYNOS5_GPIO_D02,
+	EXYNOS5_GPIO_D03,
+	EXYNOS5_GPIO_D04,
+	EXYNOS5_GPIO_D05,
+	EXYNOS5_GPIO_D06,
+	EXYNOS5_GPIO_D07,
+	EXYNOS5_GPIO_D10,	/* 96 0x60 */
+	EXYNOS5_GPIO_D11,
+	EXYNOS5_GPIO_D12,
+	EXYNOS5_GPIO_D13,
+	EXYNOS5_GPIO_D14,
+	EXYNOS5_GPIO_D15,
+	EXYNOS5_GPIO_D16,
+	EXYNOS5_GPIO_D17,
+	EXYNOS5_GPIO_Y00,	/* 104 0x68 */
+	EXYNOS5_GPIO_Y01,
+	EXYNOS5_GPIO_Y02,
+	EXYNOS5_GPIO_Y03,
+	EXYNOS5_GPIO_Y04,
+	EXYNOS5_GPIO_Y05,
+	EXYNOS5_GPIO_Y06,
+	EXYNOS5_GPIO_Y07,
+	EXYNOS5_GPIO_Y10,	/* 112 0x70 */
+	EXYNOS5_GPIO_Y11,
+	EXYNOS5_GPIO_Y12,
+	EXYNOS5_GPIO_Y13,
+	EXYNOS5_GPIO_Y14,
+	EXYNOS5_GPIO_Y15,
+	EXYNOS5_GPIO_Y16,
+	EXYNOS5_GPIO_Y17,
+	EXYNOS5_GPIO_Y20,	/* 120 0x78 */
+	EXYNOS5_GPIO_Y21,
+	EXYNOS5_GPIO_Y22,
+	EXYNOS5_GPIO_Y23,
+	EXYNOS5_GPIO_Y24,
+	EXYNOS5_GPIO_Y25,
+	EXYNOS5_GPIO_Y26,
+	EXYNOS5_GPIO_Y27,
+	EXYNOS5_GPIO_Y30,	/* 128 0x80 */
+	EXYNOS5_GPIO_Y31,
+	EXYNOS5_GPIO_Y32,
+	EXYNOS5_GPIO_Y33,
+	EXYNOS5_GPIO_Y34,
+	EXYNOS5_GPIO_Y35,
+	EXYNOS5_GPIO_Y36,
+	EXYNOS5_GPIO_Y37,
+	EXYNOS5_GPIO_Y40,	/* 136 0x88 */
+	EXYNOS5_GPIO_Y41,
+	EXYNOS5_GPIO_Y42,
+	EXYNOS5_GPIO_Y43,
+	EXYNOS5_GPIO_Y44,
+	EXYNOS5_GPIO_Y45,
+	EXYNOS5_GPIO_Y46,
+	EXYNOS5_GPIO_Y47,
+	EXYNOS5_GPIO_Y50,	/* 144 0x90 */
+	EXYNOS5_GPIO_Y51,
+	EXYNOS5_GPIO_Y52,
+	EXYNOS5_GPIO_Y53,
+	EXYNOS5_GPIO_Y54,
+	EXYNOS5_GPIO_Y55,
+	EXYNOS5_GPIO_Y56,
+	EXYNOS5_GPIO_Y57,
+	EXYNOS5_GPIO_Y60,	/* 152 0x98 */
+	EXYNOS5_GPIO_Y61,
+	EXYNOS5_GPIO_Y62,
+	EXYNOS5_GPIO_Y63,
+	EXYNOS5_GPIO_Y64,
+	EXYNOS5_GPIO_Y65,
+	EXYNOS5_GPIO_Y66,
+	EXYNOS5_GPIO_Y67,
+
+	/* GPIO_PART2_STARTS */
+	EXYNOS5_GPIO_MAX_PORT_PART_1,	/* 160 0xa0 */
+	EXYNOS5_GPIO_C40 = EXYNOS5_GPIO_MAX_PORT_PART_1,
+	EXYNOS5_GPIO_C41,
+	EXYNOS5_GPIO_C42,
+	EXYNOS5_GPIO_C43,
+	EXYNOS5_GPIO_C44,
+	EXYNOS5_GPIO_C45,
+	EXYNOS5_GPIO_C46,
+	EXYNOS5_GPIO_C47,
+
+	/* GPIO_PART3_STARTS */
+	EXYNOS5_GPIO_MAX_PORT_PART_2,	/* 168 0xa8 */
+	EXYNOS5_GPIO_X00 = EXYNOS5_GPIO_MAX_PORT_PART_2,
+	EXYNOS5_GPIO_X01,
+	EXYNOS5_GPIO_X02,
+	EXYNOS5_GPIO_X03,
+	EXYNOS5_GPIO_X04,
+	EXYNOS5_GPIO_X05,
+	EXYNOS5_GPIO_X06,
+	EXYNOS5_GPIO_X07,
+	EXYNOS5_GPIO_X10,	/* 176 0xb0 */
+	EXYNOS5_GPIO_X11,
+	EXYNOS5_GPIO_X12,
+	EXYNOS5_GPIO_X13,
+	EXYNOS5_GPIO_X14,
+	EXYNOS5_GPIO_X15,
+	EXYNOS5_GPIO_X16,
+	EXYNOS5_GPIO_X17,
+	EXYNOS5_GPIO_X20,	/* 184 0xb8 */
+	EXYNOS5_GPIO_X21,
+	EXYNOS5_GPIO_X22,
+	EXYNOS5_GPIO_X23,
+	EXYNOS5_GPIO_X24,
+	EXYNOS5_GPIO_X25,
+	EXYNOS5_GPIO_X26,
+	EXYNOS5_GPIO_X27,
+	EXYNOS5_GPIO_X30,	/* 192 0xc0 */
+	EXYNOS5_GPIO_X31,
+	EXYNOS5_GPIO_X32,
+	EXYNOS5_GPIO_X33,
+	EXYNOS5_GPIO_X34,
+	EXYNOS5_GPIO_X35,
+	EXYNOS5_GPIO_X36,
+	EXYNOS5_GPIO_X37,
+
+	/* GPIO_PART4_STARTS */
+	EXYNOS5_GPIO_MAX_PORT_PART_3,	/* 200 0xc8 */
+	EXYNOS5_GPIO_E00 = EXYNOS5_GPIO_MAX_PORT_PART_3,
+	EXYNOS5_GPIO_E01,
+	EXYNOS5_GPIO_E02,
+	EXYNOS5_GPIO_E03,
+	EXYNOS5_GPIO_E04,
+	EXYNOS5_GPIO_E05,
+	EXYNOS5_GPIO_E06,
+	EXYNOS5_GPIO_E07,
+	EXYNOS5_GPIO_E10,	/* 208 0xd0 */
+	EXYNOS5_GPIO_E11,
+	EXYNOS5_GPIO_E12,
+	EXYNOS5_GPIO_E13,
+	EXYNOS5_GPIO_E14,
+	EXYNOS5_GPIO_E15,
+	EXYNOS5_GPIO_E16,
+	EXYNOS5_GPIO_E17,
+	EXYNOS5_GPIO_F00,	/* 216 0xd8 */
+	EXYNOS5_GPIO_F01,
+	EXYNOS5_GPIO_F02,
+	EXYNOS5_GPIO_F03,
+	EXYNOS5_GPIO_F04,
+	EXYNOS5_GPIO_F05,
+	EXYNOS5_GPIO_F06,
+	EXYNOS5_GPIO_F07,
+	EXYNOS5_GPIO_F10,	/* 224 0xe0 */
+	EXYNOS5_GPIO_F11,
+	EXYNOS5_GPIO_F12,
+	EXYNOS5_GPIO_F13,
+	EXYNOS5_GPIO_F14,
+	EXYNOS5_GPIO_F15,
+	EXYNOS5_GPIO_F16,
+	EXYNOS5_GPIO_F17,
+	EXYNOS5_GPIO_G00,	/* 232 0xe8 */
+	EXYNOS5_GPIO_G01,
+	EXYNOS5_GPIO_G02,
+	EXYNOS5_GPIO_G03,
+	EXYNOS5_GPIO_G04,
+	EXYNOS5_GPIO_G05,
+	EXYNOS5_GPIO_G06,
+	EXYNOS5_GPIO_G07,
+	EXYNOS5_GPIO_G10,	/* 240 0xf0 */
+	EXYNOS5_GPIO_G11,
+	EXYNOS5_GPIO_G12,
+	EXYNOS5_GPIO_G13,
+	EXYNOS5_GPIO_G14,
+	EXYNOS5_GPIO_G15,
+	EXYNOS5_GPIO_G16,
+	EXYNOS5_GPIO_G17,
+	EXYNOS5_GPIO_G20,	/* 248 0xf8 */
+	EXYNOS5_GPIO_G21,
+	EXYNOS5_GPIO_G22,
+	EXYNOS5_GPIO_G23,
+	EXYNOS5_GPIO_G24,
+	EXYNOS5_GPIO_G25,
+	EXYNOS5_GPIO_G26,
+	EXYNOS5_GPIO_G27,
+	EXYNOS5_GPIO_H00,	/* 256 0x100 */
+	EXYNOS5_GPIO_H01,
+	EXYNOS5_GPIO_H02,
+	EXYNOS5_GPIO_H03,
+	EXYNOS5_GPIO_H04,
+	EXYNOS5_GPIO_H05,
+	EXYNOS5_GPIO_H06,
+	EXYNOS5_GPIO_H07,
+	EXYNOS5_GPIO_H10,	/* 264 0x108 */
+	EXYNOS5_GPIO_H11,
+	EXYNOS5_GPIO_H12,
+	EXYNOS5_GPIO_H13,
+	EXYNOS5_GPIO_H14,
+	EXYNOS5_GPIO_H15,
+	EXYNOS5_GPIO_H16,
+	EXYNOS5_GPIO_H17,
+
+	/* GPIO_PART4_STARTS */
+	EXYNOS5_GPIO_MAX_PORT_PART_4,	/* 272 0x110 */
+	EXYNOS5_GPIO_V00 = EXYNOS5_GPIO_MAX_PORT_PART_4,
+	EXYNOS5_GPIO_V01,
+	EXYNOS5_GPIO_V02,
+	EXYNOS5_GPIO_V03,
+	EXYNOS5_GPIO_V04,
+	EXYNOS5_GPIO_V05,
+	EXYNOS5_GPIO_V06,
+	EXYNOS5_GPIO_V07,
+	EXYNOS5_GPIO_V10,	/* 280 0x118 */
+	EXYNOS5_GPIO_V11,
+	EXYNOS5_GPIO_V12,
+	EXYNOS5_GPIO_V13,
+	EXYNOS5_GPIO_V14,
+	EXYNOS5_GPIO_V15,
+	EXYNOS5_GPIO_V16,
+	EXYNOS5_GPIO_V17,
+
+	/* GPIO_PART5_STARTS */
+	EXYNOS5_GPIO_MAX_PORT_PART_5,	/* 288 0x120 */
+	EXYNOS5_GPIO_V20 = EXYNOS5_GPIO_MAX_PORT_PART_5,
+	EXYNOS5_GPIO_V21,
+	EXYNOS5_GPIO_V22,
+	EXYNOS5_GPIO_V23,
+	EXYNOS5_GPIO_V24,
+	EXYNOS5_GPIO_V25,
+	EXYNOS5_GPIO_V26,
+	EXYNOS5_GPIO_V27,
+	EXYNOS5_GPIO_V30,	/* 296 0x128 */
+	EXYNOS5_GPIO_V31,
+	EXYNOS5_GPIO_V32,
+	EXYNOS5_GPIO_V33,
+	EXYNOS5_GPIO_V34,
+	EXYNOS5_GPIO_V35,
+	EXYNOS5_GPIO_V36,
+	EXYNOS5_GPIO_V37,
+
+	/* GPIO_PART6_STARTS */
+	EXYNOS5_GPIO_MAX_PORT_PART_6,	/* 304 0x130 */
+	EXYNOS5_GPIO_V40 = EXYNOS5_GPIO_MAX_PORT_PART_6,
+	EXYNOS5_GPIO_V41,
+	EXYNOS5_GPIO_V42,
+	EXYNOS5_GPIO_V43,
+	EXYNOS5_GPIO_V44,
+	EXYNOS5_GPIO_V45,
+	EXYNOS5_GPIO_V46,
+	EXYNOS5_GPIO_V47,
+
+	/* GPIO_PART7_STARTS */		/* 312 0x138 */
+	EXYNOS5_GPIO_MAX_PORT_PART_7,
+	EXYNOS5_GPIO_Z0 = EXYNOS5_GPIO_MAX_PORT_PART_7,
+	EXYNOS5_GPIO_Z1,
+	EXYNOS5_GPIO_Z2,
+	EXYNOS5_GPIO_Z3,
+	EXYNOS5_GPIO_Z4,
+	EXYNOS5_GPIO_Z5,
+	EXYNOS5_GPIO_Z6,
+	EXYNOS5_GPIO_MAX_PORT
+};
+
+enum exynos5420_gpio_pin {
+	/* GPIO_PART1_STARTS */
+	EXYNOS5420_GPIO_A00,	/* 0 */
+	EXYNOS5420_GPIO_A01,
+	EXYNOS5420_GPIO_A02,
+	EXYNOS5420_GPIO_A03,
+	EXYNOS5420_GPIO_A04,
+	EXYNOS5420_GPIO_A05,
+	EXYNOS5420_GPIO_A06,
+	EXYNOS5420_GPIO_A07,
+	EXYNOS5420_GPIO_A10,	/* 8 */
+	EXYNOS5420_GPIO_A11,
+	EXYNOS5420_GPIO_A12,
+	EXYNOS5420_GPIO_A13,
+	EXYNOS5420_GPIO_A14,
+	EXYNOS5420_GPIO_A15,
+	EXYNOS5420_GPIO_A16,
+	EXYNOS5420_GPIO_A17,
+	EXYNOS5420_GPIO_A20,	/* 16 0x10 */
+	EXYNOS5420_GPIO_A21,
+	EXYNOS5420_GPIO_A22,
+	EXYNOS5420_GPIO_A23,
+	EXYNOS5420_GPIO_A24,
+	EXYNOS5420_GPIO_A25,
+	EXYNOS5420_GPIO_A26,
+	EXYNOS5420_GPIO_A27,
+	EXYNOS5420_GPIO_B00,	/* 24 0x18 */
+	EXYNOS5420_GPIO_B01,
+	EXYNOS5420_GPIO_B02,
+	EXYNOS5420_GPIO_B03,
+	EXYNOS5420_GPIO_B04,
+	EXYNOS5420_GPIO_B05,
+	EXYNOS5420_GPIO_B06,
+	EXYNOS5420_GPIO_B07,
+	EXYNOS5420_GPIO_B10,	/* 32 0x20 */
+	EXYNOS5420_GPIO_B11,
+	EXYNOS5420_GPIO_B12,
+	EXYNOS5420_GPIO_B13,
+	EXYNOS5420_GPIO_B14,
+	EXYNOS5420_GPIO_B15,
+	EXYNOS5420_GPIO_B16,
+	EXYNOS5420_GPIO_B17,
+	EXYNOS5420_GPIO_B20,	/* 40 0x28 */
+	EXYNOS5420_GPIO_B21,
+	EXYNOS5420_GPIO_B22,
+	EXYNOS5420_GPIO_B23,
+	EXYNOS5420_GPIO_B24,
+	EXYNOS5420_GPIO_B25,
+	EXYNOS5420_GPIO_B26,
+	EXYNOS5420_GPIO_B27,
+	EXYNOS5420_GPIO_B30,	/* 48 0x30 */
+	EXYNOS5420_GPIO_B31,
+	EXYNOS5420_GPIO_B32,
+	EXYNOS5420_GPIO_B33,
+	EXYNOS5420_GPIO_B34,
+	EXYNOS5420_GPIO_B35,
+	EXYNOS5420_GPIO_B36,
+	EXYNOS5420_GPIO_B37,
+	EXYNOS5420_GPIO_B40,	/* 56 0x38 */
+	EXYNOS5420_GPIO_B41,
+	EXYNOS5420_GPIO_B42,
+	EXYNOS5420_GPIO_B43,
+	EXYNOS5420_GPIO_B44,
+	EXYNOS5420_GPIO_B45,
+	EXYNOS5420_GPIO_B46,
+	EXYNOS5420_GPIO_B47,
+	EXYNOS5420_GPIO_H00,	/* 64 0x40 */
+	EXYNOS5420_GPIO_H01,
+	EXYNOS5420_GPIO_H02,
+	EXYNOS5420_GPIO_H03,
+	EXYNOS5420_GPIO_H04,
+	EXYNOS5420_GPIO_H05,
+	EXYNOS5420_GPIO_H06,
+	EXYNOS5420_GPIO_H07,
+
+	/* GPIO PART 2 STARTS*/
+	EXYNOS5420_GPIO_MAX_PORT_PART_1,	/* 72 0x48 */
+	EXYNOS5420_GPIO_Y70 = EXYNOS5420_GPIO_MAX_PORT_PART_1,
+	EXYNOS5420_GPIO_Y71,
+	EXYNOS5420_GPIO_Y72,
+	EXYNOS5420_GPIO_Y73,
+	EXYNOS5420_GPIO_Y74,
+	EXYNOS5420_GPIO_Y75,
+	EXYNOS5420_GPIO_Y76,
+	EXYNOS5420_GPIO_Y77,
+
+	/* GPIO PART 3 STARTS*/
+	EXYNOS5420_GPIO_MAX_PORT_PART_2,	/* 80 0x50 */
+	EXYNOS5420_GPIO_X00 = EXYNOS5420_GPIO_MAX_PORT_PART_2,
+	EXYNOS5420_GPIO_X01,
+	EXYNOS5420_GPIO_X02,
+	EXYNOS5420_GPIO_X03,
+	EXYNOS5420_GPIO_X04,
+	EXYNOS5420_GPIO_X05,
+	EXYNOS5420_GPIO_X06,
+	EXYNOS5420_GPIO_X07,
+	EXYNOS5420_GPIO_X10,	/* 88 0x58 */
+	EXYNOS5420_GPIO_X11,
+	EXYNOS5420_GPIO_X12,
+	EXYNOS5420_GPIO_X13,
+	EXYNOS5420_GPIO_X14,
+	EXYNOS5420_GPIO_X15,
+	EXYNOS5420_GPIO_X16,
+	EXYNOS5420_GPIO_X17,
+	EXYNOS5420_GPIO_X20,	/* 96 0x60 */
+	EXYNOS5420_GPIO_X21,
+	EXYNOS5420_GPIO_X22,
+	EXYNOS5420_GPIO_X23,
+	EXYNOS5420_GPIO_X24,
+	EXYNOS5420_GPIO_X25,
+	EXYNOS5420_GPIO_X26,
+	EXYNOS5420_GPIO_X27,
+	EXYNOS5420_GPIO_X30,	/* 104 0x68 */
+	EXYNOS5420_GPIO_X31,
+	EXYNOS5420_GPIO_X32,
+	EXYNOS5420_GPIO_X33,
+	EXYNOS5420_GPIO_X34,
+	EXYNOS5420_GPIO_X35,
+	EXYNOS5420_GPIO_X36,
+	EXYNOS5420_GPIO_X37,
+
+	/* GPIO PART 4 STARTS*/
+	EXYNOS5420_GPIO_MAX_PORT_PART_3,	/* 112 0x70 */
+	EXYNOS5420_GPIO_C00 = EXYNOS5420_GPIO_MAX_PORT_PART_3,
+	EXYNOS5420_GPIO_C01,
+	EXYNOS5420_GPIO_C02,
+	EXYNOS5420_GPIO_C03,
+	EXYNOS5420_GPIO_C04,
+	EXYNOS5420_GPIO_C05,
+	EXYNOS5420_GPIO_C06,
+	EXYNOS5420_GPIO_C07,
+	EXYNOS5420_GPIO_C10,	/* 120 0x78 */
+	EXYNOS5420_GPIO_C11,
+	EXYNOS5420_GPIO_C12,
+	EXYNOS5420_GPIO_C13,
+	EXYNOS5420_GPIO_C14,
+	EXYNOS5420_GPIO_C15,
+	EXYNOS5420_GPIO_C16,
+	EXYNOS5420_GPIO_C17,
+	EXYNOS5420_GPIO_C20,	/* 128 0x80 */
+	EXYNOS5420_GPIO_C21,
+	EXYNOS5420_GPIO_C22,
+	EXYNOS5420_GPIO_C23,
+	EXYNOS5420_GPIO_C24,
+	EXYNOS5420_GPIO_C25,
+	EXYNOS5420_GPIO_C26,
+	EXYNOS5420_GPIO_C27,
+	EXYNOS5420_GPIO_C30,	/* 136 0x88 */
+	EXYNOS5420_GPIO_C31,
+	EXYNOS5420_GPIO_C32,
+	EXYNOS5420_GPIO_C33,
+	EXYNOS5420_GPIO_C34,
+	EXYNOS5420_GPIO_C35,
+	EXYNOS5420_GPIO_C36,
+	EXYNOS5420_GPIO_C37,
+	EXYNOS5420_GPIO_C40,	/* 144 0x90 */
+	EXYNOS5420_GPIO_C41,
+	EXYNOS5420_GPIO_C42,
+	EXYNOS5420_GPIO_C43,
+	EXYNOS5420_GPIO_C44,
+	EXYNOS5420_GPIO_C45,
+	EXYNOS5420_GPIO_C46,
+	EXYNOS5420_GPIO_C47,
+	EXYNOS5420_GPIO_D10,	/* 152 0x98 */
+	EXYNOS5420_GPIO_D11,
+	EXYNOS5420_GPIO_D12,
+	EXYNOS5420_GPIO_D13,
+	EXYNOS5420_GPIO_D14,
+	EXYNOS5420_GPIO_D15,
+	EXYNOS5420_GPIO_D16,
+	EXYNOS5420_GPIO_D17,
+	EXYNOS5420_GPIO_Y00,	/* 160 0xa0 */
+	EXYNOS5420_GPIO_Y01,
+	EXYNOS5420_GPIO_Y02,
+	EXYNOS5420_GPIO_Y03,
+	EXYNOS5420_GPIO_Y04,
+	EXYNOS5420_GPIO_Y05,
+	EXYNOS5420_GPIO_Y06,
+	EXYNOS5420_GPIO_Y07,
+	EXYNOS5420_GPIO_Y10,	/* 168 0xa8 */
+	EXYNOS5420_GPIO_Y11,
+	EXYNOS5420_GPIO_Y12,
+	EXYNOS5420_GPIO_Y13,
+	EXYNOS5420_GPIO_Y14,
+	EXYNOS5420_GPIO_Y15,
+	EXYNOS5420_GPIO_Y16,
+	EXYNOS5420_GPIO_Y17,
+	EXYNOS5420_GPIO_Y20,	/* 176 0xb0 */
+	EXYNOS5420_GPIO_Y21,
+	EXYNOS5420_GPIO_Y22,
+	EXYNOS5420_GPIO_Y23,
+	EXYNOS5420_GPIO_Y24,
+	EXYNOS5420_GPIO_Y25,
+	EXYNOS5420_GPIO_Y26,
+	EXYNOS5420_GPIO_Y27,
+	EXYNOS5420_GPIO_Y30,	/* 184 0xb8 */
+	EXYNOS5420_GPIO_Y31,
+	EXYNOS5420_GPIO_Y32,
+	EXYNOS5420_GPIO_Y33,
+	EXYNOS5420_GPIO_Y34,
+	EXYNOS5420_GPIO_Y35,
+	EXYNOS5420_GPIO_Y36,
+	EXYNOS5420_GPIO_Y37,
+	EXYNOS5420_GPIO_Y40,	/* 192 0xc0 */
+	EXYNOS5420_GPIO_Y41,
+	EXYNOS5420_GPIO_Y42,
+	EXYNOS5420_GPIO_Y43,
+	EXYNOS5420_GPIO_Y44,
+	EXYNOS5420_GPIO_Y45,
+	EXYNOS5420_GPIO_Y46,
+	EXYNOS5420_GPIO_Y47,
+	EXYNOS5420_GPIO_Y50,	/* 200 0xc8 */
+	EXYNOS5420_GPIO_Y51,
+	EXYNOS5420_GPIO_Y52,
+	EXYNOS5420_GPIO_Y53,
+	EXYNOS5420_GPIO_Y54,
+	EXYNOS5420_GPIO_Y55,
+	EXYNOS5420_GPIO_Y56,
+	EXYNOS5420_GPIO_Y57,
+	EXYNOS5420_GPIO_Y60,	/* 208 0xd0 */
+	EXYNOS5420_GPIO_Y61,
+	EXYNOS5420_GPIO_Y62,
+	EXYNOS5420_GPIO_Y63,
+	EXYNOS5420_GPIO_Y64,
+	EXYNOS5420_GPIO_Y65,
+	EXYNOS5420_GPIO_Y66,
+	EXYNOS5420_GPIO_Y67,
+
+	/* GPIO_PART5_STARTS */
+	EXYNOS5420_GPIO_MAX_PORT_PART_4,	/* 216 0xd8 */
+	EXYNOS5420_GPIO_E00 = EXYNOS5420_GPIO_MAX_PORT_PART_4,
+	EXYNOS5420_GPIO_E01,
+	EXYNOS5420_GPIO_E02,
+	EXYNOS5420_GPIO_E03,
+	EXYNOS5420_GPIO_E04,
+	EXYNOS5420_GPIO_E05,
+	EXYNOS5420_GPIO_E06,
+	EXYNOS5420_GPIO_E07,
+	EXYNOS5420_GPIO_E10,	/* 224 0xe0 */
+	EXYNOS5420_GPIO_E11,
+	EXYNOS5420_GPIO_E12,
+	EXYNOS5420_GPIO_E13,
+	EXYNOS5420_GPIO_E14,
+	EXYNOS5420_GPIO_E15,
+	EXYNOS5420_GPIO_E16,
+	EXYNOS5420_GPIO_E17,
+	EXYNOS5420_GPIO_F00,	/* 232 0xe8 */
+	EXYNOS5420_GPIO_F01,
+	EXYNOS5420_GPIO_F02,
+	EXYNOS5420_GPIO_F03,
+	EXYNOS5420_GPIO_F04,
+	EXYNOS5420_GPIO_F05,
+	EXYNOS5420_GPIO_F06,
+	EXYNOS5420_GPIO_F07,
+	EXYNOS5420_GPIO_F10,	/* 240 0xf0 */
+	EXYNOS5420_GPIO_F11,
+	EXYNOS5420_GPIO_F12,
+	EXYNOS5420_GPIO_F13,
+	EXYNOS5420_GPIO_F14,
+	EXYNOS5420_GPIO_F15,
+	EXYNOS5420_GPIO_F16,
+	EXYNOS5420_GPIO_F17,
+	EXYNOS5420_GPIO_G00,	/* 248 0xf8 */
+	EXYNOS5420_GPIO_G01,
+	EXYNOS5420_GPIO_G02,
+	EXYNOS5420_GPIO_G03,
+	EXYNOS5420_GPIO_G04,
+	EXYNOS5420_GPIO_G05,
+	EXYNOS5420_GPIO_G06,
+	EXYNOS5420_GPIO_G07,
+	EXYNOS5420_GPIO_G10,	/* 256 0x100 */
+	EXYNOS5420_GPIO_G11,
+	EXYNOS5420_GPIO_G12,
+	EXYNOS5420_GPIO_G13,
+	EXYNOS5420_GPIO_G14,
+	EXYNOS5420_GPIO_G15,
+	EXYNOS5420_GPIO_G16,
+	EXYNOS5420_GPIO_G17,
+	EXYNOS5420_GPIO_G20,	/* 264 0x108 */
+	EXYNOS5420_GPIO_G21,
+	EXYNOS5420_GPIO_G22,
+	EXYNOS5420_GPIO_G23,
+	EXYNOS5420_GPIO_G24,
+	EXYNOS5420_GPIO_G25,
+	EXYNOS5420_GPIO_G26,
+	EXYNOS5420_GPIO_G27,
+	EXYNOS5420_GPIO_J40,	/* 272 0x110 */
+	EXYNOS5420_GPIO_J41,
+	EXYNOS5420_GPIO_J42,
+	EXYNOS5420_GPIO_J43,
+	EXYNOS5420_GPIO_J44,
+	EXYNOS5420_GPIO_J45,
+	EXYNOS5420_GPIO_J46,
+	EXYNOS5420_GPIO_J47,
+
+	/* GPIO_PART6_STARTS */
+	EXYNOS5420_GPIO_MAX_PORT_PART_5,	/* 280 0x118 */
+	EXYNOS5420_GPIO_Z0 = EXYNOS5420_GPIO_MAX_PORT_PART_5,
+	EXYNOS5420_GPIO_Z1,
+	EXYNOS5420_GPIO_Z2,
+	EXYNOS5420_GPIO_Z3,
+	EXYNOS5420_GPIO_Z4,
+	EXYNOS5420_GPIO_Z5,
+	EXYNOS5420_GPIO_Z6,
+	EXYNOS5420_GPIO_MAX_PORT
+};
+struct gpio_info {
+	unsigned int reg_addr;	/* Address of register for this part */
+	unsigned int max_gpio;	/* Maximum GPIO in this part */
+};
+
+#define EXYNOS5_GPIO_NUM_PARTS	8
+static struct gpio_info exynos5_gpio_data[EXYNOS5_GPIO_NUM_PARTS] = {
+	{ EXYNOS5_GPIO_PART1_BASE, EXYNOS5_GPIO_MAX_PORT_PART_1 },
+	{ EXYNOS5_GPIO_PART2_BASE, EXYNOS5_GPIO_MAX_PORT_PART_2 },
+	{ EXYNOS5_GPIO_PART3_BASE, EXYNOS5_GPIO_MAX_PORT_PART_3 },
+	{ EXYNOS5_GPIO_PART4_BASE, EXYNOS5_GPIO_MAX_PORT_PART_4 },
+	{ EXYNOS5_GPIO_PART5_BASE, EXYNOS5_GPIO_MAX_PORT_PART_5 },
+	{ EXYNOS5_GPIO_PART6_BASE, EXYNOS5_GPIO_MAX_PORT_PART_6 },
+	{ EXYNOS5_GPIO_PART7_BASE, EXYNOS5_GPIO_MAX_PORT_PART_7 },
+	{ EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT },
+};
+
+#define EXYNOS5420_GPIO_NUM_PARTS	6
+static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = {
+	{ EXYNOS5420_GPIO_PART1_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_1 },
+	{ EXYNOS5420_GPIO_PART2_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_2 },
+	{ EXYNOS5420_GPIO_PART3_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_3 },
+	{ EXYNOS5420_GPIO_PART4_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_4 },
+	{ EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_5 },
+	{ EXYNOS5420_GPIO_PART6_BASE, EXYNOS5420_GPIO_MAX_PORT },
+};
+
+static inline struct gpio_info *get_gpio_data(void)
+{
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return exynos5420_gpio_data;
+		else
+			return exynos5_gpio_data;
+	} else {
+		return NULL;
+	}
+}
+
+static inline unsigned int get_bank_num(void)
+{
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return EXYNOS5420_GPIO_NUM_PARTS;
+		else
+			return EXYNOS5_GPIO_NUM_PARTS;
+	} else {
+		return 0;
+	}
+}
+
+void gpio_cfg_pin(int gpio, int cfg);
+void gpio_set_pull(int gpio, int mode);
+void gpio_set_drv(int gpio, int mode);
+int gpio_direction_output(unsigned gpio, int value);
+int gpio_set_value(unsigned gpio, int value);
 #endif
 
 /* Pin configurations */
diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c
index 379a45c..58821c4 100644
--- a/board/samsung/smdk5250/exynos5-dt.c
+++ b/board/samsung/smdk5250/exynos5-dt.c
@@ -27,12 +27,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_SOUND_MAX98095
 static void board_enable_audio_codec(void)
 {
-	struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
-						samsung_get_base_gpio_part1();
-
 	/* Enable MAX98095 Codec */
-	s5p_gpio_direction_output(&gpio1->x1, 7, 1);
-	s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
+	gpio_direction_output(EXYNOS5_GPIO_X17, 1);
+	gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
 }
 #endif
 
@@ -47,19 +44,16 @@ int exynos_init(void)
 #ifdef CONFIG_LCD
 void exynos_cfg_lcd_gpio(void)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
-
 	/* For Backlight */
-	s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
-	s5p_gpio_set_value(&gpio1->b2, 0, 1);
+	gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
+	gpio_set_value(EXYNOS5_GPIO_B20, 1);
 
 	/* LCD power on */
-	s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
-	s5p_gpio_set_value(&gpio1->x1, 5, 1);
+	gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT);
+	gpio_set_value(EXYNOS5_GPIO_X15, 1);
 
 	/* Set Hotplug detect for DP */
-	s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+	gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
 }
 
 void exynos_set_dp_phy(unsigned int onoff)
diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c
index 28a6d9e..bdfb49f 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -29,12 +29,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_SOUND_MAX98095
 static void  board_enable_audio_codec(void)
 {
-	struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
-						samsung_get_base_gpio_part1();
-
 	/* Enable MAX98095 Codec */
-	s5p_gpio_direction_output(&gpio1->x1, 7, 1);
-	s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
+	gpio_direction_output(EXYNOS5_GPIO_X17, 1);
+	gpio_set_pull(EXYNOS5_GPIO_X17, GPIO_PULL_NONE);
 }
 #endif
 
@@ -275,19 +272,17 @@ int exynos_power_init(void)
 #ifdef CONFIG_LCD
 void exynos_cfg_lcd_gpio(void)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 
 	/* For Backlight */
-	s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
-	s5p_gpio_set_value(&gpio1->b2, 0, 1);
+	gpio_cfg_pin(EXYNOS5_GPIO_B20, GPIO_OUTPUT);
+	gpio_set_value(EXYNOS5_GPIO_B20, 1);
 
 	/* LCD power on */
-	s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
-	s5p_gpio_set_value(&gpio1->x1, 5, 1);
+	gpio_cfg_pin(EXYNOS5_GPIO_X15, GPIO_OUTPUT);
+	gpio_set_value(EXYNOS5_GPIO_X15, 1);
 
 	/* Set Hotplug detect for DP */
-	s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+	gpio_cfg_pin(EXYNOS5_GPIO_X07, GPIO_FUNC(0x3));
 }
 
 void exynos_set_dp_phy(unsigned int onoff)
diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c
index e4606ec..fa3aa2c 100644
--- a/board/samsung/smdk5420/smdk5420.c
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -21,11 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_USB_EHCI_EXYNOS
 static int board_usb_vbus_init(void)
 {
-	struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
-						samsung_get_base_gpio_part1();
-
 	/* Enable VBUS power switch */
-	s5p_gpio_direction_output(&gpio1->x2, 6, 1);
+	gpio_direction_output(EXYNOS5420_GPIO_X26, 1);
 
 	/* VBUS turn ON time */
 	mdelay(3);
@@ -49,15 +46,15 @@ void cfg_lcd_gpio(void)
 		(struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
 
 	/* For Backlight */
-	s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
-	s5p_gpio_set_value(&gpio1->b2, 0, 1);
+	gpio_cfg_pin(EXYNOS5420_GPIO_B10, S5P_GPIO_OUTPUT);
+	gpio_set_value(EXYNOS5420_GPIO_B20, 1);
 
 	/* LCD power on */
-	s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
-	s5p_gpio_set_value(&gpio1->x1, 5, 1);
+	gpio_cfg_pin(EXYNOS5420_GPIO_X15, S5P_GPIO_OUTPUT);
+	gpio_set_value(EXYNOS5420_GPIO_X15, 1);
 
 	/* Set Hotplug detect for DP */
-	s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+	gpio_cfg_pin(EXYNOS5420_GPIO_X07, S5P_GPIO_FUNC(0x3));
 }
 
 vidinfo_t panel_info = {
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index 11a0472..c29a04a 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -12,7 +12,7 @@
 #define S5P_GPIO_GET_BANK(x)	((x >> S5P_GPIO_BANK_SHIFT) \
 				& S5P_GPIO_BANK_MASK)
 
-#define S5P_GPIO_GET_PIN(x)	(x & S5P_GPIO_PIN_MASK)
+#define S5P_GPIO_GET_PIN(x)	((x & S5P_GPIO_PIN_MASK) % GPIO_PER_BANK)
 
 #define CON_MASK(x)		(0xf << ((x) << 2))
 #define CON_SFR(x, v)		((v) << ((x) << 2))
@@ -127,6 +127,29 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
 	writel(value, &bank->drv);
 }
 
+#ifdef HAVE_GENERIC_GPIO
+static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
+{
+	const struct gpio_info *data;
+	unsigned int upto;
+	int i, count;
+
+	data = get_gpio_data();
+	count = get_bank_num();
+	for (i = upto = 0; i < count;
+			i++, upto = data->max_gpio, data++) {
+		debug("i=%d, upto=%d\n", i, upto);
+		if (gpio < data->max_gpio) {
+			struct s5p_gpio_bank *bank;
+			bank = (struct s5p_gpio_bank *)data->reg_addr;
+			bank += (gpio - upto) / GPIO_PER_BANK;
+			debug("gpio=%d, bank=%p\n", gpio, bank);
+			return bank;
+		}
+	}
+	return NULL;
+}
+#else
 struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
 {
 	unsigned bank = S5P_GPIO_GET_BANK(gpio);
@@ -134,6 +157,7 @@ struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
 
 	return (struct s5p_gpio_bank *)(base + bank);
 }
+#endif
 
 int s5p_gpio_get_pin(unsigned gpio)
 {
@@ -179,3 +203,21 @@ int gpio_set_value(unsigned gpio, int value)
 
 	return 0;
 }
+
+void gpio_set_pull(int gpio, int mode)
+{
+	s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
+			  s5p_gpio_get_pin(gpio), mode);
+}
+
+void gpio_set_drv(int gpio, int mode)
+{
+	s5p_gpio_set_drv(s5p_gpio_get_bank(gpio),
+			 s5p_gpio_get_pin(gpio), mode);
+}
+
+void gpio_cfg_pin(int gpio, int cfg)
+{
+	s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio),
+			 s5p_gpio_get_pin(gpio), cfg);
+}
-- 
1.8.3.2

[U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature

[Simon Glass]

On 12 April 2014 02:43, Akshay Saraswat <akshay.s@samsung.com> wrote:

> From: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>
> This patch adds gpio pin numbering support for EXYNOS 5250 & 5420.
> To have consistent 0..n-1 GPIO numbering the banks are divided
> into different parts where ever they have holes in them.
>
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
>

Acked-by: Simon Glass <sjg@chromium.org>

Tested on snow with backlight GPIOs.

[U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature

[Lukasz Majewski]

Hi Akshay,

I'm not Samsung tree maintainer, but by chance I've come across those
patches and...

First question - why have you omitted u-boot-samsung tree maintainer?
I've added Minkyu to CC.

Also in the cover letter you claim that this patch was "build tested"
for Exynos4 based boards. Why didn't you add at least one maintainer of
those boards to CC?

> +
> +/* A list of valid GPIO numbers for the asm-generic/gpio.h interface
> */ +enum exynos5_gpio_pin {
> +	/* GPIO_PART1_STARTS */
> +	EXYNOS5_GPIO_A00,	/* 0 */
> +	EXYNOS5_GPIO_A01,
> +	EXYNOS5_GPIO_A02,
> +	EXYNOS5_GPIO_A03,
> +	EXYNOS5_GPIO_A04,

According to the patch description, you had a compilation error when
were adding the support for Exynos 5250 and 5420. Why you fix the
problem by rewriting the whole framework?

IN the patch 2/4 you have:

-		gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
-		gpio_set_pull(start + i, GPIO_PULL_NONE);
-		gpio_set_drv(start + i, GPIO_DRV_4X);
+		gpio_cfg_pin(start + i, S5P_GPIO_FUNC(0x2));
+		gpio_set_pull(start + i, S5P_GPIO_PULL_NONE);
+		gpio_set_drv(start + i, S5P_GPIO_DRV_4X);

What is the rationale to change the name to S5P_GPIO and not stick to
GPIO_FUNC? In which way gpios for Exynos5 are different than for
Exynos4? Cannot we finally reuse the Exynos 4 and 5 code?


With the same patch:

-  	case PERIPH_ID_UART1:
-		bank = &gpio1->d0;
-		start = 0;
+		start = EXYNOS5_GPIO_D00;

What is wrong with specifying the bank field? 
Why your gpio command cannot use the bank approach?

And one more question: Is this work compliant with new driver model,
which will be accepted at the merge window after the v2014.04 release?

If not, then there is no point to review this code, since GPIO would
need to be adjusted to use this framework.

--
Best regards,

Lukasz Majewski

Samsung R&D Institute Poland (SRPOL) | Linux Platform Group

[U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature

[Akshay Saraswat]

Hi Lukasz,

>Hi Akshay,
>
>I'm not Samsung tree maintainer, but by chance I've come across those
>patches and...
>
>First question - why have you omitted u-boot-samsung tree maintainer?
>I've added Minkyu to CC.
>

Minkyu has an email ID "promsoft at gmail.com" and I added that in CC.
Probably you don't know this email id :-)

>
>Also in the cover letter you claim that this patch was "build tested"
>for Exynos4 based boards. Why didn't you add at least one maintainer of
>those boards to CC?
>

In cover letter I have not mentioned anywhere that I have built or tested
these patches over Exynos4. Patch 2/4 says "Build tested" because Rajeshwari
did build images for Exynos4 boards and that was successfull but nobody tested
booting those images.
I do not possess any Exynos4 board. These patches are meant for Exynos5 only.
But Yes, there are compiler errors introduced for smkc100 because of this new
patch-set and I will fix them in the next patch-set.

>
>> +
>> +/* A list of valid GPIO numbers for the asm-generic/gpio.h interface
>> */ +enum exynos5_gpio_pin {
>> +	/* GPIO_PART1_STARTS */
>> +	EXYNOS5_GPIO_A00,	/* 0 */
>> +	EXYNOS5_GPIO_A01,
>> +	EXYNOS5_GPIO_A02,
>> +	EXYNOS5_GPIO_A03,
>> +	EXYNOS5_GPIO_A04,
>
>According to the patch description, you had a compilation error when
>were adding the support for Exynos 5250 and 5420. Why you fix the
>problem by rewriting the whole framework?
>

This framework is not intended to fix compiler warnings or errors but to make
GPIO numbering easy to remember and sequential, without any holes in between.

>
>IN the patch 2/4 you have:
>
>-		gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
>-		gpio_set_pull(start + i, GPIO_PULL_NONE);
>-		gpio_set_drv(start + i, GPIO_DRV_4X);
>+		gpio_cfg_pin(start + i, S5P_GPIO_FUNC(0x2));
>+		gpio_set_pull(start + i, S5P_GPIO_PULL_NONE);
>+		gpio_set_drv(start + i, S5P_GPIO_DRV_4X);
>
>What is the rationale to change the name to S5P_GPIO and not stick to
>GPIO_FUNC? In which way gpios for Exynos5 are different than for
>Exynos4? Cannot we finally reuse the Exynos 4 and 5 code?
>

We have enum member GPIO_INPUT in common/cmd_gpio.c and GPIO_INPUT define
in arch-exynos/gpio.h. To remove such conflicts we renamed all s5p defines
from "GPIO_*" to "S5P_GPIO_*".
We are using the same s5p_gpio.c for both Exynos4 and 5 as far as I know.
I dont get the exact issue here. Do you want me to remove "S5P_". Is that it ?

>
>With the same patch:
>
>-  	case PERIPH_ID_UART1:
>-		bank = &gpio1->d0;
>-		start = 0;
>+		start = EXYNOS5_GPIO_D00;
>
>What is wrong with specifying the bank field? 
>Why your gpio command cannot use the bank approach?
>

Ultimately we are using banks and pin_nums specific to the bank only
after we extract exact bank from the sequential pin_num.

>
>And one more question: Is this work compliant with new driver model,
>which will be accepted at the merge window after the v2014.04 release?
>
>
>If not, then there is no point to review this code, since GPIO would
>need to be adjusted to use this framework.
>

Please explain more. I don't get this as well :-)

>--
>Best regards,
>
>Lukasz Majewski
>
>Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
>

Regards,
Akshay Saraswat

[U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature

[Lukasz Majewski]

Hi Akshay,

> Hi Lukasz,
> 
> >Hi Akshay,
> >
> >I'm not Samsung tree maintainer, but by chance I've come across those
> >patches and...
> >
> >First question - why have you omitted u-boot-samsung tree maintainer?
> >I've added Minkyu to CC.
> >
> 
> Minkyu has an email ID "promsoft at gmail.com" and I added that in CC.
> Probably you don't know this email id :-)

I do know it :-), but this is not the official one.

Adding involved people to CC really speed up things :-)

> 
> >
> >Also in the cover letter you claim that this patch was "build tested"
> >for Exynos4 based boards. Why didn't you add at least one maintainer
> >of those boards to CC?
> >
> 
> In cover letter I have not mentioned anywhere that I have built or
> tested these patches over Exynos4. 
> Patch 2/4 says "Build tested"
> because Rajeshwari did build images for Exynos4 boards and that was
> successfull but nobody tested booting those images.

As Przemek written to you in the other mail. There is a build problem
with trats2/trats boards.

> I do not possess any Exynos4 board. 

That is why it is a good practice to ask maintainer's of those boards
to test it for you. 

> These patches are meant for
> Exynos5 only.

We will probably go with your approach to make (_finally_) the gpio code
consistent for Exynos4/5.

> But Yes, there are compiler errors introduced for
> smkc100 because of this new patch-set and I will fix them in the next
> patch-set.

I'm a bit confused now. Was this patch set build tested or not? 

> 
> >
> >> +
> >> +/* A list of valid GPIO numbers for the asm-generic/gpio.h
> >> interface */ +enum exynos5_gpio_pin {
> >> +	/* GPIO_PART1_STARTS */
> >> +	EXYNOS5_GPIO_A00,	/* 0 */
> >> +	EXYNOS5_GPIO_A01,
> >> +	EXYNOS5_GPIO_A02,
> >> +	EXYNOS5_GPIO_A03,
> >> +	EXYNOS5_GPIO_A04,
> >
> >According to the patch description, you had a compilation error when
> >were adding the support for Exynos 5250 and 5420. Why you fix the
> >problem by rewriting the whole framework?
> >
> 
> This framework is not intended to fix compiler warnings or errors but
> to make GPIO numbering easy to remember and sequential, without any
> holes in between.

Samsung boards were swinging from part+bank+pin number approach to
sequential GPIO number from time to time. I think it is a good
time to clean things up. 

> 
> >
> >IN the patch 2/4 you have:
> >
> >-		gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
> >-		gpio_set_pull(start + i, GPIO_PULL_NONE);
> >-		gpio_set_drv(start + i, GPIO_DRV_4X);
> >+		gpio_cfg_pin(start + i, S5P_GPIO_FUNC(0x2));
> >+		gpio_set_pull(start + i, S5P_GPIO_PULL_NONE);
> >+		gpio_set_drv(start + i, S5P_GPIO_DRV_4X);
> >
> >What is the rationale to change the name to S5P_GPIO and not stick to
> >GPIO_FUNC? In which way gpios for Exynos5 are different than for
> >Exynos4? Cannot we finally reuse the Exynos 4 and 5 code?
> >
> 
> We have enum member GPIO_INPUT in common/cmd_gpio.c and GPIO_INPUT
> define in arch-exynos/gpio.h. To remove such conflicts we renamed all
> s5p defines from "GPIO_*" to "S5P_GPIO_*".
> We are using the same s5p_gpio.c for both Exynos4 and 5 as far as I
> know. I dont get the exact issue here. Do you want me to remove
> "S5P_". Is that it ?

S5P_ corresponds to at most Exynos4 SoC (Up till S5PV310). However,
since the file is named s5p_gpio.c, then I think that S5P_ is a
appropriate prefix.

> 
> >
> >With the same patch:
> >
> >-  	case PERIPH_ID_UART1:
> >-		bank = &gpio1->d0;
> >-		start = 0;
> >+		start = EXYNOS5_GPIO_D00;
> >
> >What is wrong with specifying the bank field? 
> >Why your gpio command cannot use the bank approach?
> >
> 
> Ultimately we are using banks and pin_nums specific to the bank only
> after we extract exact bank from the sequential pin_num.

Ok.

> 
> >
> >And one more question: Is this work compliant with new driver model,
> >which will be accepted at the merge window after the v2014.04
> >release?
> >
> >
> >If not, then there is no point to review this code, since GPIO would
> >need to be adjusted to use this framework.
> >
> 
> Please explain more. I don't get this as well :-)

My point is that the new driver model (introduced by Simon) is going to
be included. I'm concern if after introduction of it we would need to
rewrite the gpio code to comply with it.

> 
> >--
> >Best regards,
> >
> >Lukasz Majewski
> >
> >Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
> >
> 
> Regards,
> Akshay Saraswat



-- 
Best regards,

Lukasz Majewski

Samsung R&D Institute Poland (SRPOL) | Linux Platform Group

[U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature

[Minkyu Kang]

Dear Akshay,

On 14/04/14 19:53, Lukasz Majewski wrote:
> Hi Akshay,
> 
>> Hi Lukasz,
>>
>>> Hi Akshay,
>>>
>>> I'm not Samsung tree maintainer, but by chance I've come across those
>>> patches and...
>>>
>>> First question - why have you omitted u-boot-samsung tree maintainer?
>>> I've added Minkyu to CC.
>>>
>>
>> Minkyu has an email ID "promsoft at gmail.com" and I added that in CC.
>> Probably you don't know this email id :-)
> 
> I do know it :-), but this is not the official one.
> 
> Adding involved people to CC really speed up things :-)
> 

I am always sensing about SAMSUNG related patches.
Please don't worry about it :)

>>
>>>
>>> Also in the cover letter you claim that this patch was "build tested"
>>> for Exynos4 based boards. Why didn't you add at least one maintainer
>>> of those boards to CC?
>>>
>>
>> In cover letter I have not mentioned anywhere that I have built or
>> tested these patches over Exynos4. 
>> Patch 2/4 says "Build tested"
>> because Rajeshwari did build images for Exynos4 boards and that was
>> successfull but nobody tested booting those images.
> 
> As Przemek written to you in the other mail. There is a build problem
> with trats2/trats boards.

Please fix it.

> 
>> I do not possess any Exynos4 board. 
> 
> That is why it is a good practice to ask maintainer's of those boards
> to test it for you. 
> 
>> These patches are meant for
>> Exynos5 only.

No. please consider Exynos4 also.
If you make patches for Exynos4 too, then it will be great job.
Przemek or Lukasz will help your test.

> 
> We will probably go with your approach to make (_finally_) the gpio code
> consistent for Exynos4/5.
> 
>> But Yes, there are compiler errors introduced for
>> smkc100 because of this new patch-set and I will fix them in the next
>> patch-set.

next patch-set means v7? right?

> 
> I'm a bit confused now. Was this patch set build tested or not? 
> 
>>
>>>
>>>> +
>>>> +/* A list of valid GPIO numbers for the asm-generic/gpio.h
>>>> interface */ +enum exynos5_gpio_pin {
>>>> +	/* GPIO_PART1_STARTS */
>>>> +	EXYNOS5_GPIO_A00,	/* 0 */
>>>> +	EXYNOS5_GPIO_A01,
>>>> +	EXYNOS5_GPIO_A02,
>>>> +	EXYNOS5_GPIO_A03,
>>>> +	EXYNOS5_GPIO_A04,
>>>
>>> According to the patch description, you had a compilation error when
>>> were adding the support for Exynos 5250 and 5420. Why you fix the
>>> problem by rewriting the whole framework?
>>>
>>
>> This framework is not intended to fix compiler warnings or errors but
>> to make GPIO numbering easy to remember and sequential, without any
>> holes in between.
> 
> Samsung boards were swinging from part+bank+pin number approach to
> sequential GPIO number from time to time. I think it is a good
> time to clean things up. 
> 
>>
>>>
>>> IN the patch 2/4 you have:
>>>
>>> -		gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
>>> -		gpio_set_pull(start + i, GPIO_PULL_NONE);
>>> -		gpio_set_drv(start + i, GPIO_DRV_4X);
>>> +		gpio_cfg_pin(start + i, S5P_GPIO_FUNC(0x2));
>>> +		gpio_set_pull(start + i, S5P_GPIO_PULL_NONE);
>>> +		gpio_set_drv(start + i, S5P_GPIO_DRV_4X);
>>>
>>> What is the rationale to change the name to S5P_GPIO and not stick to
>>> GPIO_FUNC? In which way gpios for Exynos5 are different than for
>>> Exynos4? Cannot we finally reuse the Exynos 4 and 5 code?
>>>
>>
>> We have enum member GPIO_INPUT in common/cmd_gpio.c and GPIO_INPUT
>> define in arch-exynos/gpio.h. To remove such conflicts we renamed all
>> s5p defines from "GPIO_*" to "S5P_GPIO_*".
>> We are using the same s5p_gpio.c for both Exynos4 and 5 as far as I
>> know. I dont get the exact issue here. Do you want me to remove
>> "S5P_". Is that it ?
> 
> S5P_ corresponds to at most Exynos4 SoC (Up till S5PV310). However,
> since the file is named s5p_gpio.c, then I think that S5P_ is a
> appropriate prefix.

Actually I have plan to rename from S5P_ to EXYNOS_. but not now.
It look OK to me.

> 
>>
>>>
>>> With the same patch:
>>>
>>> -  	case PERIPH_ID_UART1:
>>> -		bank = &gpio1->d0;
>>> -		start = 0;
>>> +		start = EXYNOS5_GPIO_D00;
>>>
>>> What is wrong with specifying the bank field? 
>>> Why your gpio command cannot use the bank approach?
>>>
>>
>> Ultimately we are using banks and pin_nums specific to the bank only
>> after we extract exact bank from the sequential pin_num.
> 
> Ok.
> 
>>
>>>
>>> And one more question: Is this work compliant with new driver model,
>>> which will be accepted at the merge window after the v2014.04
>>> release?
>>>
>>>
>>> If not, then there is no point to review this code, since GPIO would
>>> need to be adjusted to use this framework.
>>>
>>
>> Please explain more. I don't get this as well :-)
> 
> My point is that the new driver model (introduced by Simon) is going to
> be included. I'm concern if after introduction of it we would need to
> rewrite the gpio code to comply with it.
> 
>>
>>> --
>>> Best regards,
>>>
>>> Lukasz Majewski
>>>
>>> Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
>>>
>>
>> Regards,
>> Akshay Saraswat
> 
> 
> 

Thanks,
Minkyu Kang.

[U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature

[Simon Glass]

Hi Lukasz,

On 14 April 2014 01:17, Lukasz Majewski <l.majewski@samsung.com> wrote:

[snip[

I think your questions are mostly answered but I wanted to chime in on a
few.

What is wrong with specifying the bank field?
> Why your gpio command cannot use the bank approach?
>

U-Boot has a generic GPIO API and we should try to use it where possible.
This has been a long-standing TODO for exynos.


>
> And one more question: Is this work compliant with new driver model,
> which will be accepted at the merge window after the v2014.04 release?
>
> If not, then there is no point to review this code, since GPIO would
> need to be adjusted to use this framework.
>

The driver model framework is already in mainline. At present only sandbox
uses it for GPIO. I started looking at exynos since I thought it might be
quite easy to convert, but found that the generic GPIO stuff was still not
merged.

This series will make it much easier to convert exynos GPIO to driver
model, since we can just change the driver.

Regards,
Simon

[U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature

[Akshay Saraswat]

Hi Minkyu, Simon and Lukasz,

>Dear Akshay,
>
>On 14/04/14 19:53, Lukasz Majewski wrote:
>> Hi Akshay,
>> 
>>> Hi Lukasz,
>>>
>>>> Hi Akshay,
>>>>
>>>> I'm not Samsung tree maintainer, but by chance I've come across those
>>>> patches and...
>>>>
>>>> First question - why have you omitted u-boot-samsung tree maintainer?
>>>> I've added Minkyu to CC.
>>>>
>>>
>>> Minkyu has an email ID "promsoft at gmail.com" and I added that in CC.
>>> Probably you don't know this email id :-)
>> 
>> I do know it :-), but this is not the official one.
>> 
>> Adding involved people to CC really speed up things :-)
>> 
>
>I am always sensing about SAMSUNG related patches.
>Please don't worry about it :)
>
>>>
>>>>
>>>> Also in the cover letter you claim that this patch was "build tested"
>>>> for Exynos4 based boards. Why didn't you add at least one maintainer
>>>> of those boards to CC?
>>>>
>>>
>>> In cover letter I have not mentioned anywhere that I have built or
>>> tested these patches over Exynos4. 
>>> Patch 2/4 says "Build tested"
>>> because Rajeshwari did build images for Exynos4 boards and that was
>>> successfull but nobody tested booting those images.
>> 
>> As Przemek written to you in the other mail. There is a build problem
>> with trats2/trats boards.
>
>Please fix it.
>
>> 
>>> I do not possess any Exynos4 board. 
>> 
>> That is why it is a good practice to ask maintainer's of those boards
>> to test it for you. 
>> 
>>> These patches are meant for
>>> Exynos5 only.
>
>No. please consider Exynos4 also.
>If you make patches for Exynos4 too, then it will be great job.
>Przemek or Lukasz will help your test.
>
>> 

I borrowed an Origen board and doing changes for Exynos4 as well.
I'll push next patch-set tomorrow with Exynos4 and 5 support together.

>> We will probably go with your approach to make (_finally_) the gpio code
>> consistent for Exynos4/5.
>> 
>>> But Yes, there are compiler errors introduced for
>>> smkc100 because of this new patch-set and I will fix them in the next
>>> patch-set.
>
>next patch-set means v7? right?
>

Yes, next patch set would be v7.

>> 
>> I'm a bit confused now. Was this patch set build tested or not? 
>> 
>>>
>>>>
>>>>> +
>>>>> +/* A list of valid GPIO numbers for the asm-generic/gpio.h
>>>>> interface */ +enum exynos5_gpio_pin {
>>>>> +	/* GPIO_PART1_STARTS */
>>>>> +	EXYNOS5_GPIO_A00,	/* 0 */
>>>>> +	EXYNOS5_GPIO_A01,
>>>>> +	EXYNOS5_GPIO_A02,
>>>>> +	EXYNOS5_GPIO_A03,
>>>>> +	EXYNOS5_GPIO_A04,
>>>>
>>>> According to the patch description, you had a compilation error when
>>>> were adding the support for Exynos 5250 and 5420. Why you fix the
>>>> problem by rewriting the whole framework?
>>>>
>>>
>>> This framework is not intended to fix compiler warnings or errors but
>>> to make GPIO numbering easy to remember and sequential, without any
>>> holes in between.
>> 
>> Samsung boards were swinging from part+bank+pin number approach to
>> sequential GPIO number from time to time. I think it is a good
>> time to clean things up. 
>> 
>>>
>>>>
>>>> IN the patch 2/4 you have:
>>>>
>>>> -		gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
>>>> -		gpio_set_pull(start + i, GPIO_PULL_NONE);
>>>> -		gpio_set_drv(start + i, GPIO_DRV_4X);
>>>> +		gpio_cfg_pin(start + i, S5P_GPIO_FUNC(0x2));
>>>> +		gpio_set_pull(start + i, S5P_GPIO_PULL_NONE);
>>>> +		gpio_set_drv(start + i, S5P_GPIO_DRV_4X);
>>>>
>>>> What is the rationale to change the name to S5P_GPIO and not stick to
>>>> GPIO_FUNC? In which way gpios for Exynos5 are different than for
>>>> Exynos4? Cannot we finally reuse the Exynos 4 and 5 code?
>>>>
>>>
>>> We have enum member GPIO_INPUT in common/cmd_gpio.c and GPIO_INPUT
>>> define in arch-exynos/gpio.h. To remove such conflicts we renamed all
>>> s5p defines from "GPIO_*" to "S5P_GPIO_*".
>>> We are using the same s5p_gpio.c for both Exynos4 and 5 as far as I
>>> know. I dont get the exact issue here. Do you want me to remove
>>> "S5P_". Is that it ?
>> 
>> S5P_ corresponds to at most Exynos4 SoC (Up till S5PV310). However,
>> since the file is named s5p_gpio.c, then I think that S5P_ is a
>> appropriate prefix.
>
>Actually I have plan to rename from S5P_ to EXYNOS_. but not now.
>It look OK to me.
>
>> 
>>>
>>>>
>>>> With the same patch:
>>>>
>>>> -  	case PERIPH_ID_UART1:
>>>> -		bank = &gpio1->d0;
>>>> -		start = 0;
>>>> +		start = EXYNOS5_GPIO_D00;
>>>>
>>>> What is wrong with specifying the bank field? 
>>>> Why your gpio command cannot use the bank approach?
>>>>
>>>
>>> Ultimately we are using banks and pin_nums specific to the bank only
>>> after we extract exact bank from the sequential pin_num.
>> 
>> Ok.
>> 
>>>
>>>>
>>>> And one more question: Is this work compliant with new driver model,
>>>> which will be accepted at the merge window after the v2014.04
>>>> release?
>>>>
>>>>
>>>> If not, then there is no point to review this code, since GPIO would
>>>> need to be adjusted to use this framework.
>>>>
>>>
>>> Please explain more. I don't get this as well :-)
>> 
>> My point is that the new driver model (introduced by Simon) is going to
>> be included. I'm concern if after introduction of it we would need to
>> rewrite the gpio code to comply with it.
>> 
>>>
>>>> --
>>>> Best regards,
>>>>
>>>> Lukasz Majewski
>>>>
>>>> Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
>>>>
>>>
>>> Regards,
>>> Akshay Saraswat
>> 
>> 
>> 
>
>Thanks,
>Minkyu Kang.
>

Regards,
Akshay Saraswat

[U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature

[Przemyslaw Marczak]

Hello,
I like this idea. This is a good feature for easy and fast gpio 
maintaining. I have few comments to this.

On 04/12/2014 11:43 AM, Akshay Saraswat wrote:
> From: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>
> This patch adds gpio pin numbering support for EXYNOS 5250 & 5420.
> To have consistent 0..n-1 GPIO numbering the banks are divided
> into different parts where ever they have holes in them.
>
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
> ---

You use quite magic numbers in gpio names like "EXYNOS5_GPIO_A05",
maybe better is to add "PIN" word here like this: EXYNOS5_GPIO_A0_PIN5.
So then we really know what we are using and I think this just looks better.

> diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
> index d6868fa..211383d 100644
> --- a/arch/arm/include/asm/arch-exynos/gpio.h
> +++ b/arch/arm/include/asm/arch-exynos/gpio.h
> @@ -141,14 +141,16 @@ struct exynos5420_gpio_part1 {
>
It seems that those all exynos5*_gpio_partX structures and also 
exynos5*_gpio_get() macros can be removed now.

>   struct exynos5420_gpio_part2 {
>   	struct s5p_gpio_bank y7; /* 0x1340_0000 */
> -	struct s5p_gpio_bank res[0x5f]; /*  */
> +};
> +
> +struct exynos5420_gpio_part3 {
>   	struct s5p_gpio_bank x0; /* 0x1340_0C00 */
>   	struct s5p_gpio_bank x1; /* 0x1340_0C20 */
>   	struct s5p_gpio_bank x2; /* 0x1340_0C40 */
>   	struct s5p_gpio_bank x3; /* 0x1340_0C60 */
>   };
>
> -struct exynos5420_gpio_part3 {
> +struct exynos5420_gpio_part4 {
>   	struct s5p_gpio_bank c0;
>   	struct s5p_gpio_bank c1;
>   	struct s5p_gpio_bank c2;
> @@ -164,7 +166,7 @@ struct exynos5420_gpio_part3 {
>   	struct s5p_gpio_bank y6;
>   };
>
> -struct exynos5420_gpio_part4 {
> +struct exynos5420_gpio_part5 {
>   	struct s5p_gpio_bank e0; /* 0x1400_0000 */
>   	struct s5p_gpio_bank e1; /* 0x1400_0020 */
>   	struct s5p_gpio_bank f0; /* 0x1400_0040 */
> @@ -175,7 +177,7 @@ struct exynos5420_gpio_part4 {
>   	struct s5p_gpio_bank j4; /* 0x1400_00E0 */
>   };
>
> -struct exynos5420_gpio_part5 {
> +struct exynos5420_gpio_part6 {
>   	struct s5p_gpio_bank z0; /* 0x0386_0000 */
>   };
>
> @@ -200,16 +202,20 @@ struct exynos5_gpio_part1 {
>   	struct s5p_gpio_bank y4;
>   	struct s5p_gpio_bank y5;
>   	struct s5p_gpio_bank y6;
> -	struct s5p_gpio_bank res1[0x3];
> +};
> +
> +struct exynos5_gpio_part2 {
>   	struct s5p_gpio_bank c4;
> -	struct s5p_gpio_bank res2[0x48];
> +};
> +
> +struct exynos5_gpio_part3 {
>   	struct s5p_gpio_bank x0;
>   	struct s5p_gpio_bank x1;
>   	struct s5p_gpio_bank x2;
>   	struct s5p_gpio_bank x3;
>   };
>
> -struct exynos5_gpio_part2 {
> +struct exynos5_gpio_part4 {
>   	struct s5p_gpio_bank e0;
>   	struct s5p_gpio_bank e1;
>   	struct s5p_gpio_bank f0;
> @@ -221,20 +227,25 @@ struct exynos5_gpio_part2 {
>   	struct s5p_gpio_bank h1;
>   };
>
> -struct exynos5_gpio_part3 {
> +struct exynos5_gpio_part5 {
>   	struct s5p_gpio_bank v0;
>   	struct s5p_gpio_bank v1;
> -	struct s5p_gpio_bank res1[0x1];
> +};
> +
> +struct exynos5_gpio_part6 {
>   	struct s5p_gpio_bank v2;
>   	struct s5p_gpio_bank v3;
> -	struct s5p_gpio_bank res2[0x1];
> +};
> +
> +struct exynos5_gpio_part7 {
>   	struct s5p_gpio_bank v4;
>   };
>
> -struct exynos5_gpio_part4 {
> +struct exynos5_gpio_part8 {
>   	struct s5p_gpio_bank z;
>   };
>

There are also unchanged gpios initializations in files:
- arndale/arndale.c line 19
- smdk5420/smdk5420.c line 45

Thanks

-- 
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com

[U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature

[Przemyslaw Marczak]

Hi,
I missed this email before.

On 04/14/2014 04:55 PM, Akshay Saraswat wrote:
> Hi Minkyu, Simon and Lukasz,
>
>> Dear Akshay,
>>
>> On 14/04/14 19:53, Lukasz Majewski wrote:
>>> Hi Akshay,
>>>
>>>> Hi Lukasz,
>>>>
>>>>> Hi Akshay,
>>>>>
>>>>> I'm not Samsung tree maintainer, but by chance I've come across those
>>>>> patches and...
>>>>>
>>>>> First question - why have you omitted u-boot-samsung tree maintainer?
>>>>> I've added Minkyu to CC.
>>>>>
>>>>
>>>> Minkyu has an email ID "promsoft at gmail.com" and I added that in CC.
>>>> Probably you don't know this email id :-)
>>>
>>> I do know it :-), but this is not the official one.
>>>
>>> Adding involved people to CC really speed up things :-)
>>>
>>
>> I am always sensing about SAMSUNG related patches.
>> Please don't worry about it :)
>>
>>>>
>>>>>
>>>>> Also in the cover letter you claim that this patch was "build tested"
>>>>> for Exynos4 based boards. Why didn't you add at least one maintainer
>>>>> of those boards to CC?
>>>>>
>>>>
>>>> In cover letter I have not mentioned anywhere that I have built or
>>>> tested these patches over Exynos4.
>>>> Patch 2/4 says "Build tested"
>>>> because Rajeshwari did build images for Exynos4 boards and that was
>>>> successfull but nobody tested booting those images.
>>>
>>> As Przemek written to you in the other mail. There is a build problem
>>> with trats2/trats boards.
>>
>> Please fix it.
>>
>>>
>>>> I do not possess any Exynos4 board.
>>>
>>> That is why it is a good practice to ask maintainer's of those boards
>>> to test it for you.
>>>
>>>> These patches are meant for
>>>> Exynos5 only.
>>
>> No. please consider Exynos4 also.
>> If you make patches for Exynos4 too, then it will be great job.
>> Przemek or Lukasz will help your test.
>>
>>>
>
> I borrowed an Origen board and doing changes for Exynos4 as well.
> I'll push next patch-set tomorrow with Exynos4 and 5 support together.
>

Great. Please look at my comments. If you finish work with your patches 
then I add the same feature for s5pc1xx.

>>> We will probably go with your approach to make (_finally_) the gpio code
>>> consistent for Exynos4/5.
>>>
>>>> But Yes, there are compiler errors introduced for
>>>> smkc100 because of this new patch-set and I will fix them in the next
>>>> patch-set.
>>
>> next patch-set means v7? right?
>>
>
> Yes, next patch set would be v7.
>
>>>
>>> I'm a bit confused now. Was this patch set build tested or not?
>>>
>>>>
>>>>>
>>>>>> +
>>>>>> +/* A list of valid GPIO numbers for the asm-generic/gpio.h
>>>>>> interface */ +enum exynos5_gpio_pin {
>>>>>> +	/* GPIO_PART1_STARTS */
>>>>>> +	EXYNOS5_GPIO_A00,	/* 0 */
>>>>>> +	EXYNOS5_GPIO_A01,
>>>>>> +	EXYNOS5_GPIO_A02,
>>>>>> +	EXYNOS5_GPIO_A03,
>>>>>> +	EXYNOS5_GPIO_A04,
>>>>>
>>>>> According to the patch description, you had a compilation error when
>>>>> were adding the support for Exynos 5250 and 5420. Why you fix the
>>>>> problem by rewriting the whole framework?
>>>>>
>>>>
>>>> This framework is not intended to fix compiler warnings or errors but
>>>> to make GPIO numbering easy to remember and sequential, without any
>>>> holes in between.
>>>
>>> Samsung boards were swinging from part+bank+pin number approach to
>>> sequential GPIO number from time to time. I think it is a good
>>> time to clean things up.
>>>
>>>>
>>>>>
>>>>> IN the patch 2/4 you have:
>>>>>
>>>>> -		gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
>>>>> -		gpio_set_pull(start + i, GPIO_PULL_NONE);
>>>>> -		gpio_set_drv(start + i, GPIO_DRV_4X);
>>>>> +		gpio_cfg_pin(start + i, S5P_GPIO_FUNC(0x2));
>>>>> +		gpio_set_pull(start + i, S5P_GPIO_PULL_NONE);
>>>>> +		gpio_set_drv(start + i, S5P_GPIO_DRV_4X);
>>>>>
>>>>> What is the rationale to change the name to S5P_GPIO and not stick to
>>>>> GPIO_FUNC? In which way gpios for Exynos5 are different than for
>>>>> Exynos4? Cannot we finally reuse the Exynos 4 and 5 code?
>>>>>
>>>>
>>>> We have enum member GPIO_INPUT in common/cmd_gpio.c and GPIO_INPUT
>>>> define in arch-exynos/gpio.h. To remove such conflicts we renamed all
>>>> s5p defines from "GPIO_*" to "S5P_GPIO_*".
>>>> We are using the same s5p_gpio.c for both Exynos4 and 5 as far as I
>>>> know. I dont get the exact issue here. Do you want me to remove
>>>> "S5P_". Is that it ?
>>>
>>> S5P_ corresponds to at most Exynos4 SoC (Up till S5PV310). However,
>>> since the file is named s5p_gpio.c, then I think that S5P_ is a
>>> appropriate prefix.
>>
>> Actually I have plan to rename from S5P_ to EXYNOS_. but not now.
>> It look OK to me.
>>
>>>
>>>>
>>>>>
>>>>> With the same patch:
>>>>>
>>>>> -  	case PERIPH_ID_UART1:
>>>>> -		bank = &gpio1->d0;
>>>>> -		start = 0;
>>>>> +		start = EXYNOS5_GPIO_D00;
>>>>>
>>>>> What is wrong with specifying the bank field?
>>>>> Why your gpio command cannot use the bank approach?
>>>>>
>>>>
>>>> Ultimately we are using banks and pin_nums specific to the bank only
>>>> after we extract exact bank from the sequential pin_num.
>>>
>>> Ok.
>>>
>>>>
>>>>>
>>>>> And one more question: Is this work compliant with new driver model,
>>>>> which will be accepted at the merge window after the v2014.04
>>>>> release?
>>>>>
>>>>>
>>>>> If not, then there is no point to review this code, since GPIO would
>>>>> need to be adjusted to use this framework.
>>>>>
>>>>
>>>> Please explain more. I don't get this as well :-)
>>>
>>> My point is that the new driver model (introduced by Simon) is going to
>>> be included. I'm concern if after introduction of it we would need to
>>> rewrite the gpio code to comply with it.
>>>
>>>>
>>>>> --
>>>>> Best regards,
>>>>>
>>>>> Lukasz Majewski
>>>>>
>>>>> Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
>>>>>
>>>>
>>>> Regards,
>>>> Akshay Saraswat
>>>
>>>
>>>
>>
>> Thanks,
>> Minkyu Kang.
>>
>
> Regards,
> Akshay Saraswat
>

Thanks!
-- 
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com

[U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature

[Simon Glass]

Hi,

On 14 April 2014 09:15, Przemyslaw Marczak <p.marczak@samsung.com> wrote:

> Hello,
> I like this idea. This is a good feature for easy and fast gpio
> maintaining. I have few comments to this.
>
>
> On 04/12/2014 11:43 AM, Akshay Saraswat wrote:
>
>> From: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>>
>> This patch adds gpio pin numbering support for EXYNOS 5250 & 5420.
>> To have consistent 0..n-1 GPIO numbering the banks are divided
>> into different parts where ever they have holes in them.
>>
>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
>> ---
>>
>
> You use quite magic numbers in gpio names like "EXYNOS5_GPIO_A05",
> maybe better is to add "PIN" word here like this: EXYNOS5_GPIO_A0_PIN5.
> So then we really know what we are using and I think this just looks
> better.


I'm not sure I agree with the idea of a more verbose naming. The naming in
this series fits better with the idea of numbered GPIOs. The bank number is
of limited interest to users of GPIOs anyway. Exynos is slightly odd in
that banks have both a letter and number (A0, A1), but that doesn't seem
like a reason to change.

Regards,
Simon

[U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature

[Lukasz Majewski]

Hi Simon,

> Hi Lukasz,
> 
> On 14 April 2014 01:17, Lukasz Majewski <l.majewski@samsung.com>
> wrote:
> 
> [snip[
> 
> I think your questions are mostly answered but I wanted to chime in
> on a few.
> 
> What is wrong with specifying the bank field?
> > Why your gpio command cannot use the bank approach?
> >
> 
> U-Boot has a generic GPIO API and we should try to use it where
> possible. This has been a long-standing TODO for exynos.

I'm also fully aware that Exynos suffers from inconsistent gpio API.
However, I'm very glad that with Akshay's and our effort this goal
will be accomplished :-)

> 
> 
> >
> > And one more question: Is this work compliant with new driver model,
> > which will be accepted at the merge window after the v2014.04
> > release?
> >
> > If not, then there is no point to review this code, since GPIO would
> > need to be adjusted to use this framework.
> >
> 
> The driver model framework is already in mainline. 

I was rather thinking about the "big switch" as we did with KBUILD
after the v2014.01. Anyway, I'm looking forward to see the wide
deployment of device model in u-boot.

> At present only
> sandbox uses it for GPIO. I started looking at exynos since I thought
> it might be quite easy to convert, but found that the generic GPIO
> stuff was still not merged.
> 
> This series will make it much easier to convert exynos GPIO to driver
> model, since we can just change the driver.

Thanks for clarification.

> 
> Regards,
> Simon
> 


-- 
Best regards,

Lukasz Majewski

Samsung R&D Institute Poland (SRPOL) | Linux Platform Group

[U-Boot] [PATCH v6 1/4] EXYNOS5: Add gpio pin numbering feature

[Simon Glass]

Hi Lukasz,

On 14 April 2014 23:25, Lukasz Majewski <l.majewski@samsung.com> wrote:

> Hi Simon,
>
> > Hi Lukasz,
> >
> > On 14 April 2014 01:17, Lukasz Majewski <l.majewski@samsung.com>
> > wrote:
> >
> > [snip[
> >
> > I think your questions are mostly answered but I wanted to chime in
> > on a few.
> >
> > What is wrong with specifying the bank field?
> > > Why your gpio command cannot use the bank approach?
> > >
> >
> > U-Boot has a generic GPIO API and we should try to use it where
> > possible. This has been a long-standing TODO for exynos.
>
> I'm also fully aware that Exynos suffers from inconsistent gpio API.
> However, I'm very glad that with Akshay's and our effort this goal
> will be accomplished :-)
>
> >
> >
> > >
> > > And one more question: Is this work compliant with new driver model,
> > > which will be accepted at the merge window after the v2014.04
> > > release?
> > >
> > > If not, then there is no point to review this code, since GPIO would
> > > need to be adjusted to use this framework.
> > >
> >
> > The driver model framework is already in mainline.
>
> I was rather thinking about the "big switch" as we did with KBUILD
> after the v2014.01. Anyway, I'm looking forward to see the wide
> deployment of device model in u-boot.
>

I don't expect a big switch. Each subsystem needs to add support for it,
and then (as a separate step) each driver needs to be ported into the new
uclass. So it will likely be an incremental effort.


> > At present only
> > sandbox uses it for GPIO. I started looking at exynos since I thought
> > it might be quite easy to convert, but found that the generic GPIO
> > stuff was still not merged.
> >
> > This series will make it much easier to convert exynos GPIO to driver
> > model, since we can just change the driver.
>
> Thanks for clarification.
>

I'm probably going to take a look at Tegra while waiting for this series to
land. Let's see how it goes.

Regards,
Simon