* [U-Boot] [PATCH][v2] board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config
@ 2014-03-08 11:15 Prabhakar Kushwaha
2014-04-23 21:57 ` York Sun
0 siblings, 1 reply; 2+ messages in thread
From: Prabhakar Kushwaha @ 2014-03-08 11:15 UTC (permalink / raw)
To: u-boot
The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher
than 2.5 MHZ. It violates the IEEE specs.
So Slow MDC clock to comply IEEE specs
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: Update commit message
board/freescale/b4860qds/b4_pbi.cfg | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/freescale/b4860qds/b4_pbi.cfg b/board/freescale/b4860qds/b4_pbi.cfg
index 57b726e..05377ba 100644
--- a/board/freescale/b4860qds/b4_pbi.cfg
+++ b/board/freescale/b4860qds/b4_pbi.cfg
@@ -22,6 +22,9 @@
09110024 00100008
09110028 00100008
0911002c 00100008
+#slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
#Flush PBL data
09138000 00000000
091380c0 00000000
--
1.7.9.5
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [U-Boot] [PATCH][v2] board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config
2014-03-08 11:15 [U-Boot] [PATCH][v2] board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config Prabhakar Kushwaha
@ 2014-04-23 21:57 ` York Sun
0 siblings, 0 replies; 2+ messages in thread
From: York Sun @ 2014-04-23 21:57 UTC (permalink / raw)
To: u-boot
On 03/08/2014 03:15 AM, Prabhakar Kushwaha wrote:
> The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher
> than 2.5 MHZ. It violates the IEEE specs.
>
> So Slow MDC clock to comply IEEE specs
>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
> Changes for v2: Update commit message
Applied to u-boot-mpc85xx/master, thanks.
York
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2014-03-08 11:15 [U-Boot] [PATCH][v2] board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config Prabhakar Kushwaha
2014-04-23 21:57 ` York Sun
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