From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Wed, 23 Apr 2014 15:28:40 -0700 Subject: [U-Boot] [PATCH 1/4][v7] powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS In-Reply-To: <1395166226-23473-1-git-send-email-aneesh.bansal@freescale.com> References: <1395166226-23473-1-git-send-email-aneesh.bansal@freescale.com> Message-ID: <53583E98.5090300@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 03/18/2014 11:10 AM, Aneesh Bansal wrote: > Changes: > 1. L2 cache is being invalidated by Boot ROM code for e6500 core. > So removing the invalidation from start.S > 2. Clear the LAW and corresponding configuration for CPC. Boot ROM > code uses it as hosekeeping area. > 3. For Secure boot, CPC is configured as SRAM and used as house > keeping area. This configuration is to be disabled once in uboot. > Earlier this disabling of CPC as SRAM was happening in cpu_init_r. > As a result cache invalidation function was getting skipped in > case CPC is configured as SRAM.This was causing random crashes. > > Signed-off-by: Ruchika Gupta > Signed-off-by: Aneesh Bansal > --- Applied to u-boot-mpc85xx/master, thanks. York