[U-Boot] [linux-sunxi] [PATCH v5 7/8] sunxi: mmc support

[Stefan Roese <sr@denx.de>]

On 05.05.2014 12:52, Ian Campbell wrote:
> This adds support for the MMC controller on the Allwinner A20 (sun7i)
> processor.
> 
> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
> Signed-off-by: Luke Leighton <lkcl@lkcl.net>
> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
> Signed-off-by: Wills Wang <wills.wang.open@gmail.com>
> Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
> Reviewed-by: Marek Vasut <marex@denx.de>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Tom Cubie <Mr.hipboi@gmail.com>
> Cc: Aaron Maoye <leafy.myeh@allwinnertech.com>
> Cc: Pantelis Antoniou <panto@antoniou-consulting.com>

Ian, thanks a lot for your endurance and patience to get this sunxi stuff
upstream. Really appreciated. One comment below:

<snip>

> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> index 328334a..dc7f636 100644
> --- a/board/sunxi/board.c
> +++ b/board/sunxi/board.c
> @@ -14,6 +14,8 @@
>   #include <common.h>
>   #include <asm/arch/clock.h>
>   #include <asm/arch/dram.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/arch/mmc.h>
>   
>   DECLARE_GLOBAL_DATA_PTR;
>   
> @@ -43,6 +45,76 @@ int dram_init(void)
>   	return 0;
>   }
>   
> +#ifdef CONFIG_GENERIC_MMC
> +static void mmc_pinmux_setup(int sdc)
> +{
> +	unsigned int pin;
> +
> +	switch (sdc) {
> +	case 0:
> +		/* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
> +		for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
> +			sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0);
> +			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
> +			sunxi_gpio_set_drv(pin, 2);
> +		}
> +		break;
> +
> +	case 1:
> +#if CONFIG_MMC1_PG
> +		/* PG0-CMD, PG1-CLK, PG2~5-D0~3 : 4 */
> +		for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
> +			sunxi_gpio_set_cfgpin(pin, SUN4I_GPG0_SDC1);
> +			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
> +			sunxi_gpio_set_drv(pin, 2);
> +		}
> +#else
> +		/* PH22-CMD, PH23-CLK, PH24~27-D0~D3 : 5 */
> +		for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
> +			sunxi_gpio_set_cfgpin(pin, SUN4I_GPH22_SDC1);
> +			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
> +			sunxi_gpio_set_drv(pin, 2);
> +		}
> +#endif

Are you sure that this is correct and shouldn't be:

+#ifdef CONFIG_MMC1_PG

?

A quick scan through this patch series shows that this define
is not set at all. Perhaps its outdated? Or is it used to support
some other sunxi SoC? Not sure, perhaps it should be removed for
now.

Other than this please add my:

Reviewed-by: Stefan Roese <sr@denx.de>

Thanks,
Stefan