[U-Boot] [PATCH] powerpc/mpc85xx: 32bit DDR changes for P1020/P1011

[U-Boot] [PATCH] powerpc/mpc85xx: 32bit DDR changes for P1020/P1011

[Prabhakar Kushwaha]

The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010
where max DDR data width supported is 64bit.

Add dynamic DDR size adjustment in second stage boot loader execution.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/cpu.c |    7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 12e8e10..9c082b4 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -347,7 +347,12 @@ phys_size_t initdram(int board_type)
 	defined(CONFIG_QEMU_E500)
 	return fsl_ddr_sdram_size();
 #else
-	return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	struct cpu_type *cpu = gd->arch.cpu;
+	/* P1020 and it's derivatives support max 32bit DDR width */
+	if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011)
+		return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2;
+	else
+		return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 #endif
 }
 #else /* CONFIG_SYS_RAMBOOT */
-- 
1.7.9.5

[U-Boot] [PATCH] powerpc/mpc85xx: 32bit DDR changes for P1020/P1011

[York Sun]

On 05/12/2014 10:50 PM, Prabhakar Kushwaha wrote:
> The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010
> where max DDR data width supported is 64bit.
> 
> Add dynamic DDR size adjustment in second stage boot loader execution.
> 
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
>  arch/powerpc/cpu/mpc85xx/cpu.c |    7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
> index 12e8e10..9c082b4 100644
> --- a/arch/powerpc/cpu/mpc85xx/cpu.c
> +++ b/arch/powerpc/cpu/mpc85xx/cpu.c
> @@ -347,7 +347,12 @@ phys_size_t initdram(int board_type)
>  	defined(CONFIG_QEMU_E500)
>  	return fsl_ddr_sdram_size();
>  #else
> -	return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
> +	struct cpu_type *cpu = gd->arch.cpu;
> +	/* P1020 and it's derivatives support max 32bit DDR width */
> +	if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011)
> +		return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2;
> +	else
> +		return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
>  #endif
>  }
>  #else /* CONFIG_SYS_RAMBOOT */
> 

Prabhakar,

The second stage boot loader doesn't re-initialize DDR, right? The size should
come from either fsl_ddr_sdram_size() or the predefined macro
CONFIG_SYS_SDRAM_SIZE. It looks like you are modifying the predefiend one. Is
this what you want? If so, why don't you defined the macro with correct value?

York