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From: Balaji T K <balajitk@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] mmc: omap_hsmmc: add adma support
Date: Thu, 15 May 2014 19:45:28 +0530	[thread overview]
Message-ID: <5374CC00.2010206@ti.com> (raw)
In-Reply-To: <20140512145002.GD22182@bill-the-cat>

On Monday 12 May 2014 08:20 PM, Tom Rini wrote:
> On Mon, May 12, 2014 at 07:12:44PM +0530, Balaji T K wrote:
>> On Monday 12 May 2014 06:58 PM, Tom Rini wrote:
>>> On Fri, May 02, 2014 at 07:25:20PM +0530, Balaji T K wrote:
>>>
>>>> MMC instance 1 and 2 is capable of ADMA in omap4, omap5.
>>>> Add support for ADMA and enable ADMA for read/write to
>>>> improve mmc throughput.
>>> [snip]
>>>> @@ -44,12 +45,30 @@
>>>>   #undef OMAP_HSMMC_USE_GPIO
>>>>   #endif
>>>>
>>>> +#ifdef CONFIG_SPL_BUILD
>>>> +#undef CONFIG_OMAP_MMC_ADMA
>>>> +#endif
>>>
>>> Why?  Especially since a number of the folks interested in this for
>>> performance want it for SPL OS mode.  Thanks!
>>
>> Because in SoCs like OMAP4/5 mmc1/2 adma doesn't have access to sram.
>> So can't have descriptor or src / destination buffers (allocated on stack)
>> given by mmc core on sram.
>
> And we can't malloc them?
>

For descriptor yes, but for src / dest, I doubt since
it would be difficult to force the upper (fs, mmc..) layers for controller limitation
and some ARCH might require the buffers to be cache aligned

Does malloc return buffers aligned to cache boundary ?

  reply	other threads:[~2014-05-15 14:15 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-05-02 13:55 [U-Boot] [PATCH] mmc: omap_hsmmc: add adma support Balaji T K
2014-05-12 13:21 ` Balaji T K
2014-05-12 13:28 ` Tom Rini
2014-05-12 13:42   ` Balaji T K
2014-05-12 14:50     ` Tom Rini
2014-05-15 14:15       ` Balaji T K [this message]
2014-05-15 17:55         ` Tom Rini

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