From mboxrd@z Thu Jan  1 00:00:00 1970
From: York Sun <yorksun@freescale.com>
Date: Fri, 6 Jun 2014 13:17:32 -0700
Subject: [U-Boot] [Patch v4 2/5] ARMv8: Adjust MMU setup
In-Reply-To: <20140606173243.GC18918@leverpostej>
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	<20140605100926.GA6430@leverpostej>
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	<20140605174156.GG31564@leverpostej>
	<5390B82F.5040601@freescale.com>
	<20140606123312.GB18918@leverpostej>
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	<20140606173243.GC18918@leverpostej>
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On 06/06/2014 10:32 AM, Mark Rutland wrote:
>>> How is TCR_EL2.SH0 (or TCR_EL1.SH*) configured?
>>>
>>> You'll only need to flush the cache if they're configured non shareable.
>>
>> It is configured as non shareable.
> 
> Is there any reason not to configure them as inner shareable? That way
> the MMU will look in the D-cache, and you won't have to spend time
> flushing them.
> 

Mark,

I appreciate the reminder. I tried on our emulator. With inner share set for TCR
SH0 bits, u-boot works with the flushing, but doesn't work without flushing. It
went to exception.

Can you share more information about the inner share? I need to follow up with
our designer to confirm.

York