* [U-Boot] [PATCH v2 01/12] sunxi: mksunxiboot: Fix loading of files with a size which is not a multiple of 4
2014-06-03 19:41 [U-Boot] [PATCH v2 00/12] sunxi: Bug fixes, sun4i and sun5i support, pmic support and network improvements Hans de Goede
@ 2014-06-03 19:41 ` Hans de Goede
2014-06-03 19:41 ` [U-Boot] [PATCH v2 02/12] sunxi: Fix u-boot-spl.lds to refer to .vectors Hans de Goede
` (10 subsequent siblings)
11 siblings, 0 replies; 27+ messages in thread
From: Hans de Goede @ 2014-06-03 19:41 UTC (permalink / raw)
To: u-boot
We should not be aligning the amount of bytes which we try to read from the
disk, this leads to trying to read more bytes then there are which fails.
file_size is already aligned to BLOCK_SIZE before being stored in
img.header.length, so there is no need for load_size at all.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
tools/mksunxiboot.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c
index da7c9f0..1f0fbae 100644
--- a/tools/mksunxiboot.c
+++ b/tools/mksunxiboot.c
@@ -77,7 +77,7 @@ int main(int argc, char *argv[])
{
int fd_in, fd_out;
struct boot_img img;
- unsigned file_size, load_size;
+ unsigned file_size;
int count;
if (argc < 2) {
@@ -101,8 +101,6 @@ int main(int argc, char *argv[])
if (file_size > SRAM_LOAD_MAX_SIZE) {
fprintf(stderr, "ERROR: File too large!\n");
return EXIT_FAILURE;
- } else {
- load_size = ALIGN(file_size, sizeof(int));
}
fd_out = open(argv[2], O_WRONLY | O_CREAT, 0666);
@@ -113,8 +111,8 @@ int main(int argc, char *argv[])
/* read file to buffer to calculate checksum */
lseek(fd_in, 0, SEEK_SET);
- count = read(fd_in, img.code, load_size);
- if (count != load_size) {
+ count = read(fd_in, img.code, file_size);
+ if (count != file_size) {
perror("Reading input image");
return EXIT_FAILURE;
}
@@ -126,7 +124,7 @@ int main(int argc, char *argv[])
& 0x00FFFFFF);
memcpy(img.header.magic, BOOT0_MAGIC, 8); /* no '0' termination */
img.header.length =
- ALIGN(load_size + sizeof(struct boot_file_head), BLOCK_SIZE);
+ ALIGN(file_size + sizeof(struct boot_file_head), BLOCK_SIZE);
gen_check_sum(&img.header);
count = write(fd_out, &img, img.header.length);
--
1.9.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [U-Boot] [PATCH v2 02/12] sunxi: Fix u-boot-spl.lds to refer to .vectors
2014-06-03 19:41 [U-Boot] [PATCH v2 00/12] sunxi: Bug fixes, sun4i and sun5i support, pmic support and network improvements Hans de Goede
2014-06-03 19:41 ` [U-Boot] [PATCH v2 01/12] sunxi: mksunxiboot: Fix loading of files with a size which is not a multiple of 4 Hans de Goede
@ 2014-06-03 19:41 ` Hans de Goede
2014-06-03 19:41 ` [U-Boot] [PATCH v2 03/12] sunxi: Remove mmc DMA support Hans de Goede
` (9 subsequent siblings)
11 siblings, 0 replies; 27+ messages in thread
From: Hans de Goede @ 2014-06-03 19:41 UTC (permalink / raw)
To: u-boot
Adjust the u-boot-spl.lds linker script to match the changes made in the
41623c91b09a0c865fab41acdaff30f060f29ad6 "arm: move exception handling out
of start.S files" commit.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
arch/arm/cpu/armv7/sunxi/u-boot-spl.lds | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
index 5008028..c1ae227 100644
--- a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
@@ -27,6 +27,7 @@ SECTIONS
.text :
{
__start = .;
+ *(.vectors)
arch/arm/cpu/armv7/start.o (.text)
*(.text*)
} > .sram
--
1.9.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [U-Boot] [PATCH v2 03/12] sunxi: Remove mmc DMA support
2014-06-03 19:41 [U-Boot] [PATCH v2 00/12] sunxi: Bug fixes, sun4i and sun5i support, pmic support and network improvements Hans de Goede
2014-06-03 19:41 ` [U-Boot] [PATCH v2 01/12] sunxi: mksunxiboot: Fix loading of files with a size which is not a multiple of 4 Hans de Goede
2014-06-03 19:41 ` [U-Boot] [PATCH v2 02/12] sunxi: Fix u-boot-spl.lds to refer to .vectors Hans de Goede
@ 2014-06-03 19:41 ` Hans de Goede
2014-06-03 19:41 ` [U-Boot] [PATCH v2 04/12] sunxi: Implement reset_cpu Hans de Goede
` (8 subsequent siblings)
11 siblings, 0 replies; 27+ messages in thread
From: Hans de Goede @ 2014-06-03 19:41 UTC (permalink / raw)
To: u-boot
The DMA code in sunxi_mmc.c is broken. mmc_trans_data_by_dma() allocates the
dma descriptors on the stack, and then exits while the dma transfer is in
progress, so the dma engine is reading stack memory which at that point may
be re-used. So far we've gotten away with this by luck, but recent u-boot
changes have shifted the stack start address by 16 bytes, which combined
with dma alignment now exposes this problem.
Since we end up just busy waiting for the dma engine anyway, this commit
fixes things by simply removing the dma code, resulting in smaller bug-free
code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
drivers/mmc/sunxi_mmc.c | 140 ++---------------------------------------
include/configs/sunxi-common.h | 1 -
2 files changed, 6 insertions(+), 135 deletions(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index eb7b115..ae0cf1a 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -16,28 +16,6 @@
#include <asm/arch/cpu.h>
#include <asm/arch/mmc.h>
-struct sunxi_mmc_des {
- u32 reserved1_1:1;
- u32 dic:1; /* disable interrupt on completion */
- u32 last_des:1; /* 1-this data buffer is the last buffer */
- u32 first_des:1; /* 1-data buffer is the first buffer,
- 0-data buffer contained in the next
- descriptor is 1st buffer */
- u32 des_chain:1; /* 1-the 2nd address in the descriptor is the
- next descriptor address */
- u32 end_of_ring:1; /* 1-last descriptor flag when using dual
- data buffer in descriptor */
- u32 reserved1_2:24;
- u32 card_err_sum:1; /* transfer error flag */
- u32 own:1; /* des owner:1-idma owns it, 0-host owns it */
-#define SDXC_DES_NUM_SHIFT 16
-#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT)
- u32 data_buf1_sz:16;
- u32 data_buf2_sz:16;
- u32 buf_addr_ptr1;
- u32 buf_addr_ptr2;
-};
-
struct sunxi_mmc_host {
unsigned mmc_no;
uint32_t *mclkreg;
@@ -189,6 +167,9 @@ static int mmc_core_init(struct mmc *mmc)
/* Reset controller */
writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
+ udelay(1000);
+ /* Always read / write data through the CPU */
+ writel(SUNXI_MMC_GCTRL_ACCESS_BY_AHB, &mmchost->reg->gctrl);
return 0;
}
@@ -220,85 +201,6 @@ static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
return 0;
}
-static int mmc_trans_data_by_dma(struct mmc *mmc, struct mmc_data *data)
-{
- struct sunxi_mmc_host *mmchost = mmc->priv;
- unsigned byte_cnt = data->blocksize * data->blocks;
- unsigned char *buff;
- unsigned des_idx = 0;
- unsigned buff_frag_num =
- (byte_cnt + SDXC_DES_BUFFER_MAX_LEN - 1) >> SDXC_DES_NUM_SHIFT;
- unsigned remain;
- unsigned i, rval;
- ALLOC_CACHE_ALIGN_BUFFER(struct sunxi_mmc_des, pdes, buff_frag_num);
-
- buff = data->flags & MMC_DATA_READ ?
- (unsigned char *)data->dest : (unsigned char *)data->src;
- remain = byte_cnt & (SDXC_DES_BUFFER_MAX_LEN - 1);
-
- flush_cache((unsigned long)buff, (unsigned long)byte_cnt);
- for (i = 0; i < buff_frag_num; i++, des_idx++) {
- memset((void *)&pdes[des_idx], 0, sizeof(struct sunxi_mmc_des));
- pdes[des_idx].des_chain = 1;
- pdes[des_idx].own = 1;
- pdes[des_idx].dic = 1;
- if (buff_frag_num > 1 && i != buff_frag_num - 1)
- pdes[des_idx].data_buf1_sz = 0; /* 0 == max_len */
- else
- pdes[des_idx].data_buf1_sz = remain;
-
- pdes[des_idx].buf_addr_ptr1 =
- (u32) buff + i * SDXC_DES_BUFFER_MAX_LEN;
- if (i == 0)
- pdes[des_idx].first_des = 1;
-
- if (i == buff_frag_num - 1) {
- pdes[des_idx].dic = 0;
- pdes[des_idx].last_des = 1;
- pdes[des_idx].end_of_ring = 1;
- pdes[des_idx].buf_addr_ptr2 = 0;
- } else {
- pdes[des_idx].buf_addr_ptr2 = (u32)&pdes[des_idx + 1];
- }
- }
- flush_cache((unsigned long)pdes,
- sizeof(struct sunxi_mmc_des) * (des_idx + 1));
-
- rval = readl(&mmchost->reg->gctrl);
- /* Enable DMA */
- writel(rval | SUNXI_MMC_GCTRL_DMA_RESET | SUNXI_MMC_GCTRL_DMA_ENABLE,
- &mmchost->reg->gctrl);
- /* Reset iDMA */
- writel(SUNXI_MMC_IDMAC_RESET, &mmchost->reg->dmac);
- /* Enable iDMA */
- writel(SUNXI_MMC_IDMAC_FIXBURST | SUNXI_MMC_IDMAC_ENABLE,
- &mmchost->reg->dmac);
- rval = readl(&mmchost->reg->idie) &
- ~(SUNXI_MMC_IDIE_TXIRQ|SUNXI_MMC_IDIE_RXIRQ);
- if (data->flags & MMC_DATA_WRITE)
- rval |= SUNXI_MMC_IDIE_TXIRQ;
- else
- rval |= SUNXI_MMC_IDIE_RXIRQ;
- writel(rval, &mmchost->reg->idie);
- writel((u32) pdes, &mmchost->reg->dlba);
- writel((0x2 << 28) | (0x7 << 16) | (0x01 << 3),
- &mmchost->reg->ftrglevel);
-
- return 0;
-}
-
-static void mmc_enable_dma_accesses(struct mmc *mmc, int dma)
-{
- struct sunxi_mmc_host *mmchost = mmc->priv;
-
- unsigned int gctrl = readl(&mmchost->reg->gctrl);
- if (dma)
- gctrl &= ~SUNXI_MMC_GCTRL_ACCESS_BY_AHB;
- else
- gctrl |= SUNXI_MMC_GCTRL_ACCESS_BY_AHB;
- writel(gctrl, &mmchost->reg->gctrl);
-}
-
static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
unsigned int done_bit, const char *what)
{
@@ -327,7 +229,6 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
unsigned int timeout_msecs;
int error = 0;
unsigned int status = 0;
- unsigned int usedma = 0;
unsigned int bytecnt = 0;
if (mmchost->fatal_err)
@@ -378,20 +279,8 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
bytecnt = data->blocksize * data->blocks;
debug("trans data %d bytes\n", bytecnt);
-#if defined(CONFIG_MMC_SUNXI_USE_DMA) && !defined(CONFIG_SPL_BUILD)
- if (bytecnt > 64) {
-#else
- if (0) {
-#endif
- usedma = 1;
- mmc_enable_dma_accesses(mmc, 1);
- ret = mmc_trans_data_by_dma(mmc, data);
- writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
- } else {
- mmc_enable_dma_accesses(mmc, 0);
- writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
- ret = mmc_trans_data_by_cpu(mmc, data);
- }
+ writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
+ ret = mmc_trans_data_by_cpu(mmc, data);
if (ret) {
error = readl(&mmchost->reg->rint) & \
SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
@@ -405,7 +294,7 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
goto out;
if (data) {
- timeout_msecs = usedma ? 120 * bytecnt : 120;
+ timeout_msecs = 120;
debug("cacl timeout %x msec\n", timeout_msecs);
error = mmc_rint_wait(mmc, timeout_msecs,
data->blocks > 1 ?
@@ -442,23 +331,6 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
debug("mmc resp 0x%08x\n", cmd->response[0]);
}
out:
- if (data && usedma) {
- /* IDMASTAREG
- * IDST[0] : idma tx int
- * IDST[1] : idma rx int
- * IDST[2] : idma fatal bus error
- * IDST[4] : idma descriptor invalid
- * IDST[5] : idma error summary
- * IDST[8] : idma normal interrupt sumary
- * IDST[9] : idma abnormal interrupt sumary
- */
- status = readl(&mmchost->reg->idst);
- writel(status, &mmchost->reg->idst);
- writel(0, &mmchost->reg->idie);
- writel(0, &mmchost->reg->dmac);
- writel(readl(&mmchost->reg->gctrl) & ~SUNXI_MMC_GCTRL_DMA_ENABLE,
- &mmchost->reg->gctrl);
- }
if (error < 0) {
writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
mmc_update_clk(mmc);
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 5d72d62..fd02d0d 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -70,7 +70,6 @@
#define CONFIG_CMD_MMC
#define CONFIG_MMC_SUNXI
#define CONFIG_MMC_SUNXI_SLOT 0
-#define CONFIG_MMC_SUNXI_USE_DMA
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */
--
1.9.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [U-Boot] [PATCH v2 04/12] sunxi: Implement reset_cpu
2014-06-03 19:41 [U-Boot] [PATCH v2 00/12] sunxi: Bug fixes, sun4i and sun5i support, pmic support and network improvements Hans de Goede
` (2 preceding siblings ...)
2014-06-03 19:41 ` [U-Boot] [PATCH v2 03/12] sunxi: Remove mmc DMA support Hans de Goede
@ 2014-06-03 19:41 ` Hans de Goede
2014-06-03 19:41 ` [U-Boot] [PATCH v2 05/12] sunxi: Add sun4i support Hans de Goede
` (7 subsequent siblings)
11 siblings, 0 replies; 27+ messages in thread
From: Hans de Goede @ 2014-06-03 19:41 UTC (permalink / raw)
To: u-boot
There is no way to reset the cpu, so use the watchdog for this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
arch/arm/cpu/armv7/sunxi/board.c | 7 +++++++
arch/arm/include/asm/arch-sunxi/timer.h | 5 +++++
2 files changed, 12 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 49c9448..c80b421 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -56,6 +56,13 @@ int gpio_init(void)
void reset_cpu(ulong addr)
{
+ static const struct sunxi_wdog *wdog =
+ &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
+
+ /* Set the watchdog for its shortest interval (.5s) and wait */
+ writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
+ writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
+ while (1);
}
/* do some early init */
diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h
index 6aacfd7..58e14fd 100644
--- a/arch/arm/include/asm/arch-sunxi/timer.h
+++ b/arch/arm/include/asm/arch-sunxi/timer.h
@@ -11,6 +11,11 @@
#ifndef _SUNXI_TIMER_H_
#define _SUNXI_TIMER_H_
+#define WDT_CTRL_RESTART (0x1 << 0)
+#define WDT_CTRL_KEY (0x0a57 << 1)
+#define WDT_MODE_EN (0x1 << 0)
+#define WDT_MODE_RESET_EN (0x1 << 1)
+
#ifndef __ASSEMBLY__
#include <linux/types.h>
--
1.9.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [U-Boot] [PATCH v2 05/12] sunxi: Add sun4i support
2014-06-03 19:41 [U-Boot] [PATCH v2 00/12] sunxi: Bug fixes, sun4i and sun5i support, pmic support and network improvements Hans de Goede
` (3 preceding siblings ...)
2014-06-03 19:41 ` [U-Boot] [PATCH v2 04/12] sunxi: Implement reset_cpu Hans de Goede
@ 2014-06-03 19:41 ` Hans de Goede
2014-06-05 18:13 ` Ian Campbell
2014-06-03 19:41 ` [U-Boot] [PATCH v2 06/12] sunxi: Add sun5i support Hans de Goede
` (6 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Hans de Goede @ 2014-06-03 19:41 UTC (permalink / raw)
To: u-boot
Add support for the Allwinner A10 SoC also known as the Allwinner sun4i family,
and add the Cubieboard board which uses the A10 SoC.
Compared to sun7 only the DRAM controller is a bit different:
-Controller reset bits are inverted, but only for Rev. A
-Different hpcr values
-No MBUS on sun4i
-Various other initialization changes
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
arch/arm/cpu/armv7/sunxi/Makefile | 2 +
arch/arm/cpu/armv7/sunxi/cpu_info.c | 7 ++++
arch/arm/cpu/armv7/sunxi/dram.c | 81 +++++++++++++++++++++++++++++++++++--
board/sunxi/Makefile | 1 +
board/sunxi/dram_cubieboard.c | 31 ++++++++++++++
boards.cfg | 1 +
include/configs/sun4i.h | 23 +++++++++++
7 files changed, 143 insertions(+), 3 deletions(-)
create mode 100644 board/sunxi/dram_cubieboard.c
create mode 100644 include/configs/sun4i.h
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index a64bfa1..856d353 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -11,6 +11,7 @@ obj-y += timer.o
obj-y += board.o
obj-y += clock.o
obj-y += pinmux.o
+obj-$(CONFIG_SUN4I) += clock_sun4i.o
obj-$(CONFIG_SUN7I) += clock_sun4i.o
ifndef CONFIG_SPL_BUILD
@@ -18,6 +19,7 @@ obj-y += cpu_info.o
endif
ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SUN4I) += dram.o
obj-$(CONFIG_SUN7I) += dram.o
ifdef CONFIG_SPL_FEL
obj-y += start.o
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index b4c3d5c..b4b5089 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -13,7 +13,14 @@
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
+#ifdef CONFIG_SUN4I
+ puts("CPU: Allwinner A10 (SUN4I)\n");
+#elif defined CONFIG_SUN7I
puts("CPU: Allwinner A20 (SUN7I)\n");
+#else
+#warning Please update cpu_info.c with correct CPU information
+ puts("CPU: SUNXI Family\n");
+#endif
return 0;
}
#endif
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index b43c4b4..1de7529 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -53,16 +53,37 @@ static void mctl_ddr3_reset(void)
struct sunxi_dram_reg *dram =
(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
- clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
- udelay(2);
- setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+#ifdef CONFIG_SUN4I
+ struct sunxi_timer_reg *timer =
+ (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
+ u32 reg_val;
+
+ writel(0, &timer->cpu_cfg);
+ reg_val = readl(&timer->cpu_cfg);
+
+ if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
+ CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
+ setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+ udelay(2);
+ clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
+ } else
+#endif
+ {
+ clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
+ udelay(2);
+ setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+ }
}
static void mctl_set_drive(void)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+#ifdef CONFIG_SUN7I
clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
+#else
+ clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
+#endif
DRAM_MCR_MODE_EN(0x3) |
0xffc);
}
@@ -134,6 +155,16 @@ static void mctl_enable_dllx(u32 phase)
}
static u32 hpcr_value[32] = {
+#ifdef CONFIG_SUN4I
+ 0x0301, 0x0301, 0x0301, 0x0301,
+ 0x0301, 0x0301, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0x1031, 0x1031, 0x0735, 0x5031,
+ 0x1035, 0x0731, 0x1031, 0x0735,
+ 0x1035, 0x1031, 0x0731, 0x1035,
+ 0x1031, 0x0301, 0x0301, 0x0731
+#endif
#ifdef CONFIG_SUN7I
0x0301, 0x0301, 0x0301, 0x0301,
0x0301, 0x0301, 0x0301, 0x0301,
@@ -223,22 +254,32 @@ static void mctl_setup_dram_clock(u32 clk)
clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
#endif
+#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
/* setup MBUS clock */
reg_val = CCM_MBUS_CTRL_GATE |
CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) |
CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
writel(reg_val, &ccm->mbus_clk_cfg);
+#endif
/*
* open DRAMC AHB & DLL register clock
* close it first
*/
+#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
+#else
+ clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
+#endif
udelay(22);
/* then open it */
+#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
+#else
+ setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
+#endif
udelay(22);
}
@@ -385,6 +426,13 @@ static void dramc_clock_output_en(u32 on)
else
clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
#endif
+#ifdef CONFIG_SUN4I
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ if (on)
+ setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
+ else
+ clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
+#endif
}
static const u16 tRFC_table[2][6] = {
@@ -421,11 +469,19 @@ unsigned long dramc_init(struct dram_para *para)
mctl_setup_dram_clock(para->clock);
/* reset external DRAM */
+#ifndef CONFIG_SUN7I
+ mctl_ddr3_reset();
+#endif
mctl_set_drive();
/* dram clock off */
dramc_clock_output_en(0);
+#ifdef CONFIG_SUN4I
+ /* select dram controller 1 */
+ writel(DRAM_CSEL_MAGIC, &dram->csel);
+#endif
+
mctl_itm_disable();
mctl_enable_dll0(para->tpr3);
@@ -482,6 +538,9 @@ unsigned long dramc_init(struct dram_para *para)
mctl_ddr3_reset();
else
setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+#else
+ /* dram clock on */
+ dramc_clock_output_en(1);
#endif
udelay(1);
@@ -490,6 +549,22 @@ unsigned long dramc_init(struct dram_para *para)
mctl_enable_dllx(para->tpr3);
+#ifdef CONFIG_SUN4I
+ /* set odt impedance divide ratio */
+ reg_val = ((para->zq) >> 8) & 0xfffff;
+ reg_val |= ((para->zq) & 0xff) << 20;
+ reg_val |= (para->zq) & 0xf0000000;
+ writel(reg_val, &dram->zqcr0);
+#endif
+
+#ifdef CONFIG_SUN4I
+ /* set I/O configure register */
+ reg_val = 0x00cc0000;
+ reg_val |= (para->odt_en) & 0x3;
+ reg_val |= ((para->odt_en) & 0x3) << 30;
+ writel(reg_val, &dram->iocr);
+#endif
+
/* set refresh period */
dramc_set_autorefresh_cycle(para->clock, para->type - 2, density);
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index cbf8f08..4902d70 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -10,4 +10,5 @@
#
obj-y += board.o
obj-$(CONFIG_SUNXI_GMAC) += gmac.o
+obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o
obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o
diff --git a/board/sunxi/dram_cubieboard.c b/board/sunxi/dram_cubieboard.c
new file mode 100644
index 0000000..399028c
--- /dev/null
+++ b/board/sunxi/dram_cubieboard.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 480,
+ .type = 3,
+ .rank_num = 1,
+ .density = 4096,
+ .io_width = 16,
+ .bus_width = 32,
+ .cas = 6,
+ .zq = 123,
+ .odt_en = 0,
+ .size = 1024,
+ .tpr0 = 0x30926692,
+ .tpr1 = 0x1090,
+ .tpr2 = 0x1a0c8,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0,
+ .emr2 = 0,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/boards.cfg b/boards.cfg
index 4760a1f..d7c6847 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -381,6 +381,7 @@ Active arm armv7 rmobile renesas lager
Active arm armv7 s5pc1xx samsung goni s5p_goni - Przemyslaw Marczak <p.marczak@samsung.com>
Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
+Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL Hans de Goede <hdegoede@redhat.com>
Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII -
Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII -
Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org>
diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h
new file mode 100644
index 0000000..6560b65
--- /dev/null
+++ b/include/configs/sun4i.h
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * Configuration settings for the Allwinner A10 (sun4i) CPU
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A10 specific configuration
+ */
+#define CONFIG_SUN4I /* sun4i SoC generation */
+
+#define CONFIG_SYS_PROMPT "sun4i# "
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
--
1.9.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [U-Boot] [PATCH v2 05/12] sunxi: Add sun4i support
2014-06-03 19:41 ` [U-Boot] [PATCH v2 05/12] sunxi: Add sun4i support Hans de Goede
@ 2014-06-05 18:13 ` Ian Campbell
0 siblings, 0 replies; 27+ messages in thread
From: Ian Campbell @ 2014-06-05 18:13 UTC (permalink / raw)
To: u-boot
On Tue, 2014-06-03 at 21:41 +0200, Hans de Goede wrote:
> Add support for the Allwinner A10 SoC also known as the Allwinner sun4i family,
> and add the Cubieboard board which uses the A10 SoC.
>
> Compared to sun7 only the DRAM controller is a bit different:
> -Controller reset bits are inverted, but only for Rev. A
> -Different hpcr values
> -No MBUS on sun4i
> -Various other initialization changes
>
> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v2 06/12] sunxi: Add sun5i support
2014-06-03 19:41 [U-Boot] [PATCH v2 00/12] sunxi: Bug fixes, sun4i and sun5i support, pmic support and network improvements Hans de Goede
` (4 preceding siblings ...)
2014-06-03 19:41 ` [U-Boot] [PATCH v2 05/12] sunxi: Add sun4i support Hans de Goede
@ 2014-06-03 19:41 ` Hans de Goede
2014-06-05 18:14 ` Ian Campbell
2014-06-03 19:41 ` [U-Boot] [PATCH v2 07/12] sunxi: Add i2c support Hans de Goede
` (5 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Hans de Goede @ 2014-06-03 19:41 UTC (permalink / raw)
To: u-boot
Add support for the Allwinner A13 and A10s SoCs also know as the Allwinner
sun5i family, and the A13-OLinuXinoM A13 based and r7-tv-dongle A10s based
boards.
The only differences compared to the already supported sun4i and sun7i
families are all in the DRAM controller initialization:
-Different hcpr values
-Different MBUS settings
-Some other small initialization changes
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
arch/arm/cpu/armv7/sunxi/Makefile | 2 ++
arch/arm/cpu/armv7/sunxi/board.c | 12 ++++++++++++
arch/arm/cpu/armv7/sunxi/cpu_info.c | 8 ++++++++
arch/arm/cpu/armv7/sunxi/dram.c | 21 +++++++++++++++++++++
board/sunxi/Makefile | 2 ++
board/sunxi/dram_a13_oli_micro.c | 32 ++++++++++++++++++++++++++++++++
board/sunxi/dram_r7dongle.c | 31 +++++++++++++++++++++++++++++++
boards.cfg | 2 ++
include/configs/sun5i.h | 23 +++++++++++++++++++++++
include/configs/sunxi-common.h | 2 ++
10 files changed, 135 insertions(+)
create mode 100644 board/sunxi/dram_a13_oli_micro.c
create mode 100644 board/sunxi/dram_r7dongle.c
create mode 100644 include/configs/sun5i.h
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 856d353..6c70639 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -12,6 +12,7 @@ obj-y += board.o
obj-y += clock.o
obj-y += pinmux.o
obj-$(CONFIG_SUN4I) += clock_sun4i.o
+obj-$(CONFIG_SUN5I) += clock_sun4i.o
obj-$(CONFIG_SUN7I) += clock_sun4i.o
ifndef CONFIG_SPL_BUILD
@@ -20,6 +21,7 @@ endif
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SUN4I) += dram.o
+obj-$(CONFIG_SUN5I) += dram.o
obj-$(CONFIG_SUN7I) += dram.o
ifdef CONFIG_SPL_FEL
obj-y += start.o
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index c80b421..0118f5b 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -47,9 +47,21 @@ u32 spl_boot_mode(void)
int gpio_init(void)
{
+#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
+ sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
+ sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
+#else
+#error Unsupported console port number. Please fix pin mux settings in board.c
+#endif
return 0;
}
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index b4b5089..5cf35ac 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -15,6 +15,14 @@ int print_cpuinfo(void)
{
#ifdef CONFIG_SUN4I
puts("CPU: Allwinner A10 (SUN4I)\n");
+#elif defined CONFIG_SUN5I
+ u32 val = readl(SUNXI_SID_BASE + 0x08);
+ switch ((val >> 12) & 0xf) {
+ case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break;
+ case 3: puts("CPU: Allwinner A13 (SUN5I)\n"); break;
+ case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break;
+ default: puts("CPU: Allwinner A1X (SUN5I)\n");
+ }
#elif defined CONFIG_SUN7I
puts("CPU: Allwinner A20 (SUN7I)\n");
#else
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 1de7529..0f1ceec 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -155,6 +155,16 @@ static void mctl_enable_dllx(u32 phase)
}
static u32 hpcr_value[32] = {
+#ifdef CONFIG_SUN5I
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0x1031, 0x1031, 0x0735, 0x1035,
+ 0x1035, 0x0731, 0x1031, 0,
+ 0x0301, 0x0301, 0x0301, 0x0301,
+ 0x0301, 0x0301, 0x0301, 0
+#endif
#ifdef CONFIG_SUN4I
0x0301, 0x0301, 0x0301, 0x0301,
0x0301, 0x0301, 0, 0,
@@ -257,9 +267,15 @@ static void mctl_setup_dram_clock(u32 clk)
#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
/* setup MBUS clock */
reg_val = CCM_MBUS_CTRL_GATE |
+#ifdef CONFIG_SUN7I
CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) |
CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
+#else /* defined(CONFIG_SUN5I) */
+ CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) |
+ CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
+ CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
+#endif
writel(reg_val, &ccm->mbus_clk_cfg);
#endif
@@ -468,6 +484,11 @@ unsigned long dramc_init(struct dram_para *para)
/* setup DRAM relative clock */
mctl_setup_dram_clock(para->clock);
+#ifdef CONFIG_SUN5I
+ /* Disable any pad power save control */
+ writel(0, &dram->ppwrsctl);
+#endif
+
/* reset external DRAM */
#ifndef CONFIG_SUN7I
mctl_ddr3_reset();
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index 4902d70..7083632 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -10,5 +10,7 @@
#
obj-y += board.o
obj-$(CONFIG_SUNXI_GMAC) += gmac.o
+obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o
obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o
obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o
+obj-$(CONFIG_R7DONGLE) += dram_r7dongle.o
diff --git a/board/sunxi/dram_a13_oli_micro.c b/board/sunxi/dram_a13_oli_micro.c
new file mode 100644
index 0000000..8154ea2
--- /dev/null
+++ b/board/sunxi/dram_a13_oli_micro.c
@@ -0,0 +1,32 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 408,
+ .type = 3,
+ .rank_num = 1,
+ .density = 2048,
+ .io_width = 16,
+ .bus_width = 16,
+ .cas = 9,
+ .zq = 123,
+ .odt_en = 0,
+ .size = 256,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0,
+ .emr2 = 0x10,
+ .emr3 = 0,
+
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_r7dongle.c b/board/sunxi/dram_r7dongle.c
new file mode 100644
index 0000000..59343cb
--- /dev/null
+++ b/board/sunxi/dram_r7dongle.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 384,
+ .type = 3,
+ .rank_num = 1,
+ .density = 2048,
+ .io_width = 8,
+ .bus_width = 32,
+ .cas = 9,
+ .zq = 123,
+ .odt_en = 0,
+ .size = 1024,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0x04,
+ .emr2 = 0x10,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/boards.cfg b/boards.cfg
index d7c6847..f2da564 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -381,9 +381,11 @@ Active arm armv7 rmobile renesas lager
Active arm armv7 s5pc1xx samsung goni s5p_goni - Przemyslaw Marczak <p.marczak@samsung.com>
Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
+Active arm armv7 sunxi - sunxi A13-OLinuXinoM sun5i:A13_OLINUXINOM,SPL,CONS_INDEX=2 Hans de Goede <hdegoede@redhat.com>
Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL Hans de Goede <hdegoede@redhat.com>
Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII -
Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII -
+Active arm armv7 sunxi - sunxi r7-tv-dongle sun5i:R7DONGLE,SPL Hans de Goede <hdegoede@redhat.com>
Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org>
Active arm armv7 u8500 st-ericsson u8500 u8500_href - -
Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com>
diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h
new file mode 100644
index 0000000..43f0d67
--- /dev/null
+++ b/include/configs/sun5i.h
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * Configuration settings for the Allwinner A13 (sun5i) CPU
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SUN5I /* sun5i SoC generation */
+
+#define CONFIG_SYS_PROMPT "sun5i# "
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index fd02d0d..1d1c87d 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -161,7 +161,9 @@
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
+#ifndef CONFIG_CONS_INDEX
#define CONFIG_CONS_INDEX 1 /* UART0 */
+#endif
#ifdef CONFIG_SUNXI_GMAC
#define CONFIG_DESIGNWARE_ETH /* GMAC can use designware driver */
--
1.9.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [U-Boot] [PATCH v2 06/12] sunxi: Add sun5i support
2014-06-03 19:41 ` [U-Boot] [PATCH v2 06/12] sunxi: Add sun5i support Hans de Goede
@ 2014-06-05 18:14 ` Ian Campbell
0 siblings, 0 replies; 27+ messages in thread
From: Ian Campbell @ 2014-06-05 18:14 UTC (permalink / raw)
To: u-boot
On Tue, 2014-06-03 at 21:41 +0200, Hans de Goede wrote:
> Add support for the Allwinner A13 and A10s SoCs also know as the Allwinner
> sun5i family, and the A13-OLinuXinoM A13 based and r7-tv-dongle A10s based
> boards.
>
> The only differences compared to the already supported sun4i and sun7i
> families are all in the DRAM controller initialization:
>
> -Different hcpr values
> -Different MBUS settings
> -Some other small initialization changes
>
> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v2 07/12] sunxi: Add i2c support
2014-06-03 19:41 [U-Boot] [PATCH v2 00/12] sunxi: Bug fixes, sun4i and sun5i support, pmic support and network improvements Hans de Goede
` (5 preceding siblings ...)
2014-06-03 19:41 ` [U-Boot] [PATCH v2 06/12] sunxi: Add sun5i support Hans de Goede
@ 2014-06-03 19:41 ` Hans de Goede
2014-06-04 4:34 ` Heiko Schocher
2014-06-03 19:41 ` [U-Boot] [PATCH v2 08/12] sunxi: Add axp209 pmic support Hans de Goede
` (4 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Hans de Goede @ 2014-06-03 19:41 UTC (permalink / raw)
To: u-boot
Add support for the i2c controller found on all Allwinner sunxi SoCs,
this is the same controller as found on the Marvell orion5x and kirkwood
SoC families, with a slightly different register layout, so this patch uses
the existing mvtwsi code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
arch/arm/cpu/armv7/sunxi/board.c | 6 ++++++
arch/arm/include/asm/arch-sunxi/i2c.h | 15 +++++++++++++++
board/sunxi/board.c | 7 +++++++
drivers/i2c/Makefile | 1 +
drivers/i2c/mvtwsi.c | 18 ++++++++++++++++++
include/configs/sunxi-common.h | 9 +++++++++
6 files changed, 56 insertions(+)
create mode 100644 arch/arm/include/asm/arch-sunxi/i2c.h
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 0118f5b..7d86409 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -11,6 +11,7 @@
*/
#include <common.h>
+#include <i2c.h>
#include <netdev.h>
#include <miiphy.h>
#include <serial.h>
@@ -91,11 +92,16 @@ void s_init(void)
clock_init();
timer_init();
gpio_init();
+ i2c_init_board();
#ifdef CONFIG_SPL_BUILD
gd = &gdata;
preloader_console_init();
+#ifdef CONFIG_SPL_I2C_SUPPORT
+ /* Needed early by sunxi_board_init if PMU is enabled */
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
sunxi_board_init();
#endif
}
diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h
new file mode 100644
index 0000000..dc5406b
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/i2c.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _SUNXI_I2C_H_
+#define _SUNXI_I2C_H_
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_I2C_MVTWSI_BASE SUNXI_TWI0_BASE
+/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
+#define CONFIG_SYS_TCLK 24000000
+
+#endif
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index b05d0b9..543b809 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -106,6 +106,13 @@ int board_mmc_init(bd_t *bis)
}
#endif
+void i2c_init_board(void)
+{
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0);
+ clock_twi_onoff(0, 1);
+}
+
#ifdef CONFIG_SPL_BUILD
void sunxi_board_init(void)
{
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index e33586d..494c5c7 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -27,5 +27,6 @@ obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o
obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
+obj-$(CONFIG_SYS_I2C_SUNXI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 5ba0e03..e670515 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -22,6 +22,8 @@
#include <asm/arch/orion5x.h>
#elif defined(CONFIG_KIRKWOOD)
#include <asm/arch/kirkwood.h>
+#elif defined(CONFIG_SUNXI)
+#include <asm/arch/i2c.h>
#else
#error Driver mvtwsi not supported by SoC or board
#endif
@@ -30,6 +32,20 @@
* TWSI register structure
*/
+#ifdef CONFIG_SUNXI
+
+struct mvtwsi_registers {
+ u32 slave_address;
+ u32 xtnd_slave_addr;
+ u32 data;
+ u32 control;
+ u32 status;
+ u32 baudrate;
+ u32 soft_reset;
+};
+
+#else
+
struct mvtwsi_registers {
u32 slave_address;
u32 data;
@@ -43,6 +59,8 @@ struct mvtwsi_registers {
u32 soft_reset;
};
+#endif
+
/*
* Control register fields
*/
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 1d1c87d..2db083c 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -161,6 +161,15 @@
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
+/* I2C */
+#define CONFIG_SPL_I2C_SUPPORT
+/* No CONFIG_SYS_I2C as we use the non converted mvtwsi driver */
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SUNXI
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_I2C_SLAVE 0x7f
+#define CONFIG_CMD_I2C
+
#ifndef CONFIG_CONS_INDEX
#define CONFIG_CONS_INDEX 1 /* UART0 */
#endif
--
1.9.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [U-Boot] [PATCH v2 07/12] sunxi: Add i2c support
2014-06-03 19:41 ` [U-Boot] [PATCH v2 07/12] sunxi: Add i2c support Hans de Goede
@ 2014-06-04 4:34 ` Heiko Schocher
2014-06-09 14:48 ` Hans de Goede
0 siblings, 1 reply; 27+ messages in thread
From: Heiko Schocher @ 2014-06-04 4:34 UTC (permalink / raw)
To: u-boot
Hello Hans,
Am 03.06.2014 21:41, schrieb Hans de Goede:
> Add support for the i2c controller found on all Allwinner sunxi SoCs,
> this is the same controller as found on the Marvell orion5x and kirkwood
> SoC families, with a slightly different register layout, so this patch uses
> the existing mvtwsi code.
>
> Signed-off-by: Hans de Goede<hdegoede@redhat.com>
> Acked-by: Ian Campbell<ijc@hellion.org.uk>
> ---
> arch/arm/cpu/armv7/sunxi/board.c | 6 ++++++
> arch/arm/include/asm/arch-sunxi/i2c.h | 15 +++++++++++++++
> board/sunxi/board.c | 7 +++++++
> drivers/i2c/Makefile | 1 +
> drivers/i2c/mvtwsi.c | 18 ++++++++++++++++++
> include/configs/sunxi-common.h | 9 +++++++++
> 6 files changed, 56 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-sunxi/i2c.h
[...]
> diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
> index 1d1c87d..2db083c 100644
> --- a/include/configs/sunxi-common.h
> +++ b/include/configs/sunxi-common.h
> @@ -161,6 +161,15 @@
> #undef CONFIG_CMD_NET
> #undef CONFIG_CMD_NFS
>
> +/* I2C */
> +#define CONFIG_SPL_I2C_SUPPORT
> +/* No CONFIG_SYS_I2C as we use the non converted mvtwsi driver */
> +#define CONFIG_HARD_I2C
NACK. Goal is to get rid of HARD_I2C define ... please convert this
driver to fit with CONFIG_SYS_I2C framework.
A fast look in this driver, this should not to be to hard, as this
driver does not support multi busses...
A good example for porting a i2c driver with no multibus support is:
commit 0bdffe71fddeaa46768a39305797e4512dee0f15
Author: Heiko Schocher <hs@denx.de>
Date: Fri Nov 8 07:30:53 2013 +0100
i2c, zynq: convert zynq i2c driver to new multibus/multiadapter framework
> +#define CONFIG_SYS_I2C_SUNXI
> +#define CONFIG_SYS_I2C_SPEED 400000
> +#define CONFIG_SYS_I2C_SLAVE 0x7f
> +#define CONFIG_CMD_I2C
> +
> #ifndef CONFIG_CONS_INDEX
> #define CONFIG_CONS_INDEX 1 /* UART0 */
> #endif
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 27+ messages in thread* [U-Boot] [PATCH v2 07/12] sunxi: Add i2c support
2014-06-04 4:34 ` Heiko Schocher
@ 2014-06-09 14:48 ` Hans de Goede
0 siblings, 0 replies; 27+ messages in thread
From: Hans de Goede @ 2014-06-09 14:48 UTC (permalink / raw)
To: u-boot
Hi,
On 06/04/2014 06:34 AM, Heiko Schocher wrote:
> Hello Hans,
>
> Am 03.06.2014 21:41, schrieb Hans de Goede:
>> Add support for the i2c controller found on all Allwinner sunxi SoCs,
>> this is the same controller as found on the Marvell orion5x and kirkwood
>> SoC families, with a slightly different register layout, so this patch uses
>> the existing mvtwsi code.
>>
>> Signed-off-by: Hans de Goede<hdegoede@redhat.com>
>> Acked-by: Ian Campbell<ijc@hellion.org.uk>
>> ---
>> arch/arm/cpu/armv7/sunxi/board.c | 6 ++++++
>> arch/arm/include/asm/arch-sunxi/i2c.h | 15 +++++++++++++++
>> board/sunxi/board.c | 7 +++++++
>> drivers/i2c/Makefile | 1 +
>> drivers/i2c/mvtwsi.c | 18 ++++++++++++++++++
>> include/configs/sunxi-common.h | 9 +++++++++
>> 6 files changed, 56 insertions(+)
>> create mode 100644 arch/arm/include/asm/arch-sunxi/i2c.h
> [...]
>> diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
>> index 1d1c87d..2db083c 100644
>> --- a/include/configs/sunxi-common.h
>> +++ b/include/configs/sunxi-common.h
>> @@ -161,6 +161,15 @@
>> #undef CONFIG_CMD_NET
>> #undef CONFIG_CMD_NFS
>>
>> +/* I2C */
>> +#define CONFIG_SPL_I2C_SUPPORT
>> +/* No CONFIG_SYS_I2C as we use the non converted mvtwsi driver */
>> +#define CONFIG_HARD_I2C
>
> NACK. Goal is to get rid of HARD_I2C define ... please convert this
> driver to fit with CONFIG_SYS_I2C framework.
> A fast look in this driver, this should not to be to hard, as this
> driver does not support multi busses...
>
> A good example for porting a i2c driver with no multibus support is:
>
> commit 0bdffe71fddeaa46768a39305797e4512dee0f15
> Author: Heiko Schocher <hs@denx.de>
> Date: Fri Nov 8 07:30:53 2013 +0100
>
> i2c, zynq: convert zynq i2c driver to new multibus/multiadapter framework
Ok, one patch converting the mvtwsi driver to CONFIG_SYS_I2C coming up.
Note I've tested this on multiple sunxi boards / SoC generations, but
I don't have any kirkwood or orion5x boards, so I cannot guarantee that
this patch won't cause regressions there (I've compile tested the patch
with kirkwood and orion5x board configs).
Regards,
Hans
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v2 08/12] sunxi: Add axp209 pmic support
2014-06-03 19:41 [U-Boot] [PATCH v2 00/12] sunxi: Bug fixes, sun4i and sun5i support, pmic support and network improvements Hans de Goede
` (6 preceding siblings ...)
2014-06-03 19:41 ` [U-Boot] [PATCH v2 07/12] sunxi: Add i2c support Hans de Goede
@ 2014-06-03 19:41 ` Hans de Goede
2014-06-05 18:40 ` Ian Campbell
2014-06-03 19:41 ` [U-Boot] [PATCH v2 09/12] sunxi: Add axp152 " Hans de Goede
` (3 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Hans de Goede @ 2014-06-03 19:41 UTC (permalink / raw)
To: u-boot
From: Henrik Nordstrom <henrik@henriknordstrom.net>
Add support for the x-powers axp209 pmic which is found on most A10, A13 and
A20 boards.
And enable AXP209 support for the Cubietruck and Cubieboard boards.
While changing the boards.cfg lines for the Cubietruck, add Ian and me as board
maintainers for the Cubietruck.
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
board/sunxi/board.c | 22 +++++
boards.cfg | 6 +-
drivers/power/Makefile | 1 +
drivers/power/axp209.c | 180 +++++++++++++++++++++++++++++++++++++++++
include/axp209.h | 15 ++++
include/configs/sun4i.h | 1 +
include/configs/sun5i.h | 1 +
include/configs/sun7i.h | 1 +
include/configs/sunxi-common.h | 5 ++
9 files changed, 229 insertions(+), 3 deletions(-)
create mode 100644 drivers/power/axp209.c
create mode 100644 include/axp209.h
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 543b809..8375711 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -12,6 +12,9 @@
*/
#include <common.h>
+#ifdef CONFIG_AXP209_POWER
+#include <axp209.h>
+#endif
#include <asm/arch/clock.h>
#include <asm/arch/dram.h>
#include <asm/arch/gpio.h>
@@ -116,12 +119,31 @@ void i2c_init_board(void)
#ifdef CONFIG_SPL_BUILD
void sunxi_board_init(void)
{
+ int power_failed = 0;
unsigned long ramsize;
+#ifdef CONFIG_AXP209_POWER
+ power_failed |= axp209_init();
+ power_failed |= axp209_set_dcdc2(1400);
+ power_failed |= axp209_set_dcdc3(1250);
+ power_failed |= axp209_set_ldo2(3000);
+ power_failed |= axp209_set_ldo3(2800);
+ power_failed |= axp209_set_ldo4(2800);
+#endif
+
printf("DRAM:");
ramsize = sunxi_dram_init();
printf(" %lu MiB\n", ramsize >> 20);
if (!ramsize)
hang();
+
+ /*
+ * Only clock up the CPU to full speed if we are reasonably
+ * assured it's being powered with suitable core voltage
+ */
+ if (!power_failed)
+ clock_set_pll1(CONFIG_CLK_FULL_SPEED);
+ else
+ printf("Failed to set core voltage! Can't set CPU frequency\n");
}
#endif
diff --git a/boards.cfg b/boards.cfg
index f2da564..151c443 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -382,9 +382,9 @@ Active arm armv7 s5pc1xx samsung goni
Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
Active arm armv7 sunxi - sunxi A13-OLinuXinoM sun5i:A13_OLINUXINOM,SPL,CONS_INDEX=2 Hans de Goede <hdegoede@redhat.com>
-Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL Hans de Goede <hdegoede@redhat.com>
-Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII -
-Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII -
+Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,AXP209_POWER Hans de Goede <hdegoede@redhat.com>
+Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,AXP209_POWER,SUNXI_GMAC,RGMII Ian Campbell <ijc@hellion.org.uk>:Hans de Goede <hdegoede@redhat.com>
+Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII Ian Campbell <ijc@hellion.org.uk>:Hans de Goede <hdegoede@redhat.com>
Active arm armv7 sunxi - sunxi r7-tv-dongle sun5i:R7DONGLE,SPL Hans de Goede <hdegoede@redhat.com>
Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org>
Active arm armv7 u8500 st-ericsson u8500 u8500_href - -
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index 53ff97d..063ac8f 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -5,6 +5,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_AXP209_POWER) += axp209.o
obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o
obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o
obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o
diff --git a/drivers/power/axp209.c b/drivers/power/axp209.c
new file mode 100644
index 0000000..fc1befa
--- /dev/null
+++ b/drivers/power/axp209.c
@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2012
+ * Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <axp209.h>
+
+enum axp209_reg {
+ AXP209_POWER_STATUS = 0x00,
+ AXP209_CHIP_VERSION = 0x03,
+ AXP209_DCDC2_VOLTAGE = 0x23,
+ AXP209_DCDC3_VOLTAGE = 0x27,
+ AXP209_LDO24_VOLTAGE = 0x28,
+ AXP209_LDO3_VOLTAGE = 0x29,
+ AXP209_IRQ_STATUS5 = 0x4c,
+ AXP209_SHUTDOWN = 0x32,
+};
+
+#define AXP209_POWER_STATUS_ON_BY_DC (1 << 0)
+
+#define AXP209_IRQ5_PEK_UP (1 << 6)
+#define AXP209_IRQ5_PEK_DOWN (1 << 5)
+
+#define AXP209_POWEROFF (1 << 7)
+
+static int axp209_write(enum axp209_reg reg, u8 val)
+{
+ return i2c_write(0x34, reg, 1, &val, 1);
+}
+
+static int axp209_read(enum axp209_reg reg, u8 *val)
+{
+ return i2c_read(0x34, reg, 1, val, 1);
+}
+
+static int axp209_mvolt_to_cfg(int mvolt, int min, int max, int div)
+{
+ if (mvolt < min)
+ mvolt = min;
+ else if (mvolt > max)
+ mvolt = max;
+
+ return (mvolt - min) / div;
+}
+
+int axp209_set_dcdc2(int mvolt)
+{
+ int cfg, rc;
+ u8 current;
+
+ cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25);
+
+ /* Do we really need to be this gentle? It has built-in voltage slope */
+ while ((rc = axp209_read(AXP209_DCDC2_VOLTAGE, ¤t)) == 0 &&
+ current != cfg) {
+ if (current < cfg)
+ current++;
+ else
+ current--;
+
+ rc = axp209_write(AXP209_DCDC2_VOLTAGE, current);
+ if (rc)
+ break;
+ }
+
+ return rc;
+}
+
+int axp209_set_dcdc3(int mvolt)
+{
+ int cfg = axp209_mvolt_to_cfg(mvolt, 700, 3500, 25);
+
+ return axp209_write(AXP209_DCDC3_VOLTAGE, cfg);
+}
+
+int axp209_set_ldo2(int mvolt)
+{
+ int rc, cfg;
+ u8 reg;
+
+ cfg = axp209_mvolt_to_cfg(mvolt, 1800, 3300, 100);
+
+ rc = axp209_read(AXP209_LDO24_VOLTAGE, ®);
+ if (rc)
+ return rc;
+
+ /* LDO2 configuration is in upper 4 bits */
+ reg = (reg & 0x0f) | (cfg << 4);
+ return axp209_write(AXP209_LDO24_VOLTAGE, reg);
+}
+
+int axp209_set_ldo3(int mvolt)
+{
+ int cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25);
+
+ if (mvolt == -1)
+ cfg = 0x80; /* determined by LDO3IN pin */
+
+ return axp209_write(AXP209_LDO3_VOLTAGE, cfg);
+}
+
+int axp209_set_ldo4(int mvolt)
+{
+ int cfg, rc;
+ static const int vindex[] = {
+ 1250, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2500,
+ 2700, 2800, 3000, 3100, 3200, 3300
+ };
+ u8 reg;
+
+ /* Translate mvolt to register cfg value, requested <= selected */
+ for (cfg = 15; vindex[cfg] > mvolt && cfg > 0; cfg--);
+
+ rc = axp209_read(AXP209_LDO24_VOLTAGE, ®);
+ if (rc)
+ return rc;
+
+ /* LDO4 configuration is in lower 4 bits */
+ reg = (reg & 0xf0) | (cfg << 0);
+ return axp209_write(AXP209_LDO24_VOLTAGE, reg);
+}
+
+void axp209_poweroff(void)
+{
+ u8 val;
+
+ if (axp209_read(AXP209_SHUTDOWN, &val) != 0)
+ return;
+
+ val |= AXP209_POWEROFF;
+
+ if (axp209_write(AXP209_SHUTDOWN, val) != 0)
+ return;
+
+ udelay(10000); /* wait for power to drain */
+}
+
+int axp209_init(void)
+{
+ u8 ver;
+ int rc;
+
+ rc = axp209_read(AXP209_CHIP_VERSION, &ver);
+ if (rc)
+ return rc;
+
+ /* Low 4 bits is chip version */
+ ver &= 0x0f;
+
+ if (ver != 0x1)
+ return -1;
+
+ return 0;
+}
+
+int axp209_poweron_by_dc(void)
+{
+ u8 v;
+
+ if (axp209_read(AXP209_POWER_STATUS, &v))
+ return 0;
+
+ return (v & AXP209_POWER_STATUS_ON_BY_DC);
+}
+
+int axp209_power_button(void)
+{
+ u8 v;
+
+ if (axp209_read(AXP209_IRQ_STATUS5, &v))
+ return 0;
+
+ axp209_write(AXP209_IRQ_STATUS5, AXP209_IRQ5_PEK_DOWN);
+
+ return v & AXP209_IRQ5_PEK_DOWN;
+}
diff --git a/include/axp209.h b/include/axp209.h
new file mode 100644
index 0000000..9edfa3f
--- /dev/null
+++ b/include/axp209.h
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+extern int axp209_set_dcdc2(int mvolt);
+extern int axp209_set_dcdc3(int mvolt);
+extern int axp209_set_ldo2(int mvolt);
+extern int axp209_set_ldo3(int mvolt);
+extern int axp209_set_ldo4(int mvolt);
+extern void axp209_poweroff(void);
+extern int axp209_init(void);
+extern int axp209_poweron_by_dc(void);
+extern int axp209_power_button(void);
diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h
index 6560b65..037f995 100644
--- a/include/configs/sun4i.h
+++ b/include/configs/sun4i.h
@@ -12,6 +12,7 @@
* A10 specific configuration
*/
#define CONFIG_SUN4I /* sun4i SoC generation */
+#define CONFIG_CLK_FULL_SPEED 1008000000
#define CONFIG_SYS_PROMPT "sun4i# "
diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h
index 43f0d67..c6138b7 100644
--- a/include/configs/sun5i.h
+++ b/include/configs/sun5i.h
@@ -12,6 +12,7 @@
* High Level Configuration Options
*/
#define CONFIG_SUN5I /* sun5i SoC generation */
+#define CONFIG_CLK_FULL_SPEED 1008000000
#define CONFIG_SYS_PROMPT "sun5i# "
diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
index 9b693f7..d9be104 100644
--- a/include/configs/sun7i.h
+++ b/include/configs/sun7i.h
@@ -13,6 +13,7 @@
* A20 specific configuration
*/
#define CONFIG_SUN7I /* sun7i SoC generation */
+#define CONFIG_CLK_FULL_SPEED 912000000
#define CONFIG_SYS_PROMPT "sun7i# "
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 2db083c..b76227e 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -170,6 +170,11 @@
#define CONFIG_SYS_I2C_SLAVE 0x7f
#define CONFIG_CMD_I2C
+/* PMU */
+#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER
+#define CONFIG_SPL_POWER_SUPPORT
+#endif
+
#ifndef CONFIG_CONS_INDEX
#define CONFIG_CONS_INDEX 1 /* UART0 */
#endif
--
1.9.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [U-Boot] [PATCH v2 08/12] sunxi: Add axp209 pmic support
2014-06-03 19:41 ` [U-Boot] [PATCH v2 08/12] sunxi: Add axp209 pmic support Hans de Goede
@ 2014-06-05 18:40 ` Ian Campbell
2014-06-09 8:25 ` Hans de Goede
0 siblings, 1 reply; 27+ messages in thread
From: Ian Campbell @ 2014-06-05 18:40 UTC (permalink / raw)
To: u-boot
On Tue, 2014-06-03 at 21:41 +0200, Hans de Goede wrote:
> +int axp209_set_ldo3(int mvolt)
> +{
> + int cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25);
> +
> + if (mvolt == -1)
> + cfg = 0x80; /* determined by LDO3IN pin */
Thus would seem more natural as
if (mvolt == -1)
cfg = 0x80; /* comment... */
else
cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25);
BTW, I've just noticed that cfg is often an int but axp209_write etc all
deal in u8's. Do you not want to be dealing with u8's throughout?
> +void axp209_poweroff(void)
> +{
> + u8 val;
> +
> + if (axp209_read(AXP209_SHUTDOWN, &val) != 0)
> + return;
> +
> + val |= AXP209_POWEROFF;
> +
> + if (axp209_write(AXP209_SHUTDOWN, val) != 0)
> + return;
> +
> + udelay(10000); /* wait for power to drain */
Is this essentially a "wait to die" loop? i.e. we expect power to
disappear while in the middle of it. In which case shouldn't it be
infinite? What would happen if we were to return from this function?
Nothing actually calls it AFAICT so maybe you can just punt on the whole
thing and drop the function for now...
Ian.
^ permalink raw reply [flat|nested] 27+ messages in thread* [U-Boot] [PATCH v2 08/12] sunxi: Add axp209 pmic support
2014-06-05 18:40 ` Ian Campbell
@ 2014-06-09 8:25 ` Hans de Goede
2014-06-09 8:50 ` Ian Campbell
0 siblings, 1 reply; 27+ messages in thread
From: Hans de Goede @ 2014-06-09 8:25 UTC (permalink / raw)
To: u-boot
Hi,
On 06/05/2014 08:40 PM, Ian Campbell wrote:
> On Tue, 2014-06-03 at 21:41 +0200, Hans de Goede wrote:
>> +int axp209_set_ldo3(int mvolt)
>> +{
>> + int cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25);
>> +
>> + if (mvolt == -1)
>> + cfg = 0x80; /* determined by LDO3IN pin */
>
> Thus would seem more natural as
> if (mvolt == -1)
> cfg = 0x80; /* comment... */
> else
> cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25);
>
I Agree that that would be better, fixed in my tree:
https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-upstreaming
Note I often rebase + force push this branch.
> BTW, I've just noticed that cfg is often an int but axp209_write etc all
> deal in u8's. Do you not want to be dealing with u8's throughout?
Agreed that this should be u8 everywhere, fixed this for both the axp209
and axp152 code.
Note I won't be re-posting these until the i2c controller conversion to
the CONFIG_SYS_I2C framework is sorted out.
>> +void axp209_poweroff(void)
>> +{
>> + u8 val;
>> +
>> + if (axp209_read(AXP209_SHUTDOWN, &val) != 0)
>> + return;
>> +
>> + val |= AXP209_POWEROFF;
>> +
>> + if (axp209_write(AXP209_SHUTDOWN, val) != 0)
>> + return;
>> +
>> + udelay(10000); /* wait for power to drain */
>
> Is this essentially a "wait to die" loop? i.e. we expect power to
> disappear while in the middle of it. In which case shouldn't it be
> infinite? What would happen if we were to return from this function?
> Nothing actually calls it AFAICT so maybe you can just punt on the whole
> thing and drop the function for now...
I agree that just dropping this function for now is best, done.
Regards,
Hans
^ permalink raw reply [flat|nested] 27+ messages in thread* [U-Boot] [PATCH v2 08/12] sunxi: Add axp209 pmic support
2014-06-09 8:25 ` Hans de Goede
@ 2014-06-09 8:50 ` Ian Campbell
2014-06-09 8:59 ` Hans de Goede
0 siblings, 1 reply; 27+ messages in thread
From: Ian Campbell @ 2014-06-09 8:50 UTC (permalink / raw)
To: u-boot
On Mon, 2014-06-09 at 10:25 +0200, Hans de Goede wrote:
> https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-upstreaming
>
> Note I often rebase + force push this branch.
I noticed ;-)
> Note I won't be re-posting these until the i2c controller conversion to
> the CONFIG_SYS_I2C framework is sorted out.
No problem. Is that a big rework then?
How would you feel about reordering things a bit to push the i2c/power
and sun[45]i stuff to the end, most of the rest looks more or less
trivial/uncontroversial to me and could potentially be applied sooner
rather than later (ulterior motive: this would unblock my AHCI
patches ;-))
If you are ok with that in principal then I'm more than happy to do the
leg work of git rebase -i.
Ian.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v2 08/12] sunxi: Add axp209 pmic support
2014-06-09 8:50 ` Ian Campbell
@ 2014-06-09 8:59 ` Hans de Goede
2014-06-09 9:06 ` Albert ARIBAUD
2014-06-09 10:09 ` Ian Campbell
0 siblings, 2 replies; 27+ messages in thread
From: Hans de Goede @ 2014-06-09 8:59 UTC (permalink / raw)
To: u-boot
Hi,
On 06/09/2014 10:50 AM, Ian Campbell wrote:
> On Mon, 2014-06-09 at 10:25 +0200, Hans de Goede wrote:
>> https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-upstreaming
>>
>> Note I often rebase + force push this branch.
>
> I noticed ;-)
>
>> Note I won't be re-posting these until the i2c controller conversion to
>> the CONFIG_SYS_I2C framework is sorted out.
>
> No problem. Is that a big rework then?
Not all that big, I'm working on it now, I hope to have it finished by the
end of today.
> How would you feel about reordering things a bit to push the i2c/power
> and sun[45]i stuff to the end, most of the rest looks more or less
> trivial/uncontroversial to me and could potentially be applied sooner
> rather than later (ulterior motive: this would unblock my AHCI
> patches ;-))
I agree, actually if you look in where your u-boot list mails go you will
see a pull-req to Albert there for the entire set I've been working on minus
the i2c + axp patches :)
Regards,
Hans
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v2 08/12] sunxi: Add axp209 pmic support
2014-06-09 8:59 ` Hans de Goede
@ 2014-06-09 9:06 ` Albert ARIBAUD
2014-06-09 9:08 ` Hans de Goede
2014-06-09 10:09 ` Ian Campbell
1 sibling, 1 reply; 27+ messages in thread
From: Albert ARIBAUD @ 2014-06-09 9:06 UTC (permalink / raw)
To: u-boot
Hi Hans,
On Mon, 09 Jun 2014 10:59:19 +0200, Hans de Goede <hdegoede@redhat.com>
wrote:
> Hi,
>
> On 06/09/2014 10:50 AM, Ian Campbell wrote:
> > On Mon, 2014-06-09 at 10:25 +0200, Hans de Goede wrote:
> >> https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-upstreaming
> >>
> >> Note I often rebase + force push this branch.
> >
> > I noticed ;-)
> >
> >> Note I won't be re-posting these until the i2c controller conversion to
> >> the CONFIG_SYS_I2C framework is sorted out.
> >
> > No problem. Is that a big rework then?
>
> Not all that big, I'm working on it now, I hope to have it finished by the
> end of today.
>
> > How would you feel about reordering things a bit to push the i2c/power
> > and sun[45]i stuff to the end, most of the rest looks more or less
> > trivial/uncontroversial to me and could potentially be applied sooner
> > rather than later (ulterior motive: this would unblock my AHCI
> > patches ;-))
>
> I agree, actually if you look in where your u-boot list mails go you will
> see a pull-req to Albert there for the entire set I've been working on minus
> the i2c + axp patches :)
Don't bother with the pull request, as I only apply PRs from git.denx.de
U-Boot repositories. I will happily apply your series from Patchwork.
Just make sure it is properly assigned to me.
> Regards,
>
> Hans
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v2 08/12] sunxi: Add axp209 pmic support
2014-06-09 9:06 ` Albert ARIBAUD
@ 2014-06-09 9:08 ` Hans de Goede
0 siblings, 0 replies; 27+ messages in thread
From: Hans de Goede @ 2014-06-09 9:08 UTC (permalink / raw)
To: u-boot
Hi,
On 06/09/2014 11:06 AM, Albert ARIBAUD wrote:
> Hi Hans,
>
> On Mon, 09 Jun 2014 10:59:19 +0200, Hans de Goede <hdegoede@redhat.com>
> wrote:
>
>> Hi,
>>
>> On 06/09/2014 10:50 AM, Ian Campbell wrote:
>>> On Mon, 2014-06-09 at 10:25 +0200, Hans de Goede wrote:
>>>> https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-upstreaming
>>>>
>>>> Note I often rebase + force push this branch.
>>>
>>> I noticed ;-)
>>>
>>>> Note I won't be re-posting these until the i2c controller conversion to
>>>> the CONFIG_SYS_I2C framework is sorted out.
>>>
>>> No problem. Is that a big rework then?
>>
>> Not all that big, I'm working on it now, I hope to have it finished by the
>> end of today.
>>
>>> How would you feel about reordering things a bit to push the i2c/power
>>> and sun[45]i stuff to the end, most of the rest looks more or less
>>> trivial/uncontroversial to me and could potentially be applied sooner
>>> rather than later (ulterior motive: this would unblock my AHCI
>>> patches ;-))
>>
>> I agree, actually if you look in where your u-boot list mails go you will
>> see a pull-req to Albert there for the entire set I've been working on minus
>> the i2c + axp patches :)
>
> Don't bother with the pull request, as I only apply PRs from git.denx.de
> U-Boot repositories. I will happily apply your series from Patchwork.
> Just make sure it is properly assigned to me.
Ok, since I dropped some patches which need more work from the series, some
of the latter ones needed some manual rebasing to apply. So I will send
a new version of the set. How do I ensure that those patches end up being
assigned to you ? So far I've been sending my patches with you as the "To"
of the emails and the list in the Cc, is that sufficient ?
Regards,
Hans
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v2 08/12] sunxi: Add axp209 pmic support
2014-06-09 8:59 ` Hans de Goede
2014-06-09 9:06 ` Albert ARIBAUD
@ 2014-06-09 10:09 ` Ian Campbell
1 sibling, 0 replies; 27+ messages in thread
From: Ian Campbell @ 2014-06-09 10:09 UTC (permalink / raw)
To: u-boot
On Mon, 2014-06-09 at 10:59 +0200, Hans de Goede wrote:
> > How would you feel about reordering things a bit to push the i2c/power
> > and sun[45]i stuff to the end, most of the rest looks more or less
> > trivial/uncontroversial to me and could potentially be applied sooner
> > rather than later (ulterior motive: this would unblock my AHCI
> > patches ;-))
>
> I agree, actually if you look in where your u-boot list mails go you will
> see a pull-req to Albert there for the entire set I've been working on minus
> the i2c + axp patches :)
Awesome, thanks!
Ian.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v2 09/12] sunxi: Add axp152 pmic support
2014-06-03 19:41 [U-Boot] [PATCH v2 00/12] sunxi: Bug fixes, sun4i and sun5i support, pmic support and network improvements Hans de Goede
` (7 preceding siblings ...)
2014-06-03 19:41 ` [U-Boot] [PATCH v2 08/12] sunxi: Add axp209 pmic support Hans de Goede
@ 2014-06-03 19:41 ` Hans de Goede
2014-06-05 18:48 ` Ian Campbell
2014-06-03 19:42 ` [U-Boot] [PATCH v2 10/12] net: Rename and cleanup sunxi (Allwinner) emac driver Hans de Goede
` (2 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Hans de Goede @ 2014-06-03 19:41 UTC (permalink / raw)
To: u-boot
Add support for the x-powers axp152 pmic which is found on most A10s boards
and enable it for the r7-tv-dongle board.
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
board/sunxi/board.c | 10 +++++
boards.cfg | 2 +-
drivers/power/Makefile | 1 +
drivers/power/axp152.c | 112 +++++++++++++++++++++++++++++++++++++++++++++++++
include/axp152.h | 11 +++++
5 files changed, 135 insertions(+), 1 deletion(-)
create mode 100644 drivers/power/axp152.c
create mode 100644 include/axp152.h
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 8375711..8607eb3 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -12,6 +12,9 @@
*/
#include <common.h>
+#ifdef CONFIG_AXP152_POWER
+#include <axp152.h>
+#endif
#ifdef CONFIG_AXP209_POWER
#include <axp209.h>
#endif
@@ -122,6 +125,13 @@ void sunxi_board_init(void)
int power_failed = 0;
unsigned long ramsize;
+#ifdef CONFIG_AXP152_POWER
+ power_failed = axp152_init();
+ power_failed |= axp152_set_dcdc2(1400);
+ power_failed |= axp152_set_dcdc3(1500);
+ power_failed |= axp152_set_dcdc4(1250);
+ power_failed |= axp152_set_ldo2(3000);
+#endif
#ifdef CONFIG_AXP209_POWER
power_failed |= axp209_init();
power_failed |= axp209_set_dcdc2(1400);
diff --git a/boards.cfg b/boards.cfg
index 151c443..827095d 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -385,7 +385,7 @@ Active arm armv7 sunxi - sunxi
Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,AXP209_POWER Hans de Goede <hdegoede@redhat.com>
Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,AXP209_POWER,SUNXI_GMAC,RGMII Ian Campbell <ijc@hellion.org.uk>:Hans de Goede <hdegoede@redhat.com>
Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII Ian Campbell <ijc@hellion.org.uk>:Hans de Goede <hdegoede@redhat.com>
-Active arm armv7 sunxi - sunxi r7-tv-dongle sun5i:R7DONGLE,SPL Hans de Goede <hdegoede@redhat.com>
+Active arm armv7 sunxi - sunxi r7-tv-dongle sun5i:R7DONGLE,SPL,AXP152_POWER Hans de Goede <hdegoede@redhat.com>
Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org>
Active arm armv7 u8500 st-ericsson u8500 u8500_href - -
Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com>
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index 063ac8f..dc64e4d 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -5,6 +5,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_AXP152_POWER) += axp152.o
obj-$(CONFIG_AXP209_POWER) += axp209.o
obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o
obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o
diff --git a/drivers/power/axp152.c b/drivers/power/axp152.c
new file mode 100644
index 0000000..a7c0bc2
--- /dev/null
+++ b/drivers/power/axp152.c
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2012
+ * Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <i2c.h>
+#include <axp152.h>
+
+enum axp152_reg {
+ AXP152_CHIP_VERSION = 0x3,
+ AXP152_DCDC2_VOLTAGE = 0x23,
+ AXP152_DCDC3_VOLTAGE = 0x27,
+ AXP152_DCDC4_VOLTAGE = 0x2B,
+ AXP152_LDO2_VOLTAGE = 0x2A,
+ AXP152_SHUTDOWN = 0x32,
+};
+
+#define AXP152_POWEROFF (1 << 7)
+
+static int axp152_write(enum axp152_reg reg, u8 val)
+{
+ return i2c_write(0x30, reg, 1, &val, 1);
+}
+
+static int axp152_read(enum axp152_reg reg, u8 *val)
+{
+ return i2c_read(0x30, reg, 1, val, 1);
+}
+
+static int axp152_mvolt_to_target(int mvolt, int min, int max, int div)
+{
+ if (mvolt < min)
+ mvolt = min;
+ else if (mvolt > max)
+ mvolt = max;
+
+ return (mvolt - min) / div;
+}
+
+int axp152_set_dcdc2(int mvolt)
+{
+ int rc, target;
+ u8 current;
+
+ target = axp152_mvolt_to_target(mvolt, 700, 2275, 25);
+
+ /* Do we really need to be this gentle? It has built-in voltage slope */
+ while ((rc = axp152_read(AXP152_DCDC2_VOLTAGE, ¤t)) == 0 &&
+ current != target) {
+ if (current < target)
+ current++;
+ else
+ current--;
+ rc = axp152_write(AXP152_DCDC2_VOLTAGE, current);
+ if (rc)
+ break;
+ }
+ return rc;
+}
+
+int axp152_set_dcdc3(int mvolt)
+{
+ int target = axp152_mvolt_to_target(mvolt, 700, 3500, 25);
+
+ return axp152_write(AXP152_DCDC3_VOLTAGE, target);
+}
+
+int axp152_set_dcdc4(int mvolt)
+{
+ int target = axp152_mvolt_to_target(mvolt, 700, 3500, 25);
+
+ return axp152_write(AXP152_DCDC4_VOLTAGE, target);
+}
+
+int axp152_set_ldo2(int mvolt)
+{
+ int target = axp152_mvolt_to_target(mvolt, 700, 3500, 100);
+
+ return axp152_write(AXP152_LDO2_VOLTAGE, target);
+}
+
+void axp152_poweroff(void)
+{
+ u8 val;
+
+ if (axp152_read(AXP152_SHUTDOWN, &val) != 0)
+ return;
+
+ val |= AXP152_POWEROFF;
+
+ if (axp152_write(AXP152_SHUTDOWN, val) != 0)
+ return;
+
+ udelay(10000); /* wait for power to drain */
+}
+
+int axp152_init(void)
+{
+ u8 ver;
+ int rc;
+
+ rc = axp152_read(AXP152_CHIP_VERSION, &ver);
+ if (rc)
+ return rc;
+
+ if (ver != 0x05)
+ return -1;
+
+ return 0;
+}
diff --git a/include/axp152.h b/include/axp152.h
new file mode 100644
index 0000000..b34c194
--- /dev/null
+++ b/include/axp152.h
@@ -0,0 +1,11 @@
+/*
+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+int axp152_set_dcdc2(int mvolt);
+int axp152_set_dcdc3(int mvolt);
+int axp152_set_dcdc4(int mvolt);
+int axp152_set_ldo2(int mvolt);
+void axp152_poweroff(void);
+int axp152_init(void);
--
1.9.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [U-Boot] [PATCH v2 10/12] net: Rename and cleanup sunxi (Allwinner) emac driver
2014-06-03 19:41 [U-Boot] [PATCH v2 00/12] sunxi: Bug fixes, sun4i and sun5i support, pmic support and network improvements Hans de Goede
` (8 preceding siblings ...)
2014-06-03 19:41 ` [U-Boot] [PATCH v2 09/12] sunxi: Add axp152 " Hans de Goede
@ 2014-06-03 19:42 ` Hans de Goede
2014-06-03 19:42 ` [U-Boot] [PATCH v2 11/12] sunxi: Add emac glue, enable emac on the cubieboard Hans de Goede
2014-06-03 19:42 ` [U-Boot] [PATCH v2 12/12] sunxi: Add support for using MII phy-s with the GMAC nic Hans de Goede
11 siblings, 0 replies; 27+ messages in thread
From: Hans de Goede @ 2014-06-03 19:42 UTC (permalink / raw)
To: u-boot
From: Stefan Roese <sr@denx.de>
There have been 3 versions of the sunxi_emac support patch during its
development. Somehow version 2 ended up in upstream u-boot where as
the u-boot-sunxi git repo got version 3.
This bumps the version in upstream u-boot to version 3 of the patch:
- Initialize MII clock earlier so mii access to allow independent use
- Name change from WEMAC to EMAC to match mainline kernel & chip manual
- Cosmetic code cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
drivers/net/Makefile | 2 +-
drivers/net/sunxi_emac.c | 521 +++++++++++++++++++++++++++++++++++++++++++++
drivers/net/sunxi_wemac.c | 525 ----------------------------------------------
include/netdev.h | 2 +-
4 files changed, 523 insertions(+), 527 deletions(-)
create mode 100644 drivers/net/sunxi_emac.c
delete mode 100644 drivers/net/sunxi_wemac.c
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 6005f7e..da2b5f8 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_DNET) += dnet.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
+obj-$(CONFIG_SUNXI_EMAC) += sunxi_emac.o
obj-$(CONFIG_ENC28J60) += enc28j60.o
obj-$(CONFIG_EP93XX) += ep93xx_eth.o
obj-$(CONFIG_ETHOC) += ethoc.o
@@ -51,7 +52,6 @@ obj-$(CONFIG_RTL8169) += rtl8169.o
obj-$(CONFIG_SH_ETHER) += sh_eth.o
obj-$(CONFIG_SMC91111) += smc91111.o
obj-$(CONFIG_SMC911X) += smc911x.o
-obj-$(CONFIG_SUNXI_WEMAC) += sunxi_wemac.o
obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
new file mode 100644
index 0000000..5a06d68
--- /dev/null
+++ b/drivers/net/sunxi_emac.c
@@ -0,0 +1,521 @@
+/*
+ * sunxi_emac.c -- Allwinner A10 ethernet driver
+ *
+ * (C) Copyright 2012, Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+
+/* EMAC register */
+struct emac_regs {
+ u32 ctl; /* 0x00 */
+ u32 tx_mode; /* 0x04 */
+ u32 tx_flow; /* 0x08 */
+ u32 tx_ctl0; /* 0x0c */
+ u32 tx_ctl1; /* 0x10 */
+ u32 tx_ins; /* 0x14 */
+ u32 tx_pl0; /* 0x18 */
+ u32 tx_pl1; /* 0x1c */
+ u32 tx_sta; /* 0x20 */
+ u32 tx_io_data; /* 0x24 */
+ u32 tx_io_data1;/* 0x28 */
+ u32 tx_tsvl0; /* 0x2c */
+ u32 tx_tsvh0; /* 0x30 */
+ u32 tx_tsvl1; /* 0x34 */
+ u32 tx_tsvh1; /* 0x38 */
+ u32 rx_ctl; /* 0x3c */
+ u32 rx_hash0; /* 0x40 */
+ u32 rx_hash1; /* 0x44 */
+ u32 rx_sta; /* 0x48 */
+ u32 rx_io_data; /* 0x4c */
+ u32 rx_fbc; /* 0x50 */
+ u32 int_ctl; /* 0x54 */
+ u32 int_sta; /* 0x58 */
+ u32 mac_ctl0; /* 0x5c */
+ u32 mac_ctl1; /* 0x60 */
+ u32 mac_ipgt; /* 0x64 */
+ u32 mac_ipgr; /* 0x68 */
+ u32 mac_clrt; /* 0x6c */
+ u32 mac_maxf; /* 0x70 */
+ u32 mac_supp; /* 0x74 */
+ u32 mac_test; /* 0x78 */
+ u32 mac_mcfg; /* 0x7c */
+ u32 mac_mcmd; /* 0x80 */
+ u32 mac_madr; /* 0x84 */
+ u32 mac_mwtd; /* 0x88 */
+ u32 mac_mrdd; /* 0x8c */
+ u32 mac_mind; /* 0x90 */
+ u32 mac_ssrr; /* 0x94 */
+ u32 mac_a0; /* 0x98 */
+ u32 mac_a1; /* 0x9c */
+};
+
+/* SRAMC register */
+struct sunxi_sramc_regs {
+ u32 ctrl0;
+ u32 ctrl1;
+};
+
+/* 0: Disable 1: Aborted frame enable(default) */
+#define EMAC_TX_AB_M (0x1 << 0)
+/* 0: CPU 1: DMA(default) */
+#define EMAC_TX_TM (0x1 << 1)
+
+#define EMAC_TX_SETUP (0)
+
+/* 0: DRQ asserted 1: DRQ automatically(default) */
+#define EMAC_RX_DRQ_MODE (0x1 << 1)
+/* 0: CPU 1: DMA(default) */
+#define EMAC_RX_TM (0x1 << 2)
+/* 0: Normal(default) 1: Pass all Frames */
+#define EMAC_RX_PA (0x1 << 4)
+/* 0: Normal(default) 1: Pass Control Frames */
+#define EMAC_RX_PCF (0x1 << 5)
+/* 0: Normal(default) 1: Pass Frames with CRC Error */
+#define EMAC_RX_PCRCE (0x1 << 6)
+/* 0: Normal(default) 1: Pass Frames with Length Error */
+#define EMAC_RX_PLE (0x1 << 7)
+/* 0: Normal 1: Pass Frames length out of range(default) */
+#define EMAC_RX_POR (0x1 << 8)
+/* 0: Not accept 1: Accept unicast Packets(default) */
+#define EMAC_RX_UCAD (0x1 << 16)
+/* 0: Normal(default) 1: DA Filtering */
+#define EMAC_RX_DAF (0x1 << 17)
+/* 0: Not accept 1: Accept multicast Packets(default) */
+#define EMAC_RX_MCO (0x1 << 20)
+/* 0: Disable(default) 1: Enable Hash filter */
+#define EMAC_RX_MHF (0x1 << 21)
+/* 0: Not accept 1: Accept Broadcast Packets(default) */
+#define EMAC_RX_BCO (0x1 << 22)
+/* 0: Disable(default) 1: Enable SA Filtering */
+#define EMAC_RX_SAF (0x1 << 24)
+/* 0: Normal(default) 1: Inverse Filtering */
+#define EMAC_RX_SAIF (0x1 << 25)
+
+#define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \
+ EMAC_RX_MCO | EMAC_RX_BCO)
+
+/* 0: Disable 1: Enable Receive Flow Control(default) */
+#define EMAC_MAC_CTL0_RFC (0x1 << 2)
+/* 0: Disable 1: Enable Transmit Flow Control(default) */
+#define EMAC_MAC_CTL0_TFC (0x1 << 3)
+
+#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)
+
+/* 0: Disable 1: Enable MAC Frame Length Checking(default) */
+#define EMAC_MAC_CTL1_FLC (0x1 << 1)
+/* 0: Disable(default) 1: Enable Huge Frame */
+#define EMAC_MAC_CTL1_HF (0x1 << 2)
+/* 0: Disable(default) 1: Enable MAC Delayed CRC */
+#define EMAC_MAC_CTL1_DCRC (0x1 << 3)
+/* 0: Disable 1: Enable MAC CRC(default) */
+#define EMAC_MAC_CTL1_CRC (0x1 << 4)
+/* 0: Disable 1: Enable MAC PAD Short frames(default) */
+#define EMAC_MAC_CTL1_PC (0x1 << 5)
+/* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */
+#define EMAC_MAC_CTL1_VC (0x1 << 6)
+/* 0: Disable(default) 1: Enable MAC auto detect Short frames */
+#define EMAC_MAC_CTL1_ADP (0x1 << 7)
+/* 0: Disable(default) 1: Enable */
+#define EMAC_MAC_CTL1_PRE (0x1 << 8)
+/* 0: Disable(default) 1: Enable */
+#define EMAC_MAC_CTL1_LPE (0x1 << 9)
+/* 0: Disable(default) 1: Enable no back off */
+#define EMAC_MAC_CTL1_NB (0x1 << 12)
+/* 0: Disable(default) 1: Enable */
+#define EMAC_MAC_CTL1_BNB (0x1 << 13)
+/* 0: Disable(default) 1: Enable */
+#define EMAC_MAC_CTL1_ED (0x1 << 14)
+
+#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
+ EMAC_MAC_CTL1_PC)
+
+#define EMAC_MAC_IPGT 0x15
+
+#define EMAC_MAC_NBTB_IPG1 0xc
+#define EMAC_MAC_NBTB_IPG2 0x12
+
+#define EMAC_MAC_CW 0x37
+#define EMAC_MAC_RM 0xf
+
+#define EMAC_MAC_MFL 0x0600
+
+/* Receive status */
+#define EMAC_CRCERR (0x1 << 4)
+#define EMAC_LENERR (0x3 << 5)
+
+#define DMA_CPU_TRRESHOLD 2000
+
+struct emac_eth_dev {
+ u32 speed;
+ u32 duplex;
+ u32 phy_configured;
+ int link_printed;
+};
+
+struct emac_rxhdr {
+ s16 rx_len;
+ u16 rx_status;
+};
+
+static void emac_inblk_32bit(void *reg, void *data, int count)
+{
+ int cnt = (count + 3) >> 2;
+
+ if (cnt) {
+ u32 *buf = data;
+
+ do {
+ u32 x = readl(reg);
+ *buf++ = x;
+ } while (--cnt);
+ }
+}
+
+static void emac_outblk_32bit(void *reg, void *data, int count)
+{
+ int cnt = (count + 3) >> 2;
+
+ if (cnt) {
+ const u32 *buf = data;
+
+ do {
+ writel(*buf++, reg);
+ } while (--cnt);
+ }
+}
+
+/* Read a word from phyxcer */
+static int emac_phy_read(const char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value)
+{
+ struct eth_device *dev = eth_get_dev_by_name(devname);
+ struct emac_regs *regs = (struct emac_regs *)dev->iobase;
+
+ /* issue the phy address and reg */
+ writel(addr << 8 | reg, ®s->mac_madr);
+
+ /* pull up the phy io line */
+ writel(0x1, ®s->mac_mcmd);
+
+ /* Wait read complete */
+ mdelay(1);
+
+ /* push down the phy io line */
+ writel(0x0, ®s->mac_mcmd);
+
+ /* and write data */
+ *value = readl(®s->mac_mrdd);
+
+ return 0;
+}
+
+/* Write a word to phyxcer */
+static int emac_phy_write(const char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
+{
+ struct eth_device *dev = eth_get_dev_by_name(devname);
+ struct emac_regs *regs = (struct emac_regs *)dev->iobase;
+
+ /* issue the phy address and reg */
+ writel(addr << 8 | reg, ®s->mac_madr);
+
+ /* pull up the phy io line */
+ writel(0x1, ®s->mac_mcmd);
+
+ /* Wait write complete */
+ mdelay(1);
+
+ /* push down the phy io line */
+ writel(0x0, ®s->mac_mcmd);
+
+ /* and write data */
+ writel(value, ®s->mac_mwtd);
+
+ return 0;
+}
+
+static void emac_setup(struct eth_device *dev)
+{
+ struct emac_regs *regs = (struct emac_regs *)dev->iobase;
+ u32 reg_val;
+ u16 phy_val;
+ u32 duplex_flag;
+
+ /* Set up TX */
+ writel(EMAC_TX_SETUP, ®s->tx_mode);
+
+ /* Set up RX */
+ writel(EMAC_RX_SETUP, ®s->rx_ctl);
+
+ /* Set MAC */
+ /* Set MAC CTL0 */
+ writel(EMAC_MAC_CTL0_SETUP, ®s->mac_ctl0);
+
+ /* Set MAC CTL1 */
+ emac_phy_read(dev->name, 1, 0, &phy_val);
+ debug("PHY SETUP, reg 0 value: %x\n", phy_val);
+ duplex_flag = !!(phy_val & (1 << 8));
+
+ reg_val = 0;
+ if (duplex_flag)
+ reg_val = (0x1 << 0);
+ writel(EMAC_MAC_CTL1_SETUP | reg_val, ®s->mac_ctl1);
+
+ /* Set up IPGT */
+ writel(EMAC_MAC_IPGT, ®s->mac_ipgt);
+
+ /* Set up IPGR */
+ writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), ®s->mac_ipgr);
+
+ /* Set up Collison window */
+ writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), ®s->mac_clrt);
+
+ /* Set up Max Frame Length */
+ writel(EMAC_MAC_MFL, ®s->mac_maxf);
+}
+
+static void emac_reset(struct eth_device *dev)
+{
+ struct emac_regs *regs = (struct emac_regs *)dev->iobase;
+
+ debug("resetting device\n");
+
+ /* RESET device */
+ writel(0, ®s->ctl);
+ udelay(200);
+
+ writel(1, ®s->ctl);
+ udelay(200);
+}
+
+static int sunxi_emac_eth_init(struct eth_device *dev, bd_t *bd)
+{
+ struct emac_regs *regs = (struct emac_regs *)dev->iobase;
+ struct emac_eth_dev *priv = dev->priv;
+ u16 phy_reg;
+
+ /* Init EMAC */
+
+ /* Flush RX FIFO */
+ setbits_le32(®s->rx_ctl, 0x8);
+ udelay(1);
+
+ /* Init MAC */
+
+ /* Soft reset MAC */
+ clrbits_le32(®s->mac_ctl0, 0x1 << 15);
+
+ /* Clear RX counter */
+ writel(0x0, ®s->rx_fbc);
+ udelay(1);
+
+ /* Set up EMAC */
+ emac_setup(dev);
+
+ writel(dev->enetaddr[0] << 16 | dev->enetaddr[1] << 8 |
+ dev->enetaddr[2], ®s->mac_a1);
+ writel(dev->enetaddr[3] << 16 | dev->enetaddr[4] << 8 |
+ dev->enetaddr[5], ®s->mac_a0);
+
+ mdelay(1);
+
+ emac_reset(dev);
+
+ /* PHY POWER UP */
+ emac_phy_read(dev->name, 1, 0, &phy_reg);
+ emac_phy_write(dev->name, 1, 0, phy_reg & (~(0x1 << 11)));
+ mdelay(1);
+
+ emac_phy_read(dev->name, 1, 0, &phy_reg);
+
+ priv->speed = miiphy_speed(dev->name, 0);
+ priv->duplex = miiphy_duplex(dev->name, 0);
+
+ /* Print link status only once */
+ if (!priv->link_printed) {
+ printf("ENET Speed is %d Mbps - %s duplex connection\n",
+ priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL");
+ priv->link_printed = 1;
+ }
+
+ /* Set EMAC SPEED depend on PHY */
+ clrsetbits_le32(®s->mac_supp, 1 << 8,
+ ((phy_reg & (0x1 << 13)) >> 13) << 8);
+
+ /* Set duplex depend on phy */
+ clrsetbits_le32(®s->mac_ctl1, 1 << 0,
+ ((phy_reg & (0x1 << 8)) >> 8) << 0);
+
+ /* Enable RX/TX */
+ setbits_le32(®s->ctl, 0x7);
+
+ return 0;
+}
+
+static void sunxi_emac_eth_halt(struct eth_device *dev)
+{
+ /* Nothing to do here */
+}
+
+static int sunxi_emac_eth_recv(struct eth_device *dev)
+{
+ struct emac_regs *regs = (struct emac_regs *)dev->iobase;
+ struct emac_rxhdr rxhdr;
+ u32 rxcount;
+ u32 reg_val;
+ int rx_len;
+ int rx_status;
+ int good_packet;
+
+ /* Check packet ready or not */
+
+ /* Race warning: The first packet might arrive with
+ * the interrupts disabled, but the second will fix
+ */
+ rxcount = readl(®s->rx_fbc);
+ if (!rxcount) {
+ /* Had one stuck? */
+ rxcount = readl(®s->rx_fbc);
+ if (!rxcount)
+ return 0;
+ }
+
+ reg_val = readl(®s->rx_io_data);
+ if (reg_val != 0x0143414d) {
+ /* Disable RX */
+ clrbits_le32(®s->ctl, 0x1 << 2);
+
+ /* Flush RX FIFO */
+ setbits_le32(®s->rx_ctl, 0x1 << 3);
+ while (readl(®s->rx_ctl) & (0x1 << 3))
+ ;
+
+ /* Enable RX */
+ setbits_le32(®s->ctl, 0x1 << 2);
+
+ return 0;
+ }
+
+ /* A packet ready now
+ * Get status/length
+ */
+ good_packet = 1;
+
+ emac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr));
+
+ rx_len = rxhdr.rx_len;
+ rx_status = rxhdr.rx_status;
+
+ /* Packet Status check */
+ if (rx_len < 0x40) {
+ good_packet = 0;
+ debug("RX: Bad Packet (runt)\n");
+ }
+
+ /* rx_status is identical to RSR register. */
+ if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) {
+ good_packet = 0;
+ if (rx_status & EMAC_CRCERR)
+ printf("crc error\n");
+ if (rx_status & EMAC_LENERR)
+ printf("length error\n");
+ }
+
+ /* Move data from EMAC */
+ if (good_packet) {
+ if (rx_len > DMA_CPU_TRRESHOLD) {
+ printf("Received packet is too big (len=%d)\n", rx_len);
+ } else {
+ emac_inblk_32bit((void *)®s->rx_io_data,
+ NetRxPackets[0], rx_len);
+
+ /* Pass to upper layer */
+ NetReceive(NetRxPackets[0], rx_len);
+ return rx_len;
+ }
+ }
+
+ return 0;
+}
+
+static int sunxi_emac_eth_send(struct eth_device *dev, void *packet, int len)
+{
+ struct emac_regs *regs = (struct emac_regs *)dev->iobase;
+
+ /* Select channel 0 */
+ writel(0, ®s->tx_ins);
+
+ /* Write packet */
+ emac_outblk_32bit((void *)®s->tx_io_data, packet, len);
+
+ /* Set TX len */
+ writel(len, ®s->tx_pl0);
+
+ /* Start translate from fifo to phy */
+ setbits_le32(®s->tx_ctl0, 1);
+
+ return 0;
+}
+
+int sunxi_emac_initialize(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_sramc_regs *sram =
+ (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
+ struct emac_regs *regs =
+ (struct emac_regs *)SUNXI_EMAC_BASE;
+ struct eth_device *dev;
+ struct emac_eth_dev *priv;
+ int pin;
+
+ dev = malloc(sizeof(*dev));
+ if (dev == NULL)
+ return -ENOMEM;
+
+ priv = (struct emac_eth_dev *)malloc(sizeof(struct emac_eth_dev));
+ if (!priv) {
+ free(dev);
+ return -ENOMEM;
+ }
+
+ memset(dev, 0, sizeof(*dev));
+ memset(priv, 0, sizeof(struct emac_eth_dev));
+
+ /* Map SRAM to EMAC */
+ setbits_le32(&sram->ctrl1, 0x5 << 2);
+
+ /* Configure pin mux settings for MII Ethernet */
+ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPA0_EMAC);
+
+ /* Set up clock gating */
+ setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);
+
+ /* Set MII clock */
+ clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2);
+
+ dev->iobase = (int)regs;
+ dev->priv = priv;
+ dev->init = sunxi_emac_eth_init;
+ dev->halt = sunxi_emac_eth_halt;
+ dev->send = sunxi_emac_eth_send;
+ dev->recv = sunxi_emac_eth_recv;
+ strcpy(dev->name, "emac");
+
+ eth_register(dev);
+
+ miiphy_register(dev->name, emac_phy_read, emac_phy_write);
+
+ return 0;
+}
diff --git a/drivers/net/sunxi_wemac.c b/drivers/net/sunxi_wemac.c
deleted file mode 100644
index 699a381..0000000
--- a/drivers/net/sunxi_wemac.c
+++ /dev/null
@@ -1,525 +0,0 @@
-/*
- * sunxi_wemac.c -- Allwinner A10 ethernet driver
- *
- * (C) Copyright 2012, Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <miiphy.h>
-#include <linux/err.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-
-/* EMAC register */
-struct wemac_regs {
- u32 ctl; /* 0x00 */
- u32 tx_mode; /* 0x04 */
- u32 tx_flow; /* 0x08 */
- u32 tx_ctl0; /* 0x0c */
- u32 tx_ctl1; /* 0x10 */
- u32 tx_ins; /* 0x14 */
- u32 tx_pl0; /* 0x18 */
- u32 tx_pl1; /* 0x1c */
- u32 tx_sta; /* 0x20 */
- u32 tx_io_data; /* 0x24 */
- u32 tx_io_data1; /* 0x28 */
- u32 tx_tsvl0; /* 0x2c */
- u32 tx_tsvh0; /* 0x30 */
- u32 tx_tsvl1; /* 0x34 */
- u32 tx_tsvh1; /* 0x38 */
- u32 rx_ctl; /* 0x3c */
- u32 rx_hash0; /* 0x40 */
- u32 rx_hash1; /* 0x44 */
- u32 rx_sta; /* 0x48 */
- u32 rx_io_data; /* 0x4c */
- u32 rx_fbc; /* 0x50 */
- u32 int_ctl; /* 0x54 */
- u32 int_sta; /* 0x58 */
- u32 mac_ctl0; /* 0x5c */
- u32 mac_ctl1; /* 0x60 */
- u32 mac_ipgt; /* 0x64 */
- u32 mac_ipgr; /* 0x68 */
- u32 mac_clrt; /* 0x6c */
- u32 mac_maxf; /* 0x70 */
- u32 mac_supp; /* 0x74 */
- u32 mac_test; /* 0x78 */
- u32 mac_mcfg; /* 0x7c */
- u32 mac_mcmd; /* 0x80 */
- u32 mac_madr; /* 0x84 */
- u32 mac_mwtd; /* 0x88 */
- u32 mac_mrdd; /* 0x8c */
- u32 mac_mind; /* 0x90 */
- u32 mac_ssrr; /* 0x94 */
- u32 mac_a0; /* 0x98 */
- u32 mac_a1; /* 0x9c */
-};
-
-/* SRAMC register */
-struct sunxi_sramc_regs {
- u32 ctrl0;
- u32 ctrl1;
-};
-
-/* 0: Disable 1: Aborted frame enable(default) */
-#define EMAC_TX_AB_M (0x1 << 0)
-/* 0: CPU 1: DMA(default) */
-#define EMAC_TX_TM (0x1 << 1)
-
-#define EMAC_TX_SETUP (0)
-
-/* 0: DRQ asserted 1: DRQ automatically(default) */
-#define EMAC_RX_DRQ_MODE (0x1 << 1)
-/* 0: CPU 1: DMA(default) */
-#define EMAC_RX_TM (0x1 << 2)
-/* 0: Normal(default) 1: Pass all Frames */
-#define EMAC_RX_PA (0x1 << 4)
-/* 0: Normal(default) 1: Pass Control Frames */
-#define EMAC_RX_PCF (0x1 << 5)
-/* 0: Normal(default) 1: Pass Frames with CRC Error */
-#define EMAC_RX_PCRCE (0x1 << 6)
-/* 0: Normal(default) 1: Pass Frames with Length Error */
-#define EMAC_RX_PLE (0x1 << 7)
-/* 0: Normal 1: Pass Frames length out of range(default) */
-#define EMAC_RX_POR (0x1 << 8)
-/* 0: Not accept 1: Accept unicast Packets(default) */
-#define EMAC_RX_UCAD (0x1 << 16)
-/* 0: Normal(default) 1: DA Filtering */
-#define EMAC_RX_DAF (0x1 << 17)
-/* 0: Not accept 1: Accept multicast Packets(default) */
-#define EMAC_RX_MCO (0x1 << 20)
-/* 0: Disable(default) 1: Enable Hash filter */
-#define EMAC_RX_MHF (0x1 << 21)
-/* 0: Not accept 1: Accept Broadcast Packets(default) */
-#define EMAC_RX_BCO (0x1 << 22)
-/* 0: Disable(default) 1: Enable SA Filtering */
-#define EMAC_RX_SAF (0x1 << 24)
-/* 0: Normal(default) 1: Inverse Filtering */
-#define EMAC_RX_SAIF (0x1 << 25)
-
-#define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \
- EMAC_RX_MCO | EMAC_RX_BCO)
-
-/* 0: Disable 1: Enable Receive Flow Control(default) */
-#define EMAC_MAC_CTL0_RFC (0x1 << 2)
-/* 0: Disable 1: Enable Transmit Flow Control(default) */
-#define EMAC_MAC_CTL0_TFC (0x1 << 3)
-
-#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)
-
-/* 0: Disable 1: Enable MAC Frame Length Checking(default) */
-#define EMAC_MAC_CTL1_FLC (0x1 << 1)
-/* 0: Disable(default) 1: Enable Huge Frame */
-#define EMAC_MAC_CTL1_HF (0x1 << 2)
-/* 0: Disable(default) 1: Enable MAC Delayed CRC */
-#define EMAC_MAC_CTL1_DCRC (0x1 << 3)
-/* 0: Disable 1: Enable MAC CRC(default) */
-#define EMAC_MAC_CTL1_CRC (0x1 << 4)
-/* 0: Disable 1: Enable MAC PAD Short frames(default) */
-#define EMAC_MAC_CTL1_PC (0x1 << 5)
-/* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */
-#define EMAC_MAC_CTL1_VC (0x1 << 6)
-/* 0: Disable(default) 1: Enable MAC auto detect Short frames */
-#define EMAC_MAC_CTL1_ADP (0x1 << 7)
-/* 0: Disable(default) 1: Enable */
-#define EMAC_MAC_CTL1_PRE (0x1 << 8)
-/* 0: Disable(default) 1: Enable */
-#define EMAC_MAC_CTL1_LPE (0x1 << 9)
-/* 0: Disable(default) 1: Enable no back off */
-#define EMAC_MAC_CTL1_NB (0x1 << 12)
-/* 0: Disable(default) 1: Enable */
-#define EMAC_MAC_CTL1_BNB (0x1 << 13)
-/* 0: Disable(default) 1: Enable */
-#define EMAC_MAC_CTL1_ED (0x1 << 14)
-
-#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
- EMAC_MAC_CTL1_PC)
-
-#define EMAC_MAC_IPGT 0x15
-
-#define EMAC_MAC_NBTB_IPG1 0xC
-#define EMAC_MAC_NBTB_IPG2 0x12
-
-#define EMAC_MAC_CW 0x37
-#define EMAC_MAC_RM 0xF
-
-#define EMAC_MAC_MFL 0x0600
-
-/* Receive status */
-#define EMAC_CRCERR (1 << 4)
-#define EMAC_LENERR (3 << 5)
-
-#define DMA_CPU_TRRESHOLD 2000
-
-struct wemac_eth_dev {
- u32 speed;
- u32 duplex;
- u32 phy_configured;
- int link_printed;
-};
-
-struct wemac_rxhdr {
- s16 rx_len;
- u16 rx_status;
-};
-
-static void wemac_inblk_32bit(void *reg, void *data, int count)
-{
- int cnt = (count + 3) >> 2;
-
- if (cnt) {
- u32 *buf = data;
-
- do {
- u32 x = readl(reg);
- *buf++ = x;
- } while (--cnt);
- }
-}
-
-static void wemac_outblk_32bit(void *reg, void *data, int count)
-{
- int cnt = (count + 3) >> 2;
-
- if (cnt) {
- const u32 *buf = data;
-
- do {
- writel(*buf++, reg);
- } while (--cnt);
- }
-}
-
-/*
- * Read a word from phyxcer
- */
-static int wemac_phy_read(const char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value)
-{
- struct eth_device *dev = eth_get_dev_by_name(devname);
- struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
-
- /* issue the phy address and reg */
- writel(addr << 8 | reg, ®s->mac_madr);
-
- /* pull up the phy io line */
- writel(0x1, ®s->mac_mcmd);
-
- /* Wait read complete */
- mdelay(1);
-
- /* push down the phy io line */
- writel(0x0, ®s->mac_mcmd);
-
- /* and write data */
- *value = readl(®s->mac_mrdd);
-
- return 0;
-}
-
-/*
- * Write a word to phyxcer
- */
-static int wemac_phy_write(const char *devname, unsigned char addr,
- unsigned char reg, unsigned short value)
-{
- struct eth_device *dev = eth_get_dev_by_name(devname);
- struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
-
- /* issue the phy address and reg */
- writel(addr << 8 | reg, ®s->mac_madr);
-
- /* pull up the phy io line */
- writel(0x1, ®s->mac_mcmd);
-
- /* Wait write complete */
- mdelay(1);
-
- /* push down the phy io line */
- writel(0x0, ®s->mac_mcmd);
-
- /* and write data */
- writel(value, ®s->mac_mwtd);
-
- return 0;
-}
-
-static void emac_setup(struct eth_device *dev)
-{
- struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
- u32 reg_val;
- u16 phy_val;
- u32 duplex_flag;
-
- /* Set up TX */
- writel(EMAC_TX_SETUP, ®s->tx_mode);
-
- /* Set up RX */
- writel(EMAC_RX_SETUP, ®s->rx_ctl);
-
- /* Set MAC */
- /* Set MAC CTL0 */
- writel(EMAC_MAC_CTL0_SETUP, ®s->mac_ctl0);
-
- /* Set MAC CTL1 */
- wemac_phy_read(dev->name, 1, 0, &phy_val);
- debug("PHY SETUP, reg 0 value: %x\n", phy_val);
- duplex_flag = !!(phy_val & (1 << 8));
-
- reg_val = 0;
- if (duplex_flag)
- reg_val = (0x1 << 0);
- writel(EMAC_MAC_CTL1_SETUP | reg_val, ®s->mac_ctl1);
-
- /* Set up IPGT */
- writel(EMAC_MAC_IPGT, ®s->mac_ipgt);
-
- /* Set up IPGR */
- writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), ®s->mac_ipgr);
-
- /* Set up Collison window */
- writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), ®s->mac_clrt);
-
- /* Set up Max Frame Length */
- writel(EMAC_MAC_MFL, ®s->mac_maxf);
-}
-
-static void wemac_reset(struct eth_device *dev)
-{
- struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
-
- debug("resetting device\n");
-
- /* RESET device */
- writel(0, ®s->ctl);
- udelay(200);
-
- writel(1, ®s->ctl);
- udelay(200);
-}
-
-static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd)
-{
- struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
- struct wemac_eth_dev *priv = dev->priv;
- u16 phy_reg;
-
- /* Init EMAC */
-
- /* Flush RX FIFO */
- setbits_le32(®s->rx_ctl, 0x8);
- udelay(1);
-
- /* Init MAC */
-
- /* Soft reset MAC */
- clrbits_le32(®s->mac_ctl0, 1 << 15);
-
- /* Set MII clock */
- clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2);
-
- /* Clear RX counter */
- writel(0x0, ®s->rx_fbc);
- udelay(1);
-
- /* Set up EMAC */
- emac_setup(dev);
-
- writel(dev->enetaddr[0] << 16 | dev->enetaddr[1] << 8 |
- dev->enetaddr[2], ®s->mac_a1);
- writel(dev->enetaddr[3] << 16 | dev->enetaddr[4] << 8 |
- dev->enetaddr[5], ®s->mac_a0);
-
- mdelay(1);
-
- wemac_reset(dev);
-
- /* PHY POWER UP */
- wemac_phy_read(dev->name, 1, 0, &phy_reg);
- wemac_phy_write(dev->name, 1, 0, phy_reg & (~(1 << 11)));
- mdelay(1);
-
- wemac_phy_read(dev->name, 1, 0, &phy_reg);
-
- priv->speed = miiphy_speed(dev->name, 0);
- priv->duplex = miiphy_duplex(dev->name, 0);
-
- /* Print link status only once */
- if (!priv->link_printed) {
- printf("ENET Speed is %d Mbps - %s duplex connection\n",
- priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL");
- priv->link_printed = 1;
- }
-
- /* Set EMAC SPEED depend on PHY */
- clrsetbits_le32(®s->mac_supp, 1 << 8,
- ((phy_reg & (1 << 13)) >> 13) << 8);
-
- /* Set duplex depend on phy */
- clrsetbits_le32(®s->mac_ctl1, 1 << 0,
- ((phy_reg & (1 << 8)) >> 8) << 0);
-
- /* Enable RX/TX */
- setbits_le32(®s->ctl, 0x7);
-
- return 0;
-}
-
-static void sunxi_wemac_eth_halt(struct eth_device *dev)
-{
- /* Nothing to do here */
-}
-
-static int sunxi_wemac_eth_recv(struct eth_device *dev)
-{
- struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
- struct wemac_rxhdr rxhdr;
- u32 rxcount;
- u32 reg_val;
- int rx_len;
- int rx_status;
- int good_packet;
-
- /* Check packet ready or not */
-
- /*
- * Race warning: The first packet might arrive with
- * the interrupts disabled, but the second will fix
- */
- rxcount = readl(®s->rx_fbc);
- if (!rxcount) {
- /* Had one stuck? */
- rxcount = readl(®s->rx_fbc);
- if (!rxcount)
- return 0;
- }
-
- reg_val = readl(®s->rx_io_data);
- if (reg_val != 0x0143414d) {
- /* Disable RX */
- clrbits_le32(®s->ctl, 1 << 2);
-
- /* Flush RX FIFO */
- setbits_le32(®s->rx_ctl, 1 << 3);
- while (readl(®s->rx_ctl) & (1 << 3))
- ;
-
- /* Enable RX */
- setbits_le32(®s->ctl, 1 << 2);
-
- return 0;
- }
-
- /*
- * A packet ready now
- * Get status/length
- */
- good_packet = 1;
-
- wemac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr));
-
- rx_len = rxhdr.rx_len;
- rx_status = rxhdr.rx_status;
-
- /* Packet Status check */
- if (rx_len < 0x40) {
- good_packet = 0;
- debug("RX: Bad Packet (runt)\n");
- }
-
- /* rx_status is identical to RSR register. */
- if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) {
- good_packet = 0;
- if (rx_status & EMAC_CRCERR)
- printf("crc error\n");
- if (rx_status & EMAC_LENERR)
- printf("length error\n");
- }
-
- /* Move data from WEMAC */
- if (good_packet) {
- if (rx_len > DMA_CPU_TRRESHOLD) {
- printf("Received packet is too big (len=%d)\n", rx_len);
- } else {
- wemac_inblk_32bit((void *)®s->rx_io_data,
- NetRxPackets[0], rx_len);
-
- /* Pass to upper layer */
- NetReceive(NetRxPackets[0], rx_len);
- return rx_len;
- }
- }
-
- return 0;
-}
-
-static int sunxi_wemac_eth_send(struct eth_device *dev, void *packet, int len)
-{
- struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
-
- /* Select channel 0 */
- writel(0, ®s->tx_ins);
-
- /* Write packet */
- wemac_outblk_32bit((void *)®s->tx_io_data, packet, len);
-
- /* Set TX len */
- writel(len, ®s->tx_pl0);
-
- /* Start translate from fifo to phy */
- setbits_le32(®s->tx_ctl0, 1);
-
- return 0;
-}
-
-int sunxi_wemac_initialize(void)
-{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- struct sunxi_sramc_regs *sram =
- (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
- struct eth_device *dev;
- struct wemac_eth_dev *priv;
- int pin;
-
- dev = malloc(sizeof(*dev));
- if (dev == NULL)
- return -ENOMEM;
-
- priv = (struct wemac_eth_dev *)malloc(sizeof(struct wemac_eth_dev));
- if (!priv) {
- free(dev);
- return -ENOMEM;
- }
-
- memset(dev, 0, sizeof(*dev));
- memset(priv, 0, sizeof(struct wemac_eth_dev));
-
- /* Map SRAM to EMAC */
- setbits_le32(&sram->ctrl1, 0x5 << 2);
-
- /* Configure pin mux settings for MII Ethernet */
- for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
- sunxi_gpio_set_cfgpin(pin, 2);
-
- /* Set up clock gating */
- setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_EMAC);
-
- dev->iobase = SUNXI_EMAC_BASE;
- dev->priv = priv;
- dev->init = sunxi_wemac_eth_init;
- dev->halt = sunxi_wemac_eth_halt;
- dev->send = sunxi_wemac_eth_send;
- dev->recv = sunxi_wemac_eth_recv;
- strcpy(dev->name, "wemac");
-
- eth_register(dev);
-
- miiphy_register(dev->name, wemac_phy_read, wemac_phy_write);
-
- return 0;
-}
diff --git a/include/netdev.h b/include/netdev.h
index 63481ec..e45dd7a 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -78,8 +78,8 @@ int sh_eth_initialize(bd_t *bis);
int skge_initialize(bd_t *bis);
int smc91111_initialize(u8 dev_num, int base_addr);
int smc911x_initialize(u8 dev_num, int base_addr);
+int sunxi_emac_initialize(bd_t *bis);
int sunxi_gmac_initialize(bd_t *bis);
-int sunxi_wemac_initialize(bd_t *bis);
int tsi108_eth_initialize(bd_t *bis);
int uec_standard_init(bd_t *bis);
int uli526x_initialize(bd_t *bis);
--
1.9.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [U-Boot] [PATCH v2 11/12] sunxi: Add emac glue, enable emac on the cubieboard
2014-06-03 19:41 [U-Boot] [PATCH v2 00/12] sunxi: Bug fixes, sun4i and sun5i support, pmic support and network improvements Hans de Goede
` (9 preceding siblings ...)
2014-06-03 19:42 ` [U-Boot] [PATCH v2 10/12] net: Rename and cleanup sunxi (Allwinner) emac driver Hans de Goede
@ 2014-06-03 19:42 ` Hans de Goede
2014-06-05 18:49 ` Ian Campbell
2014-06-03 19:42 ` [U-Boot] [PATCH v2 12/12] sunxi: Add support for using MII phy-s with the GMAC nic Hans de Goede
11 siblings, 1 reply; 27+ messages in thread
From: Hans de Goede @ 2014-06-03 19:42 UTC (permalink / raw)
To: u-boot
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
arch/arm/cpu/armv7/sunxi/board.c | 8 ++++++++
boards.cfg | 2 +-
include/configs/sunxi-common.h | 5 +++++
3 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 7d86409..024c8c1 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -123,6 +123,14 @@ int cpu_eth_init(bd_t *bis)
{
int rc;
+#ifdef CONFIG_SUNXI_EMAC
+ rc = sunxi_emac_initialize(bis);
+ if (rc < 0) {
+ printf("sunxi: failed to initialize emac\n");
+ return rc;
+ }
+#endif
+
#ifdef CONFIG_SUNXI_GMAC
rc = sunxi_gmac_initialize(bis);
if (rc < 0) {
diff --git a/boards.cfg b/boards.cfg
index 827095d..18a8400 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -382,7 +382,7 @@ Active arm armv7 s5pc1xx samsung goni
Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
Active arm armv7 sunxi - sunxi A13-OLinuXinoM sun5i:A13_OLINUXINOM,SPL,CONS_INDEX=2 Hans de Goede <hdegoede@redhat.com>
-Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,AXP209_POWER Hans de Goede <hdegoede@redhat.com>
+Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,AXP209_POWER,SUNXI_EMAC Hans de Goede <hdegoede@redhat.com>
Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,AXP209_POWER,SUNXI_GMAC,RGMII Ian Campbell <ijc@hellion.org.uk>:Hans de Goede <hdegoede@redhat.com>
Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII Ian Campbell <ijc@hellion.org.uk>:Hans de Goede <hdegoede@redhat.com>
Active arm armv7 sunxi - sunxi r7-tv-dongle sun5i:R7DONGLE,SPL,AXP152_POWER Hans de Goede <hdegoede@redhat.com>
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index b76227e..a9d104a 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -179,6 +179,11 @@
#define CONFIG_CONS_INDEX 1 /* UART0 */
#endif
+/* Ethernet support */
+#ifdef CONFIG_SUNXI_EMAC
+#define CONFIG_MII /* MII PHY management */
+#endif
+
#ifdef CONFIG_SUNXI_GMAC
#define CONFIG_DESIGNWARE_ETH /* GMAC can use designware driver */
#define CONFIG_DW_AUTONEG
--
1.9.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [U-Boot] [PATCH v2 12/12] sunxi: Add support for using MII phy-s with the GMAC nic
2014-06-03 19:41 [U-Boot] [PATCH v2 00/12] sunxi: Bug fixes, sun4i and sun5i support, pmic support and network improvements Hans de Goede
` (10 preceding siblings ...)
2014-06-03 19:42 ` [U-Boot] [PATCH v2 11/12] sunxi: Add emac glue, enable emac on the cubieboard Hans de Goede
@ 2014-06-03 19:42 ` Hans de Goede
2014-06-05 18:50 ` Ian Campbell
11 siblings, 1 reply; 27+ messages in thread
From: Hans de Goede @ 2014-06-03 19:42 UTC (permalink / raw)
To: u-boot
From: Chen-Yu Tsai <wens@csie.org>
Many A20 boards (ie Cubieboard2, A20-OLinuXino_MICRO) use an 100 Mbit MII
phy together with the GMAC nic found in the A20 SoC, add support for this
(this will get used when we add these boards in a later patch).
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
board/sunxi/gmac.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index e48328d..e7ff952 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -16,17 +16,28 @@ int sunxi_gmac_initialize(bd_t *bis)
setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
/* Set MII clock */
+#ifdef CONFIG_RGMII
setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
CCM_GMAC_CTRL_GPIT_RGMII);
+#else
+ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
+ CCM_GMAC_CTRL_GPIT_MII);
+#endif
/* Configure pin mux settings for GMAC */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
+#ifdef CONFIG_RGMII
/* skip unused pins in RGMII mode */
if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
continue;
+#endif
sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
+#ifdef CONFIG_RGMII
return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
+#else
+ return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
+#endif
}
--
1.9.0
^ permalink raw reply related [flat|nested] 27+ messages in thread