From mboxrd@z Thu Jan  1 00:00:00 1970
From: York Sun <yorksun@freescale.com>
Date: Wed, 11 Jun 2014 07:55:46 -0700
Subject: [U-Boot] [Patch v4 3/5] ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC
In-Reply-To: <64C55F0C-4013-4876-B9CD-EA155488D2B6@phytium.com.cn>
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	<64C55F0C-4013-4876-B9CD-EA155488D2B6@phytium.com.cn>
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On 06/11/2014 07:05 AM, fenghua at phytium.com.cn wrote:
> 
> Dear York,
>      My mailing list disabled a few days. Maybe I missed something important.
> 
>> /*
>>  * Performs a clean & invalidation of the entire data cache at all levels
>>  */
>> void flush_dcache_all(void)
>> {
>> 	__asm_flush_dcache_all();
>> +	flush_l3_cache();
>> }
>>
> 
> I thought the L3 cache is not included in the cache hierarchy.
> So, how about define it as external cache operations named with outer_cache_* just like armv7 did?
> 


I have it declared as a weak function. If you think the name needs to change, I
can do so.

York