From mboxrd@z Thu Jan  1 00:00:00 1970
From: York Sun <yorksun@freescale.com>
Date: Wed, 11 Jun 2014 14:31:40 -0700
Subject: [U-Boot] [PATCH][v3] powerpc/t4qds: Add alternate serdes
 protocols to align with A-007186
In-Reply-To: <1400208753-3021-1-git-send-email-shh.xie@gmail.com>
References: <1400208753-3021-1-git-send-email-shh.xie@gmail.com>
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On 05/15/2014 07:52 PM, shh.xie at gmail.com wrote:
> From: Shaohui Xie <Shaohui.Xie@freescale.com>
> 
> A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to
> increase and cause the PLL to unlock when the temperature delta from the
> time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V
> (or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC
> VCO. Only the protocols using Ring VCOs are impacted.
> 
> Workaround:
> For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need
> to use alternate serdes protocols. The alternate option has the same
> functionality as the original option; the only difference being LC VCO
> rather than Ring VCO.
> 
> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
> ---
> changes for V3:
> update t4_rcw.cfg.
> 
> changes for V2:
> refined commit message.
> 


Applied to u-boot-mpc85xx. Sorry for the late notice.

York