From: York Sun <yorksun@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3] powerpc/t4rdb: Add alternate serdes protocols to align with A-007186
Date: Wed, 11 Jun 2014 14:32:25 -0700 [thread overview]
Message-ID: <5398CAE9.1010600@freescale.com> (raw)
In-Reply-To: <1400564068-19485-1-git-send-email-Chunhe.Lan@freescale.com>
On 05/19/2014 10:34 PM, Chunhe Lan wrote:
> A-007186: SerDes PLL is calibrated at reset. It is possible
> for jitter to increase and cause the PLL to unlock when the
> temperature delta from the time the PLL is calibrated exceeds
> +56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using
> XnVDD of 1.5 V). No issues are seen with LC VCO. The protocols
> only using Ring VCOs are impacted.
>
> Workaround:
> For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring
> VCO, this need to use alternate serdes protocols. Alternate
> option has the same functionality as the original option; the
> only difference being LC VCO rather than Ring VCO.
>
> Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
> ---
Applied to u-boot-mpc85xx. Sorry for the late notice.
York
prev parent reply other threads:[~2014-06-11 21:32 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-20 5:34 [U-Boot] [PATCH v3] powerpc/t4rdb: Add alternate serdes protocols to align with A-007186 Chunhe Lan
2014-06-11 21:32 ` York Sun [this message]
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