[U-Boot] Driver Model and DTS Parsing

[Stephen Warren <swarren@wwwdotorg.org>]

On 06/11/2014 10:55 PM, Simon Glass wrote:
...
> Tegra doesn't have much in the device tree for GPIOs - it seems to be
> all hard-coded in the software. So I ended up with the code you saw
> which just iterates over a known number of banks, creating a device
> for each.

That still sounds wrong. Tegra HW has a single GPIO controller that
exposes a bunch of GPIOs. It isn't logically divided into banks or any
other construct that is multi-level  Although the naming of the
individual GPIOs does call something a bank, that's just a name of a
register, not separate HW blocks. It's just going to be confusing to
users if the U-Boot representation doesn't match what the HW actually has.

There's zero extra indirection caused by SW correctly describing the HW
as a single bank. I have absolutely no idea what you mean my extra
indirection here; any time there is a driver for a GPIO, you call a
function to set a GPIO. That doesn't change based on whether there are
32 or 1 GPIO controller drivers.  The only difference is how many
drivers you have to search through to find the right one. For Tegra at
least, I'm arguing for 1 driver to match the 1 HW module.

DT is supposed to represent the differences between boards more than the
differences between SoCs. Anything that the driver can reasonably derive
from the compatible value shouldn't be represented in the DT. That's why
the Tegra GPIO DT node just has a compatible value, register address,
and list of interrupts. Nothing more is required. If anything else were
put in DT, you'd end up just wasting time parsing from DT static data
that could just be in the driver.