From mboxrd@z Thu Jan  1 00:00:00 1970
From: York Sun <yorksun@freescale.com>
Date: Fri, 13 Jun 2014 12:41:44 -0700
Subject: [U-Boot] [Patch v4 2/5] ARMv8: Adjust MMU setup
In-Reply-To: <20140610091540.GE17398@leverpostej>
References: <538F48F2.3080408@freescale.com>
	<20140605100926.GA6430@leverpostej>
	<539087A5.4090803@freescale.com>
	<20140605174156.GG31564@leverpostej>
	<5390B82F.5040601@freescale.com>
	<20140606123312.GB18918@leverpostej>
	<5391D639.4080700@freescale.com>
	<20140606173243.GC18918@leverpostej>
	<539221DC.2020107@freescale.com> <53923D3F.3070004@freescale.com>
	<20140610091540.GE17398@leverpostej>
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On 06/10/2014 02:15 AM, Mark Rutland wrote:
> Hi,
> 
> Apologies for the delay in replying.
> 
> On Fri, Jun 06, 2014 at 11:14:23PM +0100, York Sun wrote:
>> On 06/06/2014 01:17 PM, York Sun wrote:
>>> On 06/06/2014 10:32 AM, Mark Rutland wrote:
>>>>>> How is TCR_EL2.SH0 (or TCR_EL1.SH*) configured?
>>>>>>
>>>>>> You'll only need to flush the cache if they're configured non shareable.
>>>>>
>>>>> It is configured as non shareable.
>>>>
>>>> Is there any reason not to configure them as inner shareable? That way
>>>> the MMU will look in the D-cache, and you won't have to spend time
>>>> flushing them.
>>>>
>>>
>>> Mark,
>>>
>>> I appreciate the reminder. I tried on our emulator. With inner share set for TCR
>>> SH0 bits, u-boot works with the flushing, but doesn't work without flushing. It
>>> went to exception.
>>>
>>> Can you share more information about the inner share? I need to follow up with
>>> our designer to confirm.
>>>
>>
>> A second thought, do I need to set the first MMU table so DDR is inner shareable?
> 
> I assume you mean configuring MAIR_ELx such that the mapping covering
> DDR is cacheable for the inner shareable domain? If so, yes.
> 

Mark,

I tried both inner share and outer. It doesn't work without flushing the cache.
I will keep this part of code until I learn otherwise.

York