From mboxrd@z Thu Jan  1 00:00:00 1970
From: Eric Nelson <eric.nelson@boundarydevices.com>
Date: Tue, 17 Jun 2014 11:59:28 -0700
Subject: [U-Boot] [PATCH 2/4] mx6sx: Add pin definitions
In-Reply-To: <53A0618A.5020703@denx.de>
References: <1402777782-15542-1-git-send-email-festevam@gmail.com>	<1402777782-15542-2-git-send-email-festevam@gmail.com>
	<53A0618A.5020703@denx.de>
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Hi Stefano,

On 06/17/2014 08:40 AM, Stefano Babic wrote:
> Hi Fabio,
> 
> On 14/06/2014 22:29, Fabio Estevam wrote:
>> From: Fabio Estevam <fabio.estevam@freescale.com>
>>
>> Add the pin definitions for mx6sx.
>>
> 
> A base question. There was a lot of work to try to abstract the pin
> definitions for the i.MX6 SOCs. For QUAD and DUAL, the pins are defined
> with the MX6_PAD_DECL macro. It works differently according to the
> selected CPU. If more as one CPU is supported in the same image, the
> check is done at runtime.
> 
> Previously, we had IOMUX_PAD, I know. Is there any special reason we
> cannot use MX6_PAD_DECL even for this new SOC ? I will not want to go
> back ignoring a lot of work that was done to merge the SOCs together.
> 

The rationale for the MX6_PAD_DECL came from the fact that the
i.MX6DQ and i.MX6DLS cpu variants had different address schemes,
but were pin-compatible.

The i.MX6SL (and i.MX6SX) are not, so any board supporting these
processors only supports that processor.

Regards,


Eric