[U-Boot] [PATCH v3 0/5] Fix SPI read and Enable required configs for Exynos5

[U-Boot] [PATCH v3 0/5] Fix SPI read and Enable required configs for Exynos5

[Akshay Saraswat]

This patch set intends to -
1. Fix SPI flash reading.
2. Enable saving environment at the end of flash.
3. Increase SPL size.
4. Enable USB booting for all Exynos5 Socs.

Changes since v2:
	- Added "Acked-by" & "Tested-by".
	- Changed assignment for *rxp in 1/5.
Changes since v1:
	- Added check for step in 1/5.
	- Added new config for SPI flash size in 2/5.
	- Made spl footprint 30 KB instead of 32 in 3/5.
	- Added "Acked-by" in 4/5.
	- Introduced new patch 5/5.

Akshay Saraswat (4):
  Exynos: SPI: Fix reading data from SPI flash
  Exynos5: Config: Place environment at the end of SPI flash
  Exynos5: Config: Increase SPL footprint for Exynos5420
  Exynos5: Config: Enable USB boot mode for all Exynos5 SoCs

Michael Pratt (1):
  Exynos: Split 5250 and 5420 memory bank configuration

 drivers/spi/exynos_spi.c        |  5 +++++
 include/configs/exynos5-dt.h    | 15 ++++++++++-----
 include/configs/exynos5250-dt.h | 13 +++++++------
 include/configs/exynos5420.h    |  6 ++++++
 4 files changed, 28 insertions(+), 11 deletions(-)

-- 
1.7.12.4

[U-Boot] [PATCH v3 1/5] Exynos: SPI: Fix reading data from SPI flash

[Akshay Saraswat]

SPI recieve and transfer code in exynos_spi driver has a logical bug.
We read data in a variable which can hold an integer. Then we assign
this integer 32 bit value to another variable which has data type uchar.
Latter represents a unit of our recieve buffer. Everytime when we write
a value to our recieve buffer we step ahead by 4 units when actually we
wrote to one unit. This results in the loss of 3 bytes out of every 4
bytes recieved. This patch intends to fix this bug.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
---
Changes since v2:
	- Added "Acked-by" & "Tested-by".
	- Changed assignment for *rxp.
Changes since v1:
	- Added check for step.

 drivers/spi/exynos_spi.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
index 4d5def2..9bb6924 100644
--- a/drivers/spi/exynos_spi.c
+++ b/drivers/spi/exynos_spi.c
@@ -302,7 +302,10 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
 					}
 				} else {
 					if (rxp || stopping) {
-						*rxp = temp;
+						if (step == 4)
+							*(uint32_t *)rxp = temp;
+						else
+							*rxp = temp;
 						rxp += step;
 					}
 					in_bytes -= step;
-- 
1.7.12.4

[U-Boot] [PATCH v3 2/5] Exynos5: Config: Place environment at the end of SPI flash

[Akshay Saraswat]

Currently environment resides at the location where BL2 ends.
This may hold good in case there is an empty space at this
position. But what if this place already has a binary or is
expected to have one. To avoid such scenarios it is better
to save environment at the end of the flash.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
---
Changes since v2:
	- Added "Acked-by" & "Tested-by".
Changes since v1:
	- Added new config for SPI flash size.

 include/configs/exynos5-dt.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h
index 5a9b1b4..3bcec85 100644
--- a/include/configs/exynos5-dt.h
+++ b/include/configs/exynos5-dt.h
@@ -207,7 +207,10 @@
 
 #define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
 #define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
-#define CONFIG_ENV_OFFSET	(CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
+
+/* Store environment at the end of a 4 MB SPI flash */
+#define FLASH_SIZE		(0x4 << 20)
+#define CONFIG_ENV_OFFSET	(FLASH_SIZE - CONFIG_BL2_SIZE)
 
 /* U-boot copy size from boot Media to DRAM.*/
 #define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
-- 
1.7.12.4

[U-Boot] [PATCH v3 3/5] Exynos5: Config: Increase SPL footprint for Exynos5420

[Akshay Saraswat]

Max footprint for SPL in both Exynos 5250 and 5420 is limited to 14 KB.
For Exynos5250 we need to keep it 14 KB because BL1 supports only fixed
size SPL downloading. But in case of Exynos5420 we need not restrict it
to 14 KB. And also, the SPL size for Exynos5420 is expected to increase
with the upcoming patches and the patches under review right now.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
---
Changes since v2:
	- Added "Acked-by" & "Tested-by".
Changes since v1:
	- Changed 5420 SPL footprint from 32 to 30 KB.

 include/configs/exynos5-dt.h    | 2 --
 include/configs/exynos5250-dt.h | 2 ++
 include/configs/exynos5420.h    | 2 ++
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h
index 3bcec85..e9787c7 100644
--- a/include/configs/exynos5-dt.h
+++ b/include/configs/exynos5-dt.h
@@ -144,8 +144,6 @@
 
 /* specific .lds file */
 #define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
-#define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
-
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index b7ff472..9fff1af 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -20,6 +20,8 @@
 #define MACH_TYPE_SMDK5250		3774
 #define CONFIG_MACH_TYPE		MACH_TYPE_SMDK5250
 
+#define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
+
 /* USB */
 #define CONFIG_CMD_USB
 #define CONFIG_USB_XHCI
diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420.h
index 3a28bbc..2ffe5ee 100644
--- a/include/configs/exynos5420.h
+++ b/include/configs/exynos5420.h
@@ -25,6 +25,8 @@
 #endif
 #define CONFIG_IRAM_TOP			0x02074000
 
+#define CONFIG_SPL_MAX_FOOTPRINT	(30 * 1024)
+
 #define CONFIG_DEVICE_TREE_LIST "exynos5420-peach-pit exynos5420-smdk5420"
 
 #define CONFIG_MAX_I2C_NUM	11
-- 
1.7.12.4

[U-Boot] [PATCH v3 4/5] Exynos5: Config: Enable USB boot mode for all Exynos5 SoCs

[Akshay Saraswat]

Right now USB booting is enabled for Exynos5250 only. Moving all the
configs for USB boot mode from exynos5250-dt.h to exynos5-dt.h in order
to enableUSB booting for all Exynos5 SoCs.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
---
Changes since v2:
	- Added "Acked-by" & "Tested-by".
Changes since v1:
	- Added "Acked-by".

 include/configs/exynos5-dt.h    | 6 ++++++
 include/configs/exynos5250-dt.h | 6 ------
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h
index e9787c7..d3ef44c 100644
--- a/include/configs/exynos5-dt.h
+++ b/include/configs/exynos5-dt.h
@@ -291,4 +291,10 @@
 
 #define CONFIG_CMD_GPIO
 
+/* USB boot mode */
+#define CONFIG_USB_BOOTING
+#define EXYNOS_COPY_USB_FNPTR_ADDR	0x02020070
+#define EXYNOS_USB_SECONDARY_BOOT	0xfeed0002
+#define EXYNOS_IRAM_SECONDARY_BASE	0x02020018
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 9fff1af..10b8942 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -29,12 +29,6 @@
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE
 
-/* USB boot mode */
-#define CONFIG_USB_BOOTING
-#define EXYNOS_COPY_USB_FNPTR_ADDR	0x02020070
-#define EXYNOS_USB_SECONDARY_BOOT	0xfeed0002
-#define EXYNOS_IRAM_SECONDARY_BASE	0x02020018
-
 #define CONFIG_SPL_TEXT_BASE	0x02023400
 
 #define CONFIG_BOOTCOMMAND	"mmc read 40007000 451 2000; bootm 40007000"
-- 
1.7.12.4

[U-Boot] [PATCH v3 5/5] Exynos: Split 5250 and 5420 memory bank configuration

[Akshay Saraswat]

From: Michael Pratt <mpratt@chromium.org>

Since snow has a different memory configuration than peach, split the
configuration between the 5250 and 5420. Exynos 5420 supports runtime
memory configuration detection, and can make the determination between 4
and 7 banks at runtime.

Include the bank size with the number of banks for context to make the
number of banks meaningful.

Signed-off-by: Michael Pratt <mpratt@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
---
Changes since v2:
	- Added "Acked-by" & "Tested-by".
Changes since v1:
	- New patch.

 include/configs/exynos5-dt.h    | 2 --
 include/configs/exynos5250-dt.h | 5 +++++
 include/configs/exynos5420.h    | 4 ++++
 3 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h
index d3ef44c..fd607ee 100644
--- a/include/configs/exynos5-dt.h
+++ b/include/configs/exynos5-dt.h
@@ -161,8 +161,6 @@
 
 #define CONFIG_RD_LVL
 
-#define CONFIG_NR_DRAM_BANKS	8
-#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
 #define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
 #define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
 #define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 10b8942..27aa455 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -65,4 +65,9 @@
 #define LCD_YRES			1600
 #define LCD_BPP			LCD_COLOR16
 #endif
+
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS	8
+#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
+
 #endif  /* __CONFIG_5250_H */
diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420.h
index 2ffe5ee..d2a9556 100644
--- a/include/configs/exynos5420.h
+++ b/include/configs/exynos5420.h
@@ -45,4 +45,8 @@
  */
 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_IRAM_TOP - 0x800)
 
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS	7
+#define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */
+
 #endif	/* __CONFIG_EXYNOS5420_H */
-- 
1.7.12.4

[U-Boot] [PATCH v3 5/5] Exynos: Split 5250 and 5420 memory bank configuration

[Minkyu Kang]

Dear Akshay Saraswat,

On 04/06/14 01:17, Akshay Saraswat wrote:
> From: Michael Pratt <mpratt@chromium.org>
> 
> Since snow has a different memory configuration than peach, split the
> configuration between the 5250 and 5420. Exynos 5420 supports runtime
> memory configuration detection, and can make the determination between 4
> and 7 banks at runtime.

I think this patch should be included to your peach-pit patchset.
And I think, the number of banks and the size of bank seems to board specific feature.
Can you guarantee if it uses same SoC then have same memory banks?

> 
> Include the bank size with the number of banks for context to make the
> number of banks meaningful.
> 
> Signed-off-by: Michael Pratt <mpratt@chromium.org>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> Tested-by: Simon Glass <sjg@chromium.org>
> ---
> Changes since v2:
> 	- Added "Acked-by" & "Tested-by".
> Changes since v1:
> 	- New patch.
> 
>  include/configs/exynos5-dt.h    | 2 --
>  include/configs/exynos5250-dt.h | 5 +++++
>  include/configs/exynos5420.h    | 4 ++++
>  3 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h
> index d3ef44c..fd607ee 100644
> --- a/include/configs/exynos5-dt.h
> +++ b/include/configs/exynos5-dt.h
> @@ -161,8 +161,6 @@
>  
>  #define CONFIG_RD_LVL
>  
> -#define CONFIG_NR_DRAM_BANKS	8
> -#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
>  #define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
>  #define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
>  #define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
> diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
> index 10b8942..27aa455 100644
> --- a/include/configs/exynos5250-dt.h
> +++ b/include/configs/exynos5250-dt.h
> @@ -65,4 +65,9 @@
>  #define LCD_YRES			1600
>  #define LCD_BPP			LCD_COLOR16
>  #endif
> +
> +/* DRAM Memory Banks */
> +#define CONFIG_NR_DRAM_BANKS	8
> +#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
> +
>  #endif  /* __CONFIG_5250_H */
> diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420.h
> index 2ffe5ee..d2a9556 100644
> --- a/include/configs/exynos5420.h
> +++ b/include/configs/exynos5420.h
> @@ -45,4 +45,8 @@
>   */
>  #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_IRAM_TOP - 0x800)
>  
> +/* DRAM Memory Banks */
> +#define CONFIG_NR_DRAM_BANKS	7
> +#define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */
> +
>  #endif	/* __CONFIG_EXYNOS5420_H */
> 

Thanks,
Minkyu Kang.

[U-Boot] [PATCH v3 5/5] Exynos: Split 5250 and 5420 memory bank configuration

[Simon Glass]

Hi Minkyu,

On 16 June 2014 23:28, Minkyu Kang <mk7.kang@samsung.com> wrote:
> Dear Akshay Saraswat,
>
> On 04/06/14 01:17, Akshay Saraswat wrote:
>> From: Michael Pratt <mpratt@chromium.org>
>>
>> Since snow has a different memory configuration than peach, split the
>> configuration between the 5250 and 5420. Exynos 5420 supports runtime
>> memory configuration detection, and can make the determination between 4
>> and 7 banks at runtime.
>
> I think this patch should be included to your peach-pit patchset.
> And I think, the number of banks and the size of bank seems to board specific feature.
> Can you guarantee if it uses same SoC then have same memory banks?

I think this is better than what we have there at present. There is a
patch from Chromium that puts this in the device tree, but it is
probably best dealt with when more patches have landed.

Regards,
Simon

[U-Boot] [PATCH v3 5/5] Exynos: Split 5250 and 5420 memory bank configuration

[Minkyu Kang]

On 18/06/14 11:11, Simon Glass wrote:
> Hi Minkyu,
> 
> On 16 June 2014 23:28, Minkyu Kang <mk7.kang@samsung.com> wrote:
>> Dear Akshay Saraswat,
>>
>> On 04/06/14 01:17, Akshay Saraswat wrote:
>>> From: Michael Pratt <mpratt@chromium.org>
>>>
>>> Since snow has a different memory configuration than peach, split the
>>> configuration between the 5250 and 5420. Exynos 5420 supports runtime
>>> memory configuration detection, and can make the determination between 4
>>> and 7 banks at runtime.
>>
>> I think this patch should be included to your peach-pit patchset.
>> And I think, the number of banks and the size of bank seems to board specific feature.
>> Can you guarantee if it uses same SoC then have same memory banks?
> 
> I think this is better than what we have there at present. There is a
> patch from Chromium that puts this in the device tree, but it is
> probably best dealt with when more patches have landed.
> 

I didn't deny this patch.
My comment is about present state.
If you can not guarantee that have same memory banks
then please split this configuration to each board's configs.

Thanks,
Minkyu Kang.

[U-Boot] [PATCH v3 5/5] Exynos: Split 5250 and 5420 memory bank configuration

[Simon Glass]

Hi Minkyu,

On 17 June 2014 23:30, Minkyu Kang <mk7.kang@samsung.com> wrote:
> On 18/06/14 11:11, Simon Glass wrote:
>> Hi Minkyu,
>>
>> On 16 June 2014 23:28, Minkyu Kang <mk7.kang@samsung.com> wrote:
>>> Dear Akshay Saraswat,
>>>
>>> On 04/06/14 01:17, Akshay Saraswat wrote:
>>>> From: Michael Pratt <mpratt@chromium.org>
>>>>
>>>> Since snow has a different memory configuration than peach, split the
>>>> configuration between the 5250 and 5420. Exynos 5420 supports runtime
>>>> memory configuration detection, and can make the determination between 4
>>>> and 7 banks at runtime.
>>>
>>> I think this patch should be included to your peach-pit patchset.
>>> And I think, the number of banks and the size of bank seems to board specific feature.
>>> Can you guarantee if it uses same SoC then have same memory banks?
>>
>> I think this is better than what we have there at present. There is a
>> patch from Chromium that puts this in the device tree, but it is
>> probably best dealt with when more patches have landed.
>>
>
> I didn't deny this patch.
> My comment is about present state.
> If you can not guarantee that have same memory banks
> then please split this configuration to each board's configs.

For Pit which can support 2GB or 4GB, U-Boot detects the correct size
at run-time. So the setting in the config file is the *maximum* memory
supported by that SOC, which is indeed fixed by the SOC and has
nothing to do with the board.

But i maybe misunderstand what you are getting at?

Regards,
Simon

[U-Boot] [PATCH v3 5/5] Exynos: Split 5250 and 5420 memory bank configuration

[Minkyu Kang]

Dear Simon Glass,

On 18/06/14 15:47, Simon Glass wrote:
> Hi Minkyu,
> 
> On 17 June 2014 23:30, Minkyu Kang <mk7.kang@samsung.com> wrote:
>> On 18/06/14 11:11, Simon Glass wrote:
>>> Hi Minkyu,
>>>
>>> On 16 June 2014 23:28, Minkyu Kang <mk7.kang@samsung.com> wrote:
>>>> Dear Akshay Saraswat,
>>>>
>>>> On 04/06/14 01:17, Akshay Saraswat wrote:
>>>>> From: Michael Pratt <mpratt@chromium.org>
>>>>>
>>>>> Since snow has a different memory configuration than peach, split the
>>>>> configuration between the 5250 and 5420. Exynos 5420 supports runtime
>>>>> memory configuration detection, and can make the determination between 4
>>>>> and 7 banks at runtime.
>>>>
>>>> I think this patch should be included to your peach-pit patchset.
>>>> And I think, the number of banks and the size of bank seems to board specific feature.
>>>> Can you guarantee if it uses same SoC then have same memory banks?
>>>
>>> I think this is better than what we have there at present. There is a
>>> patch from Chromium that puts this in the device tree, but it is
>>> probably best dealt with when more patches have landed.
>>>
>>
>> I didn't deny this patch.
>> My comment is about present state.
>> If you can not guarantee that have same memory banks
>> then please split this configuration to each board's configs.
> 
> For Pit which can support 2GB or 4GB, U-Boot detects the correct size
> at run-time. So the setting in the config file is the *maximum* memory
> supported by that SOC, which is indeed fixed by the SOC and has
> nothing to do with the board.

I see.
Then looks good to me.

Thanks,
Minkyu Kang.