[U-Boot] [Patch v4 2/5] ARMv8: Adjust MMU setup

York Sun
2014-06-06T22:14:23Z

On 06/06/2014 01:17 PM, York Sun wrote:
> On 06/06/2014 10:32 AM, Mark Rutland wrote:
>>>> How is TCR_EL2.SH0 (or TCR_EL1.SH*) configured?
>>>>
>>>> You'll only need to flush the cache if they're configured non shareable.
>>>
>>> It is configured as non shareable.
>>
>> Is there any reason not to configure them as inner shareable? That way
>> the MMU will look in the D-cache, and you won't have to spend time
>> flushing them.
>>
>
> Mark,
>
> I appreciate the reminder. I tried on our emulator. With inner share set for TCR
> SH0 bits, u-boot works with the flushing, but doesn't work without flushing. It
> went to exception.
>
> Can you share more information about the inner share? I need to follow up with
> our designer to confirm.
>

A second thought, do I need to set the first MMU table so DDR is inner shareable?

York