* [U-Boot] [PATCH v2 01/13] board: controlcenterd: Fix pci access
2014-07-02 7:31 [U-Boot] [PATCH v2 0/13] Fixes on gdsys boards and some new functionality dirk.eibach at gdsys.cc
@ 2014-07-02 7:31 ` dirk.eibach at gdsys.cc
2014-07-02 7:31 ` [U-Boot] [PATCH v2 02/13] board: gdsys: Adapt sdhc_boot.c to mmc_get_env_addr API change dirk.eibach at gdsys.cc
` (11 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: dirk.eibach at gdsys.cc @ 2014-07-02 7:31 UTC (permalink / raw)
To: u-boot
From: Dirk Eibach <dirk.eibach@gdsys.cc>
readl was called with values instead of pointers to these values.
Why this ever did work is a mystery...
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
---
Changes in v2: None
board/gdsys/p1022/controlcenterd.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c
index 8ccd9ce..0a3517d 100644
--- a/board/gdsys/p1022/controlcenterd.c
+++ b/board/gdsys/p1022/controlcenterd.c
@@ -386,9 +386,9 @@ static void hydra_initialize(void)
fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
PCI_REGION_MEM);
- versions = readl(fpga->versions);
- fpga_version = readl(fpga->fpga_version);
- fpga_features = readl(fpga->fpga_features);
+ versions = readl(&fpga->versions);
+ fpga_version = readl(&fpga->fpga_version);
+ fpga_features = readl(&fpga->fpga_features);
hardware_version = versions & 0xf;
feature_uart_channels = (fpga_features >> 6) & 0x1f;
--
1.8.3
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [PATCH v2 02/13] board: gdsys: Adapt sdhc_boot.c to mmc_get_env_addr API change
2014-07-02 7:31 [U-Boot] [PATCH v2 0/13] Fixes on gdsys boards and some new functionality dirk.eibach at gdsys.cc
2014-07-02 7:31 ` [U-Boot] [PATCH v2 01/13] board: controlcenterd: Fix pci access dirk.eibach at gdsys.cc
@ 2014-07-02 7:31 ` dirk.eibach at gdsys.cc
2014-07-02 7:31 ` [U-Boot] [PATCH v2 03/13] board: controlcenterd: Use new API for setting i2c bus dirk.eibach at gdsys.cc
` (10 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: dirk.eibach at gdsys.cc @ 2014-07-02 7:31 UTC (permalink / raw)
To: u-boot
From: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
---
Changes in v2: None
board/gdsys/p1022/sdhc_boot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/gdsys/p1022/sdhc_boot.c b/board/gdsys/p1022/sdhc_boot.c
index e432318..fd0e910 100644
--- a/board/gdsys/p1022/sdhc_boot.c
+++ b/board/gdsys/p1022/sdhc_boot.c
@@ -32,7 +32,7 @@
#define ESDHC_BOOT_IMAGE_SIZE 0x48
#define ESDHC_BOOT_IMAGE_ADDR 0x50
-int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr)
+int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
{
u8 *tmp_buf;
u32 blklen, code_offset, code_len, n;
--
1.8.3
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [PATCH v2 03/13] board: controlcenterd: Use new API for setting i2c bus
2014-07-02 7:31 [U-Boot] [PATCH v2 0/13] Fixes on gdsys boards and some new functionality dirk.eibach at gdsys.cc
2014-07-02 7:31 ` [U-Boot] [PATCH v2 01/13] board: controlcenterd: Fix pci access dirk.eibach at gdsys.cc
2014-07-02 7:31 ` [U-Boot] [PATCH v2 02/13] board: gdsys: Adapt sdhc_boot.c to mmc_get_env_addr API change dirk.eibach at gdsys.cc
@ 2014-07-02 7:31 ` dirk.eibach at gdsys.cc
2014-07-02 7:31 ` [U-Boot] [PATCH v2 04/13] board: iocon: Support DisplayPort hardware dirk.eibach at gdsys.cc
` (9 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: dirk.eibach at gdsys.cc @ 2014-07-02 7:31 UTC (permalink / raw)
To: u-boot
From: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
---
Changes in v2:
- use defines for I2C bus numbers
board/gdsys/p1022/controlcenterd-id.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/board/gdsys/p1022/controlcenterd-id.c b/board/gdsys/p1022/controlcenterd-id.c
index 3fca3c5..419fc2e 100644
--- a/board/gdsys/p1022/controlcenterd-id.c
+++ b/board/gdsys/p1022/controlcenterd-id.c
@@ -86,6 +86,11 @@ enum {
ESDHC_BOOT_IMAGE_ENTRY_OFS = 0x60,
};
+enum {
+ I2C_SOC_0 = 0,
+ I2C_SOC_1 = 1,
+};
+
struct key_program {
uint32_t magic;
uint32_t code_crc;
@@ -1156,7 +1161,7 @@ static void ccdm_hang(void)
int j;
#endif
- I2C_SET_BUS(0);
+ I2C_SET_BUS(I2C_SOC_0);
pca9698_direction_output(0x22, 0, 0); /* Finder */
pca9698_direction_output(0x22, 4, 0); /* Status */
@@ -1189,8 +1194,8 @@ int startup_ccdm_id_module(void)
int result = 0;
unsigned int orig_i2c_bus;
- orig_i2c_bus = I2C_GET_BUS();
- I2C_SET_BUS(1);
+ orig_i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(I2C_SOC_1);
/* goto end; */
@@ -1216,7 +1221,7 @@ int startup_ccdm_id_module(void)
failure:
result = 1;
end:
- I2C_SET_BUS(orig_i2c_bus);
+ i2c_set_bus_num(orig_i2c_bus);
if (result)
ccdm_hang();
--
1.8.3
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [PATCH v2 04/13] board: iocon: Support DisplayPort hardware
2014-07-02 7:31 [U-Boot] [PATCH v2 0/13] Fixes on gdsys boards and some new functionality dirk.eibach at gdsys.cc
` (2 preceding siblings ...)
2014-07-02 7:31 ` [U-Boot] [PATCH v2 03/13] board: controlcenterd: Use new API for setting i2c bus dirk.eibach at gdsys.cc
@ 2014-07-02 7:31 ` dirk.eibach at gdsys.cc
2014-07-02 7:31 ` [U-Boot] [PATCH v2 05/13] i2c: IHS I2C master driver dirk.eibach at gdsys.cc
` (8 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: dirk.eibach at gdsys.cc @ 2014-07-02 7:31 UTC (permalink / raw)
To: u-boot
From: Dirk Eibach <dirk.eibach@gdsys.cc>
There is a new iocon hardware flavor, supporting DisplayPort finally.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
---
Changes in v2: None
board/gdsys/405ep/iocon.c | 12 +++++
board/gdsys/common/Makefile | 2 +-
board/gdsys/common/dp501.c | 33 +++++++++----
board/gdsys/common/osd.c | 112 ++++++++++++++++----------------------------
include/configs/iocon.h | 9 +++-
5 files changed, 83 insertions(+), 85 deletions(-)
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index 7a98e41..079dfb2 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -15,6 +15,7 @@
#include "405ep.h"
#include <gdsys_fpga.h>
+#include "../common/dp501.h"
#include "../common/osd.h"
#include "../common/mclink.h"
@@ -98,6 +99,8 @@ enum {
unsigned int mclink_fpgacount;
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
+
static int setup_88e1518(const char *bus, unsigned char addr);
int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
@@ -371,9 +374,18 @@ int last_stage_init(void)
u16 fpga_features;
int feature_carrier_speed = fpga_features & (1<<4);
bool ch0_rgmii2_present = false;
+ int old_bus = i2c_get_bus_num();
FPGA_GET_REG(0, fpga_features, &fpga_features);
+ /* Turn on Parade DP501 */
+ pca9698_direction_output(0x20, 9, 1);
+ udelay(500000);
+
+ i2c_set_bus_num(dp501_i2c[0]);
+ dp501_powerup(0x08);
+ i2c_set_bus_num(old_bus);
+
if (!legacy)
ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
index fb841e0..7f8b427 100644
--- a/board/gdsys/common/Makefile
+++ b/board/gdsys/common/Makefile
@@ -8,6 +8,6 @@
obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
obj-$(CONFIG_IO) += miiphybb.o
obj-$(CONFIG_IO64) += miiphybb.o
-obj-$(CONFIG_IOCON) += osd.o mclink.o
+obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o
obj-$(CONFIG_DLVISION_10G) += osd.o
obj-$(CONFIG_CONTROLCENTERD) += dp501.o
diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c
index 52f3ea1..e00e589 100644
--- a/board/gdsys/common/dp501.c
+++ b/board/gdsys/common/dp501.c
@@ -60,8 +60,31 @@ void dp501_powerup(u8 addr)
i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */
dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */
dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */
+
+#ifdef CONFIG_SYS_DP501_VCAPCTRL0
+ i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0);
+#else
i2c_reg_write(addr, 0x24, 0xc0); /* SDR mode 0, ext. H/VSYNC */
+#endif
+
+#ifdef CONFIG_SYS_DP501_DIFFERENTIAL
+ i2c_reg_write(addr + 2, 0x24, 0x10); /* clock input differential */
+ i2c_reg_write(addr + 2, 0x25, 0x04);
+ i2c_reg_write(addr + 2, 0x26, 0x10);
+#else
i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */
+#endif
+
+ i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
+ i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
+ i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
+ i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
+ i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
+ i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
+ dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
+ i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
+ i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
+ i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */
if (dp501_detect_cable_adapter(addr)) {
printf("DVI/HDMI cable adapter detected\n");
@@ -69,16 +92,6 @@ void dp501_powerup(u8 addr)
dp501_clrbits(addr, 0x00, 0x08); /* DVI/HDMI HDCP operation */
} else {
printf("no DVI/HDMI cable adapter detected\n");
- i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
- i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
- i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
- i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
- i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
- i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
- dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
- i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
- i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
- i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */
dp501_setbits(addr, 0x00, 0x08); /* for DP HDCP operation */
dp501_link_training(addr);
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index c49cd9a..a839a4e 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -58,45 +58,12 @@ unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1;
int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
#endif
-#if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
-static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
-{
- u16 val;
-
- do {
- FPGA_GET_REG(screen, extended_interrupt, &val);
- } while (val & (1 << 12));
-
- FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg | (data << 8));
- FPGA_SET_REG(screen, i2c.write_mailbox, 0xc400 | (slave << 1));
-}
-
-static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
-{
- unsigned int ctr = 0;
- u16 val;
-
- do {
- FPGA_GET_REG(screen, extended_interrupt, &val);
- } while (val & (1 << 12));
-
- FPGA_SET_REG(screen, extended_interrupt, 1 << 14);
- FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg);
- FPGA_SET_REG(screen, i2c.write_mailbox, 0xc000 | (slave << 1));
-
- FPGA_GET_REG(screen, extended_interrupt, &val);
- while (!(val & (1 << 14))) {
- udelay(100000);
- if (ctr++ > 5) {
- printf("iic receive timeout\n");
- break;
- }
- FPGA_GET_REG(screen, extended_interrupt, &val);
- }
+#ifdef CONFIG_SYS_ICS8N3QV01
+int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
+#endif
- FPGA_GET_REG(screen, i2c.read_mailbox_ext, &val);
- return val >> 8;
-}
+#ifdef CONFIG_SYS_SIL1178
+int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
#endif
#ifdef CONFIG_SYS_MPC92469AC
@@ -153,7 +120,7 @@ static void mpc92469ac_set(unsigned screen, unsigned int fout)
#ifdef CONFIG_SYS_ICS8N3QV01
-static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index)
+static unsigned int ics8n3qv01_get_fout_calc(unsigned index)
{
unsigned long long n;
unsigned long long mint;
@@ -164,11 +131,11 @@ static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index)
if (index > 3)
return 0;
- reg_a = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0 + index);
- reg_b = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 4 + index);
- reg_c = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 8 + index);
- reg_d = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 12 + index);
- reg_f = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20 + index);
+ reg_a = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0 + index);
+ reg_b = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 4 + index);
+ reg_c = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 8 + index);
+ reg_d = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 12 + index);
+ reg_f = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20 + index);
mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20);
mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1)
@@ -216,7 +183,7 @@ static void ics8n3qv01_calc_parameters(unsigned int fout,
*_n = n;
}
-static void ics8n3qv01_set(unsigned screen, unsigned int fout)
+static void ics8n3qv01_set(unsigned int fout)
{
unsigned int n;
unsigned int mint;
@@ -226,7 +193,7 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout)
long long off_ppm;
u8 reg0, reg4, reg8, reg12, reg18, reg20;
- fout_calc = ics8n3qv01_get_fout_calc(screen, 1);
+ fout_calc = ics8n3qv01_get_fout_calc(1);
off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000
/ ICS8N3QV01_F_DEFAULT_1;
printf(" PLL is off by %lld ppm\n", off_ppm);
@@ -234,28 +201,28 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout)
/ ICS8N3QV01_F_DEFAULT_1;
ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n);
- reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
+ reg0 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
reg0 |= (mint & 0x1f) << 1;
reg0 |= (mfrac >> 17) & 0x01;
- fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0);
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 0, reg0);
reg4 = mfrac >> 9;
- fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4);
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 4, reg4);
reg8 = mfrac >> 1;
- fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8);
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 8, reg8);
reg12 = mfrac << 7;
reg12 |= n & 0x7f;
- fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12);
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 12, reg12);
- reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03;
+ reg18 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 18) & 0x03;
reg18 |= 0x20;
- fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18);
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 18, reg18);
- reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
+ reg20 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
reg20 |= mint & (1 << 5);
- fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20);
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 20, reg20);
}
#endif
@@ -315,9 +282,7 @@ int osd_probe(unsigned screen)
u16 version;
u16 features;
u8 value;
-#ifdef CONFIG_SYS_CH7301
int old_bus = i2c_get_bus_num();
-#endif
FPGA_GET_REG(0, osd.version, &version);
FPGA_GET_REG(0, osd.features, &features);
@@ -345,7 +310,6 @@ int osd_probe(unsigned screen)
i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
- i2c_set_bus_num(old_bus);
#endif
#ifdef CONFIG_SYS_MPC92469AC
@@ -353,29 +317,31 @@ int osd_probe(unsigned screen)
#endif
#ifdef CONFIG_SYS_ICS8N3QV01
- ics8n3qv01_set(screen, PIXCLK_640_480_60);
+ i2c_set_bus_num(ics8n3qv01_i2c[screen]);
+ ics8n3qv01_set(PIXCLK_640_480_60);
#endif
#ifdef CONFIG_SYS_SIL1178
- value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02);
+ i2c_set_bus_num(sil1178_i2c[screen]);
+ value = i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02);
if (value != 0x06) {
- printf(" Probing CH7301 SIL1178, DEV_IDL %02x\n", value);
+ printf(" Probing SIL1178, DEV_IDL %02x\n", value);
+ i2c_set_bus_num(old_bus);
return -1;
}
/* magic initialization sequence adapted from datasheet */
- fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
+ i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
#endif
- FPGA_SET_REG(screen, videocontrol, 0x0002);
FPGA_SET_REG(screen, osd.control, 0x0049);
FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1));
@@ -385,6 +351,8 @@ int osd_probe(unsigned screen)
if (screen > max_osd_screen)
max_osd_screen = screen;
+ i2c_set_bus_num(old_bus);
+
return 0;
}
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index f36c2a3..5636f38 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -121,7 +121,9 @@
#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
+#define CONFIG_SYS_ICS8N3QV01_I2C {1, 2, 3, 4}
#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
+#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
#ifndef __ASSEMBLY__
void fpga_gpio_set(unsigned int bus, int pin);
@@ -146,6 +148,8 @@ int fpga_gpio_get(unsigned int bus, int pin);
fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
else \
fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
+ while (!!fpga_gpio_get(I2C_ADAP_HWNR, 0x0020) != !!bit) \
+ ; \
} while (0)
#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
@@ -153,7 +157,6 @@ int fpga_gpio_get(unsigned int bus, int pin);
* OSD hardware
*/
#define CONFIG_SYS_MPC92469AC
-#define CONFIG_SYS_CH7301
/*
* FLASH organization
@@ -282,9 +285,11 @@ int fpga_gpio_get(unsigned int bus, int pin);
/*
* OSD Setup
*/
+#define CONFIG_SYS_ICS8N3QV01
#define CONFIG_SYS_MPC92469AC
-#define CONFIG_SYS_CH7301
#define CONFIG_SYS_OSD_SCREENS 1
+#define CONFIG_SYS_DP501_DIFFERENTIAL
+#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
#define CONFIG_BITBANGMII_MULTI
--
1.8.3
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [PATCH v2 05/13] i2c: IHS I2C master driver
2014-07-02 7:31 [U-Boot] [PATCH v2 0/13] Fixes on gdsys boards and some new functionality dirk.eibach at gdsys.cc
` (3 preceding siblings ...)
2014-07-02 7:31 ` [U-Boot] [PATCH v2 04/13] board: iocon: Support DisplayPort hardware dirk.eibach at gdsys.cc
@ 2014-07-02 7:31 ` dirk.eibach at gdsys.cc
2014-07-02 8:30 ` Heiko Schocher
2014-07-02 7:31 ` [U-Boot] [PATCH v2 06/13] board: gdsys: Fix dlvision-10g I2C configuration dirk.eibach at gdsys.cc
` (7 subsequent siblings)
12 siblings, 1 reply; 15+ messages in thread
From: dirk.eibach at gdsys.cc @ 2014-07-02 7:31 UTC (permalink / raw)
To: u-boot
From: Dirk Eibach <dirk.eibach@gdsys.cc>
IHS I2C master support was merely a hack in the osd driver.
Now it is a proper u-boot I2C framework driver, supporting the
v2.00 master features.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
---
Changes in v2:
- move ihs_i2c to drivers/i2c
- split unrelated changes
drivers/i2c/Makefile | 1 +
drivers/i2c/ihs_i2c.c | 204 +++++++++++++++++++++++++++++++++++++++++
include/configs/dlvision-10g.h | 11 +++
include/configs/iocon.h | 23 ++++-
include/gdsys_fpga.h | 25 +++--
5 files changed, 246 insertions(+), 18 deletions(-)
create mode 100644 drivers/i2c/ihs_i2c.c
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index e33586d..96bd45d 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_SYS_I2C) += i2c_core.o
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
+obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c
new file mode 100644
index 0000000..ecc5856
--- /dev/null
+++ b/drivers/i2c/ihs_i2c.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2013
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach at gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <gdsys_fpga.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ I2CINT_ERROR_EV = 1 << 13,
+ I2CINT_TRANSMIT_EV = 1 << 14,
+ I2CINT_RECEIVE_EV = 1 << 15,
+};
+
+enum {
+ I2CMB_WRITE = 1 << 10,
+ I2CMB_2BYTE = 1 << 11,
+ I2CMB_HOLD_BUS = 1 << 13,
+ I2CMB_NATIVE = 2 << 14,
+};
+
+static int wait_for_int(bool read)
+{
+ u16 val;
+ unsigned int ctr = 0;
+
+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
+ while (!(val & (I2CINT_ERROR_EV
+ | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
+ udelay(10);
+ if (ctr++ > 5000) {
+ printf("I2C timeout\n");
+ return 1;
+ }
+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
+ }
+
+ return (val & I2CINT_ERROR_EV) ? 1 : 0;
+}
+
+static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
+ bool is_last)
+{
+ u16 val;
+
+ FPGA_SET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, I2CINT_ERROR_EV
+ | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV);
+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
+
+ if (!read && len) {
+ val = buffer[0];
+
+ if (len > 1)
+ val |= buffer[1] << 8;
+ FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox_ext, val);
+ }
+
+ FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox,
+ I2CMB_NATIVE
+ | (read ? 0 : I2CMB_WRITE)
+ | (chip << 1)
+ | ((len > 1) ? I2CMB_2BYTE : 0)
+ | (is_last ? 0 : I2CMB_HOLD_BUS));
+
+ if (wait_for_int(read))
+ return 1;
+
+ if (read) {
+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c.read_mailbox_ext, &val);
+ buffer[0] = val & 0xff;
+ if (len > 1)
+ buffer[1] = val >> 8;
+ }
+
+ return 0;
+}
+
+static int ihs_i2c_address(uchar chip, uint addr, int alen, bool hold_bus)
+{
+ int shift = (alen-1) * 8;
+
+ while (alen) {
+ int transfer = MIN(alen, 2);
+ uchar buf[2];
+ bool is_last = alen <= transfer;
+
+ buf[0] = addr >> shift;
+ if (alen > 1)
+ buf[1] = addr >> (shift - 8);
+
+ if (ihs_i2c_transfer(chip, buf, transfer, false,
+ hold_bus ? false : is_last))
+ return 1;
+
+ shift -= 16;
+ alen -= transfer;
+ }
+
+ return 0;
+}
+
+static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len, bool read)
+{
+ if (len <= 0)
+ return 1;
+
+ if (ihs_i2c_address(chip, addr, alen, !read))
+ return 1;
+
+ while (len) {
+ int transfer = MIN(len, 2);
+
+ if (ihs_i2c_transfer(chip, buffer, transfer, read,
+ len <= transfer))
+ return 1;
+
+ buffer += transfer;
+ addr += transfer;
+ len -= transfer;
+ }
+
+ return 0;
+}
+
+
+static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
+{
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+ /*
+ * Call board specific i2c bus reset routine before accessing the
+ * environment, which might be in a chip on that bus. For details
+ * about this problem see doc/I2C_Edge_Conditions.
+ */
+ i2c_init_board();
+#endif
+}
+
+static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
+{
+ uchar buffer[2];
+
+ if (ihs_i2c_transfer(chip, buffer, 0, true, true))
+ return 1;
+
+ return 0;
+}
+
+static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
+{
+ return ihs_i2c_access(adap, chip, addr, alen, buffer, len, true);
+}
+
+static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
+{
+ return ihs_i2c_access(adap, chip, addr, alen, buffer, len, false);
+}
+
+static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
+ unsigned int speed)
+{
+ if (speed != adap->speed)
+ return 1;
+ return speed;
+}
+
+/*
+ * Register IHS i2c adapters
+ */
+#ifdef CONFIG_SYS_I2C_IHS_CH0
+U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
+ ihs_i2c_read, ihs_i2c_write,
+ ihs_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_IHS_SPEED_0,
+ CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
+#endif
+#ifdef CONFIG_SYS_I2C_IHS_CH1
+U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
+ ihs_i2c_read, ihs_i2c_write,
+ ihs_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_IHS_SPEED_1,
+ CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
+#endif
+#ifdef CONFIG_SYS_I2C_IHS_CH2
+U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
+ ihs_i2c_read, ihs_i2c_write,
+ ihs_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_IHS_SPEED_2,
+ CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
+#endif
+#ifdef CONFIG_SYS_I2C_IHS_CH3
+U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
+ ihs_i2c_read, ihs_i2c_write,
+ ihs_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_IHS_SPEED_3,
+ CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
+#endif
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 7877897..05a97bf 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -99,7 +99,18 @@
*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
+#define CONFIG_SYS_I2C_IHS
+#define CONFIG_SYS_I2C_IHS_CH0
+#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
+#define CONFIG_SYS_I2C_IHS_CH1
+#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
+
+#define CONFIG_SYS_SPD_BUS_NUM 2
+
/* Temp sensor/hwmon/dtt */
+#define CONFIG_SYS_DTT_BUS_NUM 2
#define CONFIG_DTT_LM63 1 /* National LM63 */
#define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 } /* Sensor addresses */
#define CONFIG_DTT_PWM_LOOKUPTABLE \
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 5636f38..36b4b55 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -99,12 +99,27 @@
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
+#define CONFIG_SYS_I2C_IHS
#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_SPD_BUS_NUM 4
#define CONFIG_PCA953X /* NXP PCA9554 */
#define CONFIG_PCA9698 /* NXP PCA9698 */
+#define CONFIG_SYS_I2C_IHS_CH0
+#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
+#define CONFIG_SYS_I2C_IHS_CH1
+#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
+#define CONFIG_SYS_I2C_IHS_CH2
+#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
+#define CONFIG_SYS_I2C_IHS_CH3
+#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
+
/*
* Software (bit-bang) I2C driver configuration
*/
@@ -121,9 +136,9 @@
#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
-#define CONFIG_SYS_ICS8N3QV01_I2C {1, 2, 3, 4}
-#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
-#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
+#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
+#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
+#define CONFIG_SYS_DP501_I2C {0, 1, 2, 3}
#ifndef __ASSEMBLY__
void fpga_gpio_set(unsigned int bus, int pin);
@@ -148,8 +163,6 @@ int fpga_gpio_get(unsigned int bus, int pin);
fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
else \
fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
- while (!!fpga_gpio_get(I2C_ADAP_HWNR, 0x0020) != !!bit) \
- ; \
} while (0)
#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index 85ddbcb..276a01e 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -43,10 +43,12 @@ struct ihs_gpio {
};
struct ihs_i2c {
- u16 write_mailbox;
+ u16 interrupt_status;
+ u16 interrupt_enable;
u16 write_mailbox_ext;
- u16 read_mailbox;
+ u16 write_mailbox;
u16 read_mailbox_ext;
+ u16 read_mailbox;
};
struct ihs_osd {
@@ -84,7 +86,6 @@ struct ihs_fpga {
#endif
#ifdef CONFIG_IO64
-
struct ihs_fpga_channel {
u16 status_int;
u16 config_int;
@@ -121,9 +122,9 @@ struct ihs_fpga {
u16 reserved_0[6]; /* 0x0008 */
struct ihs_gpio gpio; /* 0x0014 */
u16 mpc3w_control; /* 0x001a */
- u16 reserved_1[19]; /* 0x001c */
- u16 videocontrol; /* 0x0042 */
- u16 reserved_2[14]; /* 0x0044 */
+ u16 reserved_1[18]; /* 0x001c */
+ struct ihs_i2c i2c; /* 0x0040 */
+ u16 reserved_2[10]; /* 0x004c */
u16 mc_int; /* 0x0060 */
u16 mc_int_en; /* 0x0062 */
u16 mc_status; /* 0x0064 */
@@ -150,15 +151,13 @@ struct ihs_fpga {
u16 fpga_features; /* 0x0006 */
u16 reserved_0[10]; /* 0x0008 */
u16 extended_interrupt; /* 0x001c */
- u16 reserved_1[9]; /* 0x001e */
- struct ihs_i2c i2c; /* 0x0030 */
- u16 reserved_2[16]; /* 0x0038 */
+ u16 reserved_1[29]; /* 0x001e */
u16 mpc3w_control; /* 0x0058 */
- u16 reserved_3[34]; /* 0x005a */
- u16 videocontrol; /* 0x009e */
- u16 reserved_4[176]; /* 0x00a0 */
+ u16 reserved_2[3]; /* 0x005a */
+ struct ihs_i2c i2c; /* 0x0060 */
+ u16 reserved_3[205]; /* 0x0066 */
struct ihs_osd osd; /* 0x0200 */
- u16 reserved_5[761]; /* 0x020e */
+ u16 reserved_4[761]; /* 0x020e */
u16 videomem[31736]; /* 0x0800 */
};
#endif
--
1.8.3
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [PATCH v2 05/13] i2c: IHS I2C master driver
2014-07-02 7:31 ` [U-Boot] [PATCH v2 05/13] i2c: IHS I2C master driver dirk.eibach at gdsys.cc
@ 2014-07-02 8:30 ` Heiko Schocher
0 siblings, 0 replies; 15+ messages in thread
From: Heiko Schocher @ 2014-07-02 8:30 UTC (permalink / raw)
To: u-boot
Hello Dirk,
Am 02.07.2014 09:31, schrieb dirk.eibach at gdsys.cc:
> From: Dirk Eibach<dirk.eibach@gdsys.cc>
>
> IHS I2C master support was merely a hack in the osd driver.
> Now it is a proper u-boot I2C framework driver, supporting the
> v2.00 master features.
>
> Signed-off-by: Dirk Eibach<dirk.eibach@gdsys.cc>
>
> ---
>
> Changes in v2:
> - move ihs_i2c to drivers/i2c
> - split unrelated changes
>
> drivers/i2c/Makefile | 1 +
> drivers/i2c/ihs_i2c.c | 204 +++++++++++++++++++++++++++++++++++++++++
> include/configs/dlvision-10g.h | 11 +++
> include/configs/iocon.h | 23 ++++-
> include/gdsys_fpga.h | 25 +++--
> 5 files changed, 246 insertions(+), 18 deletions(-)
> create mode 100644 drivers/i2c/ihs_i2c.c
Please add a small entry in README, which describes your new config
defines, thanks!
Beside of this, your driver looks Ok to me, thanks!
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v2 06/13] board: gdsys: Fix dlvision-10g I2C configuration
2014-07-02 7:31 [U-Boot] [PATCH v2 0/13] Fixes on gdsys boards and some new functionality dirk.eibach at gdsys.cc
` (4 preceding siblings ...)
2014-07-02 7:31 ` [U-Boot] [PATCH v2 05/13] i2c: IHS I2C master driver dirk.eibach at gdsys.cc
@ 2014-07-02 7:31 ` dirk.eibach at gdsys.cc
2014-07-02 7:31 ` [U-Boot] [PATCH v2 07/13] board: gdsys: Increase iocon and dlv10g version string dirk.eibach at gdsys.cc
` (6 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: dirk.eibach at gdsys.cc @ 2014-07-02 7:31 UTC (permalink / raw)
To: u-boot
From: Dirk Eibach <dirk.eibach@gdsys.cc>
PPC4xx config options were not complete.
ICS8N3QV01 and SIL1178 needed some more configuration.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
---
Changes in v2: None
include/configs/dlvision-10g.h | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 05a97bf..16895bf 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -97,7 +97,10 @@
/*
* I2C stuff
*/
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_IHS
#define CONFIG_SYS_I2C_IHS_CH0
@@ -118,6 +121,11 @@
{ 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
#define CONFIG_DTT_TACH_LIMIT 0xa10
+#define CONFIG_SYS_ICS8N3QV01
+#define CONFIG_SYS_ICS8N3QV01_I2C {0, 1}
+#define CONFIG_SYS_SIL1178
+#define CONFIG_SYS_SIL1178_I2C {0, 1}
+
/* EBC peripherals */
#define CONFIG_SYS_FLASH_BASE 0xFC000000
@@ -317,9 +325,7 @@
/*
* OSD Setup
*/
-#define CONFIG_SYS_ICS8N3QV01
#define CONFIG_SYS_MPC92469AC
-#define CONFIG_SYS_SIL1178
#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
#endif /* __CONFIG_H */
--
1.8.3
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [PATCH v2 07/13] board: gdsys: Increase iocon and dlv10g version string
2014-07-02 7:31 [U-Boot] [PATCH v2 0/13] Fixes on gdsys boards and some new functionality dirk.eibach at gdsys.cc
` (5 preceding siblings ...)
2014-07-02 7:31 ` [U-Boot] [PATCH v2 06/13] board: gdsys: Fix dlvision-10g I2C configuration dirk.eibach at gdsys.cc
@ 2014-07-02 7:31 ` dirk.eibach at gdsys.cc
2014-07-02 7:31 ` [U-Boot] [PATCH v2 08/13] board: gdsys: Configure bridge on DP501 to support DDC only dirk.eibach at gdsys.cc
` (5 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: dirk.eibach at gdsys.cc @ 2014-07-02 7:31 UTC (permalink / raw)
To: u-boot
From: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
---
Changes in v2: None
include/configs/dlvision-10g.h | 2 +-
include/configs/iocon.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 16895bf..c2289ce 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -17,7 +17,7 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME dlvsion-10g
-#define CONFIG_IDENT_STRING " dlvision-10g 0.05"
+#define CONFIG_IDENT_STRING " dlvision-10g 0.06"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 36b4b55..1aebab3 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -17,7 +17,7 @@
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME iocon
-#define CONFIG_IDENT_STRING " iocon 0.05"
+#define CONFIG_IDENT_STRING " iocon 0.06"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F
--
1.8.3
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [PATCH v2 08/13] board: gdsys: Configure bridge on DP501 to support DDC only
2014-07-02 7:31 [U-Boot] [PATCH v2 0/13] Fixes on gdsys boards and some new functionality dirk.eibach at gdsys.cc
` (6 preceding siblings ...)
2014-07-02 7:31 ` [U-Boot] [PATCH v2 07/13] board: gdsys: Increase iocon and dlv10g version string dirk.eibach at gdsys.cc
@ 2014-07-02 7:31 ` dirk.eibach at gdsys.cc
2014-07-02 7:31 ` [U-Boot] [PATCH v2 09/13] board: gdsys: Make gdsys osd hardware detection more robust dirk.eibach at gdsys.cc
` (4 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: dirk.eibach at gdsys.cc @ 2014-07-02 7:31 UTC (permalink / raw)
To: u-boot
From: Dirk Eibach <dirk.eibach@gdsys.cc>
The I2C bridge on DP501 supports EDID, MCCS and HDCP by default.
Allow EDID only to avoid I2C address conflicts.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
---
Changes in v2: None
board/gdsys/common/dp501.c | 1 +
include/configs/controlcenterd.h | 7 ++++---
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c
index e00e589..7958bae 100644
--- a/board/gdsys/common/dp501.c
+++ b/board/gdsys/common/dp501.c
@@ -54,6 +54,7 @@ static void dp501_link_training(u8 addr)
void dp501_powerup(u8 addr)
{
dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */
+ dp501_setbits(addr, 0x0a, 0x0e); /* block HDCP and MCCS on I2C bride*/
i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */
dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */
dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 868813f..ec3145f 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -199,9 +199,10 @@
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-/* Probing DP501 I2C-Bridge will hang */
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x30}, {0, 0x37}, {0, 0x3a}, \
- {0, 0x3b}, {0, 0x50} }
+
+#ifndef CONFIG_TRAILBLAZER
+#define CONFIG_CMD_I2C
+#endif
#define CONFIG_PCA9698 /* NXP PCA9698 */
--
1.8.3
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [PATCH v2 09/13] board: gdsys: Make gdsys osd hardware detection more robust
2014-07-02 7:31 [U-Boot] [PATCH v2 0/13] Fixes on gdsys boards and some new functionality dirk.eibach at gdsys.cc
` (7 preceding siblings ...)
2014-07-02 7:31 ` [U-Boot] [PATCH v2 08/13] board: gdsys: Configure bridge on DP501 to support DDC only dirk.eibach at gdsys.cc
@ 2014-07-02 7:31 ` dirk.eibach at gdsys.cc
2014-07-02 7:31 ` [U-Boot] [PATCH v2 10/13] board: gdsys: Enable scrambling on DP501 dirk.eibach at gdsys.cc
` (3 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: dirk.eibach at gdsys.cc @ 2014-07-02 7:31 UTC (permalink / raw)
To: u-boot
From: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
---
Changes in v2: None
board/gdsys/405ep/iocon.c | 17 ++-----
board/gdsys/common/osd.c | 113 +++++++++++++++++++++++++++--------------
drivers/i2c/ihs_i2c.c | 1 -
include/configs/dlvision-10g.h | 2 -
include/configs/iocon.h | 6 ---
5 files changed, 79 insertions(+), 60 deletions(-)
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index 079dfb2..6ae15e1 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -15,7 +15,6 @@
#include "405ep.h"
#include <gdsys_fpga.h>
-#include "../common/dp501.h"
#include "../common/osd.h"
#include "../common/mclink.h"
@@ -99,8 +98,6 @@ enum {
unsigned int mclink_fpgacount;
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
-int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
-
static int setup_88e1518(const char *bus, unsigned char addr);
int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
@@ -374,20 +371,16 @@ int last_stage_init(void)
u16 fpga_features;
int feature_carrier_speed = fpga_features & (1<<4);
bool ch0_rgmii2_present = false;
- int old_bus = i2c_get_bus_num();
FPGA_GET_REG(0, fpga_features, &fpga_features);
- /* Turn on Parade DP501 */
- pca9698_direction_output(0x20, 9, 1);
- udelay(500000);
-
- i2c_set_bus_num(dp501_i2c[0]);
- dp501_powerup(0x08);
- i2c_set_bus_num(old_bus);
+ if (!legacy) {
+ /* Turn on Parade DP501 */
+ pca9698_direction_output(0x20, 9, 1);
+ udelay(500000);
- if (!legacy)
ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
+ }
print_fpga_info(0, ch0_rgmii2_present);
osd_probe(0);
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index a839a4e..1c765e4 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -9,6 +9,7 @@
#include <i2c.h>
#include <malloc.h>
+#include "dp501.h"
#include <gdsys_fpga.h>
#define CH7301_I2C_ADDR 0x75
@@ -24,6 +25,8 @@
#define SIL1178_MASTER_I2C_ADDRESS 0x38
#define SIL1178_SLAVE_I2C_ADDRESS 0x39
+#define DP501_I2C_ADDR 0x08
+
#define PIXCLK_640_480_60 25180000
enum {
@@ -54,18 +57,23 @@ u16 *buf;
unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1;
-#ifdef CONFIG_SYS_CH7301
-int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
+int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
#endif
-#ifdef CONFIG_SYS_ICS8N3QV01
-int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
+#ifdef CONFIG_SYS_CH7301_I2C
+int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
#endif
-#ifdef CONFIG_SYS_SIL1178
+#ifdef CONFIG_SYS_SIL1178_I2C
int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
#endif
+#ifdef CONFIG_SYS_DP501_I2C
+int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
+#endif
+
+
#ifdef CONFIG_SYS_MPC92469AC
static void mpc92469ac_calc_parameters(unsigned int fout,
unsigned int *post_div, unsigned int *feedback_div)
@@ -118,7 +126,7 @@ static void mpc92469ac_set(unsigned screen, unsigned int fout)
}
#endif
-#ifdef CONFIG_SYS_ICS8N3QV01
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
static unsigned int ics8n3qv01_get_fout_calc(unsigned index)
{
@@ -283,6 +291,8 @@ int osd_probe(unsigned screen)
u16 features;
u8 value;
int old_bus = i2c_get_bus_num();
+ bool pixclock_present = false;
+ bool output_driver_present = false;
FPGA_GET_REG(0, osd.version, &version);
FPGA_GET_REG(0, osd.features, &features);
@@ -297,51 +307,76 @@ int osd_probe(unsigned screen)
printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
screen, version/100, version%100, base_width, base_height);
-#ifdef CONFIG_SYS_CH7301
- i2c_set_bus_num(ch7301_i2c[screen]);
- value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
- if (value != 0x17) {
- printf(" Probing CH7301 failed, DID %02x\n", value);
- i2c_set_bus_num(old_bus);
- return -1;
- }
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
-#endif
+ /* setup pixclock */
#ifdef CONFIG_SYS_MPC92469AC
+ pixclock_present = true;
mpc92469ac_set(screen, PIXCLK_640_480_60);
#endif
-#ifdef CONFIG_SYS_ICS8N3QV01
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
i2c_set_bus_num(ics8n3qv01_i2c[screen]);
- ics8n3qv01_set(PIXCLK_640_480_60);
+ if (!i2c_probe(ICS8N3QV01_I2C_ADDR)) {
+ ics8n3qv01_set(PIXCLK_640_480_60);
+ pixclock_present = true;
+ }
#endif
-#ifdef CONFIG_SYS_SIL1178
+ if (!pixclock_present)
+ printf(" no pixelclock found\n");
+
+ /* setup output driver */
+
+#ifdef CONFIG_SYS_CH7301_I2C
+ i2c_set_bus_num(ch7301_i2c[screen]);
+ if (!i2c_probe(CH7301_I2C_ADDR)) {
+ value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
+ if (value == 0x17) {
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
+ output_driver_present = true;
+ }
+ }
+#endif
+
+#ifdef CONFIG_SYS_SIL1178_I2C
i2c_set_bus_num(sil1178_i2c[screen]);
- value = i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02);
- if (value != 0x06) {
- printf(" Probing SIL1178, DEV_IDL %02x\n", value);
- i2c_set_bus_num(old_bus);
- return -1;
+ if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) {
+ value = i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02);
+ if (value == 0x06) {
+ /*
+ * magic initialization sequence,
+ * adapted from datasheet
+ */
+ i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
+ output_driver_present = true;
+ }
+ }
+#endif
+
+#ifdef CONFIG_SYS_DP501_I2C
+ i2c_set_bus_num(dp501_i2c[screen]);
+ if (!i2c_probe(DP501_I2C_ADDR)) {
+ dp501_powerup(DP501_I2C_ADDR);
+ output_driver_present = true;
}
- /* magic initialization sequence adapted from datasheet */
- i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
- i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
- i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
- i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
- i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
- i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
- i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
- i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
- i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
- i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
#endif
+ if (!output_driver_present)
+ printf(" no output driver found\n");
+
FPGA_SET_REG(screen, osd.control, 0x0049);
FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1));
diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c
index ecc5856..fe66ce2 100644
--- a/drivers/i2c/ihs_i2c.c
+++ b/drivers/i2c/ihs_i2c.c
@@ -34,7 +34,6 @@ static int wait_for_int(bool read)
| (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
udelay(10);
if (ctr++ > 5000) {
- printf("I2C timeout\n");
return 1;
}
FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index c2289ce..08ab5c3 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -121,9 +121,7 @@
{ 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
#define CONFIG_DTT_TACH_LIMIT 0xa10
-#define CONFIG_SYS_ICS8N3QV01
#define CONFIG_SYS_ICS8N3QV01_I2C {0, 1}
-#define CONFIG_SYS_SIL1178
#define CONFIG_SYS_SIL1178_I2C {0, 1}
/* EBC peripherals */
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 1aebab3..1836d12 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -167,11 +167,6 @@ int fpga_gpio_get(unsigned int bus, int pin);
#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
/*
- * OSD hardware
- */
-#define CONFIG_SYS_MPC92469AC
-
-/*
* FLASH organization
*/
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
@@ -298,7 +293,6 @@ int fpga_gpio_get(unsigned int bus, int pin);
/*
* OSD Setup
*/
-#define CONFIG_SYS_ICS8N3QV01
#define CONFIG_SYS_MPC92469AC
#define CONFIG_SYS_OSD_SCREENS 1
#define CONFIG_SYS_DP501_DIFFERENTIAL
--
1.8.3
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [PATCH v2 10/13] board: gdsys: Enable scrambling on DP501
2014-07-02 7:31 [U-Boot] [PATCH v2 0/13] Fixes on gdsys boards and some new functionality dirk.eibach at gdsys.cc
` (8 preceding siblings ...)
2014-07-02 7:31 ` [U-Boot] [PATCH v2 09/13] board: gdsys: Make gdsys osd hardware detection more robust dirk.eibach at gdsys.cc
@ 2014-07-02 7:31 ` dirk.eibach at gdsys.cc
2014-07-02 7:31 ` [U-Boot] [PATCH v2 11/13] board: iocon: Modify iocon hardware startup dirk.eibach at gdsys.cc
` (2 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: dirk.eibach at gdsys.cc @ 2014-07-02 7:31 UTC (permalink / raw)
To: u-boot
From: Dirk Eibach <dirk.eibach@gdsys.cc>
For proper displayport performance, scrambling has to be enabled, but
is turned off on DP501 by default.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
---
Changes in v2: None
board/gdsys/common/dp501.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c
index 7958bae..7eb15ed 100644
--- a/board/gdsys/common/dp501.c
+++ b/board/gdsys/common/dp501.c
@@ -61,6 +61,7 @@ void dp501_powerup(u8 addr)
i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */
dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */
dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */
+ dp501_clrbits(addr, 0x60, 0x20); /* Enable scrambling */
#ifdef CONFIG_SYS_DP501_VCAPCTRL0
i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0);
--
1.8.3
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [PATCH v2 11/13] board: iocon: Modify iocon hardware startup
2014-07-02 7:31 [U-Boot] [PATCH v2 0/13] Fixes on gdsys boards and some new functionality dirk.eibach at gdsys.cc
` (9 preceding siblings ...)
2014-07-02 7:31 ` [U-Boot] [PATCH v2 10/13] board: gdsys: Enable scrambling on DP501 dirk.eibach at gdsys.cc
@ 2014-07-02 7:31 ` dirk.eibach at gdsys.cc
2014-07-02 7:31 ` [U-Boot] [PATCH v2 12/13] board: gdsys: Remove commands to reduce footprint dirk.eibach at gdsys.cc
2014-07-02 7:31 ` [U-Boot] [PATCH v2 13/13] fit: make sha256 support optional dirk.eibach at gdsys.cc
12 siblings, 0 replies; 15+ messages in thread
From: dirk.eibach at gdsys.cc @ 2014-07-02 7:31 UTC (permalink / raw)
To: u-boot
From: Dirk Eibach <dirk.eibach@gdsys.cc>
To avoid peer "ChReceivePathStatus"-messages on iocon startup, initialize
PHYs as soon as possible.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
---
Changes in v2: None
board/gdsys/405ep/iocon.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index 6ae15e1..1bac970 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -377,14 +377,10 @@ int last_stage_init(void)
if (!legacy) {
/* Turn on Parade DP501 */
pca9698_direction_output(0x20, 9, 1);
- udelay(500000);
ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
}
- print_fpga_info(0, ch0_rgmii2_present);
- osd_probe(0);
-
/* wait for FPGA done */
for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
unsigned int ctr = 0;
@@ -413,13 +409,16 @@ int last_stage_init(void)
}
}
- /* wait for slave-PLLs to be up and running */
+ /* give slave-PLLs and Parade DP501 some time to be up and running */
udelay(500000);
mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
slaves = mclink_probe();
mclink_fpgacount = 0;
+ print_fpga_info(0, ch0_rgmii2_present);
+ osd_probe(0);
+
if (slaves <= 0)
return 0;
--
1.8.3
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [PATCH v2 12/13] board: gdsys: Remove commands to reduce footprint
2014-07-02 7:31 [U-Boot] [PATCH v2 0/13] Fixes on gdsys boards and some new functionality dirk.eibach at gdsys.cc
` (10 preceding siblings ...)
2014-07-02 7:31 ` [U-Boot] [PATCH v2 11/13] board: iocon: Modify iocon hardware startup dirk.eibach at gdsys.cc
@ 2014-07-02 7:31 ` dirk.eibach at gdsys.cc
2014-07-02 7:31 ` [U-Boot] [PATCH v2 13/13] fit: make sha256 support optional dirk.eibach at gdsys.cc
12 siblings, 0 replies; 15+ messages in thread
From: dirk.eibach at gdsys.cc @ 2014-07-02 7:31 UTC (permalink / raw)
To: u-boot
From: Dirk Eibach <dirk.eibach@gdsys.cc>
Commit "2842c1c fit: add sha256 support" badly increased
memory footprint, so some of our boards did not build anymore.
Since monitor base must not be changed I removed some commands
to save memory.
Maybe making sha256 optional for fit would be an option for
the future since it really has some beefy footprint.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
---
Changes in v2: None
include/configs/dlvision-10g.h | 7 ++++++-
include/configs/io.h | 7 ++++++-
include/configs/iocon.h | 4 ++++
include/configs/neo.h | 8 ++++++--
4 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 08ab5c3..2567a22 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -64,9 +64,14 @@
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DTT
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_DIAG
#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_IRQ
+#undef CONFIG_CMD_NFS
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
diff --git a/include/configs/io.h b/include/configs/io.h
index 9da6cc6..649c0fb 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -64,9 +64,14 @@
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DTT
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_DIAG
#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_IRQ
+#undef CONFIG_CMD_NFS
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 1836d12..35ba1bd 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -64,6 +64,10 @@
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_FPGAD
#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_IRQ
+#undef CONFIG_CMD_NFS
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
diff --git a/include/configs/neo.h b/include/configs/neo.h
index d549985..75dc862 100644
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -61,10 +61,14 @@
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DATE
#define CONFIG_CMD_DTT
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_DIAG
#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_IRQ
+#undef CONFIG_CMD_NFS
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
--
1.8.3
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [PATCH v2 13/13] fit: make sha256 support optional
2014-07-02 7:31 [U-Boot] [PATCH v2 0/13] Fixes on gdsys boards and some new functionality dirk.eibach at gdsys.cc
` (11 preceding siblings ...)
2014-07-02 7:31 ` [U-Boot] [PATCH v2 12/13] board: gdsys: Remove commands to reduce footprint dirk.eibach at gdsys.cc
@ 2014-07-02 7:31 ` dirk.eibach at gdsys.cc
12 siblings, 0 replies; 15+ messages in thread
From: dirk.eibach at gdsys.cc @ 2014-07-02 7:31 UTC (permalink / raw)
To: u-boot
From: Dirk Eibach <dirk.eibach@gdsys.cc>
sha256 has some beefy memory footprint.
Make it optional for constrained systems.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
---
Changes in v2:
- make sha256 support optional
include/configs/dlvision-10g.h | 1 +
include/configs/io.h | 1 +
include/configs/iocon.h | 1 +
include/configs/neo.h | 1 +
include/image.h | 5 +++++
5 files changed, 9 insertions(+)
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 2567a22..6153a40 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -40,6 +40,7 @@
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
diff --git a/include/configs/io.h b/include/configs/io.h
index 649c0fb..8e32c25 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -40,6 +40,7 @@
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 35ba1bd..ae05bcb 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -39,6 +39,7 @@
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
diff --git a/include/configs/neo.h b/include/configs/neo.h
index 75dc862..4937730 100644
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -37,6 +37,7 @@
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
diff --git a/include/image.h b/include/image.h
index b71e4ba..61d5885 100644
--- a/include/image.h
+++ b/include/image.h
@@ -72,6 +72,11 @@ struct lmb;
# define IMAGE_ENABLE_SHA256 1
# endif
+#ifdef CONFIG_FIT_DISABLE_SHA256
+#undef CONFIG_SHA256
+#undef IMAGE_ENABLE_SHA256
+#endif
+
#ifndef IMAGE_ENABLE_CRC32
#define IMAGE_ENABLE_CRC32 0
#endif
--
1.8.3
^ permalink raw reply related [flat|nested] 15+ messages in thread