[U-Boot] [PATCH 3/4] ARM: LS1021A: enable ARMv7 virt support for LS1021A A7

Diana Craciun
2014-07-03T11:43:33Z

On 07/03/2014 12:51 PM, Xiubo Li wrote:
> To enable hypervisors utilizing the ARMv7 virtualization extension
> on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
> required configuration variable.
> Also we define the board specific smp_set_cpu_boot_addr() function to
> set the start address for secondary cores in the LS1021A specific
> manner.
>
> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
> ---
> arch/arm/cpu/armv7/ls102xa/cpu.c | 12 ++++++++++++
> include/configs/ls1021aqds.h | 9 +++++++++
> include/configs/ls1021atwr.h | 9 +++++++++
> 3 files changed, 30 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
> index f9046c6..2268f15 100644
> --- a/arch/arm/cpu/armv7/ls102xa/cpu.c
> +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
> @@ -101,3 +101,15 @@ int cpu_eth_init(bd_t *bis)
>
> return 0;
> }
> +
> +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
> +/* Setting the address at which secondary cores start from.*/
> +void smp_set_core_boot_addr(unsigned long addr, int corenr)
> +{
> + /* After setting the secondary cores start address, just release
> + * them to boot.
> + */
> + out_be32(CONFIG_DCFG_CCSR_SCRATCHRW1, addr);
> + out_be32(CONFIG_DCFG_CCSR_BRR, 0x2);
> +}
> +#endif
> diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
> index d639a6f..f090971 100644
> --- a/include/configs/ls1021aqds.h
> +++ b/include/configs/ls1021aqds.h
> @@ -18,6 +18,15 @@
> #define CONFIG_BOARD_EARLY_INIT_F
> #define CONFIG_ARCH_EARLY_INIT_R
>
> +#define CONFIG_ARMV7_NONSEC
> +#define CONFIG_ARMV7_VIRT
> +#define CONFIG_SOC_BIG_ENDIAN
> +#define CONFIG_DCFG_CCSR_SCRATCHRW1 0x01ee0200
> +#define CONFIG_DCFG_CCSR_BRR 0x01ee00e4

Why are you hardcoding the register addresses in this file? I saw that
all registers are defined in:
arch/arm/include/asm/arch-ls102xa/config.h. Why are these special?

> +#define CONFIG_SMP_PEN_ADDR CONFIG_DCFG_CCSR_SCRATCHRW1
> +#define CONFIG_ARM_GIC_BASE_ADDRESS 0x01400000

Why do you need the GIC base address? Can't this be read from CBAR?

> +#define CONFIG_TIMER_CLK_FREQ 125000000
> +
> #define CONFIG_HWCONFIG
> #define HWCONFIG_BUFFER_SIZE 128
>
> diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
> index a8dc56e..235a862 100644
> --- a/include/configs/ls1021atwr.h
> +++ b/include/configs/ls1021atwr.h
> @@ -18,6 +18,15 @@
> #define CONFIG_BOARD_EARLY_INIT_F
> #define CONFIG_ARCH_EARLY_INIT_R
>
> +#define CONFIG_ARMV7_NONSEC
> +#define CONFIG_ARMV7_VIRT
> +#define CONFIG_SOC_BIG_ENDIAN
> +#define CONFIG_DCFG_CCSR_SCRATCHRW1 0x01ee0200
> +#define CONFIG_DCFG_CCSR_BRR 0x01ee00e4
> +#define CONFIG_SMP_PEN_ADDR CONFIG_DCFG_CCSR_SCRATCHRW1
> +#define CONFIG_ARM_GIC_BASE_ADDRESS 0x01400000
> +#define CONFIG_TIMER_CLK_FREQ 125000000
> +
> #define CONFIG_HWCONFIG
> #define HWCONFIG_BUFFER_SIZE 128
>