From mboxrd@z Thu Jan 1 00:00:00 1970 From: Diana Craciun Date: Thu, 3 Jul 2014 14:58:27 +0300 Subject: [U-Boot] [PATCH 4/4] ARM: LS1021A: to allow non-secure R/W access for all devices' mapped region In-Reply-To: <1404381072-42875-5-git-send-email-Li.Xiubo@freescale.com> References: <1404381072-42875-1-git-send-email-Li.Xiubo@freescale.com> <1404381072-42875-5-git-send-email-Li.Xiubo@freescale.com> Message-ID: <53B54563.4090205@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 07/03/2014 12:51 PM, Xiubo Li wrote: > Signed-off-by: Xiubo Li > --- > arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 98 +++++++++++++++++-- > board/freescale/ls1021aqds/ls1021aqds.c | 110 +++++++++++++++++++-- > board/freescale/ls1021atwr/ls1021atwr.c | 111 ++++++++++++++++++++-- > 3 files changed, 298 insertions(+), 21 deletions(-) > > diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h > index 192d389..b959bf5 100644 > --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h > +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h > @@ -34,14 +34,98 @@ > #define FSL_LS102xA_DEVDISR3_PCIE1 0x80000000 > #define FSL_LS102xA_DEVDISR3_PCIE2 0x40000000 > > -/* CSU CSL2 register offset */ > -#define CSU_CSL2_IFC_REG_OFFSET 0x4 > -/* Mask of Non secure read/write access in CSU_CL registers */ > -#define CSU_CSL2x_NS_SUP_WRITE_ACCESS 0x00000080 > -#define CSU_CSL2x_NS_USER_WRITE_ACCESS 0x00000040 > -#define CSU_CSL2x_NS_SUP_READ_ACCESS 0x00000008 > -#define CSU_CSL2x_NS_USER_READ_ACCESS 0x00000004 > +enum csu_cslx_access { > + CSU_NS_SUP_R = 0x08, > + CSU_NS_SUP_W = 0x80, > + CSU_NS_SUP_RW = 0x88, > + CSU_NS_USER_R = 0x04, > + CSU_NS_USER_W = 0x40, > + CSU_NS_USER_RW = 0x44, > +}; > > +enum csu_cslx_ind { > + CSU_CSLX_PCIE2_IO = 0, > + CSU_CSLX_PCIE1_IO, > + CSU_CSLX_MG2TPR_IP, > + CSU_CSLX_IFC_MEM, > + CSU_CSLX_OCRAM, > + CSU_CSLX_GIC, > + CSU_CSLX_PCIE1, > + CSU_CSLX_OCRAM2, > + CSU_CSLX_QSPI_MEM, > + CSU_CSLX_PCIE2, > + CSU_CSLX_SATA, > + CSU_CSLX_USB3, > + CSU_CSLX_SERDES = 32, > + CSU_CSLX_QDMA, > + CSU_CSLX_LPUART2, > + CSU_CSLX_LPUART1, > + CSU_CSLX_LPUART4, > + CSU_CSLX_LPUART3, > + CSU_CSLX_LPUART6, > + CSU_CSLX_LPUART5, > + CSU_CSLX_DSPI2 = 40, > + CSU_CSLX_DSPI1, > + CSU_CSLX_QSPI, > + CSU_CSLX_ESDHC, > + CSU_CSLX_2D_ACE, > + CSU_CSLX_IFC, > + CSU_CSLX_I2C1, > + CSU_CSLX_USB2, > + CSU_CSLX_I2C3, > + CSU_CSLX_I2C2, > + CSU_CSLX_DUART2 = 50, > + CSU_CSLX_DUART1, > + CSU_CSLX_WDT2, > + CSU_CSLX_WDT1, > + CSU_CSLX_EDMA, > + CSU_CSLX_SYS_CNT, > + CSU_CSLX_DMA_MUX2, > + CSU_CSLX_DMA_MUX1, > + CSU_CSLX_DDR, > + CSU_CSLX_QUICC, > + CSU_CSLX_DCFG_CCU_RCPM = 60, > + CSU_CSLX_SECURE_BOOTROM, > + CSU_CSLX_SFP, > + CSU_CSLX_TMU, > + CSU_CSLX_SECURE_MONITOR, > + CSU_CSLX_RESERVED0, > + CSU_CSLX_ETSEC1, > + CSU_CSLX_SEC5_5, > + CSU_CSLX_ETSEC3, > + CSU_CSLX_ETSEC2, > + CSU_CSLX_GPIO2 = 70, > + CSU_CSLX_GPIO1, > + CSU_CSLX_GPIO4, > + CSU_CSLX_GPIO3, > + CSU_CSLX_PLATFORM_CONT, > + CSU_CSLX_CSU, > + CSU_CSLX_ASRC, > + CSU_CSLX_SPDIF, > + CSU_CSLX_FLEXCAN2, > + CSU_CSLX_FLEXCAN1, > + CSU_CSLX_FLEXCAN4 = 80, > + CSU_CSLX_FLEXCAN3, > + CSU_CSLX_SAI2, > + CSU_CSLX_SAI1, > + CSU_CSLX_SAI4, > + CSU_CSLX_SAI3, > + CSU_CSLX_FTM2, > + CSU_CSLX_FTM1, > + CSU_CSLX_FTM4, > + CSU_CSLX_FTM3, > + CSU_CSLX_FTM6 = 90, > + CSU_CSLX_FTM5, > + CSU_CSLX_FTM8, > + CSU_CSLX_FTM7, > + CSU_CSLX_COP_DCSR, > + CSU_CSLX_EPU, > + CSU_CSLX_GDI, > + CSU_CSLX_DDI, > + CSU_CSLX_RESERVED1, > + CSU_CSLX_USB3_PHY = 117, > + CSU_CSLX_RESERVED2, > +}; > /* > * Define default values for some CCSR macros to make header files cleaner* > * > diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c > index fe00421..7444e06 100644 > --- a/board/freescale/ls1021aqds/ls1021aqds.c > +++ b/board/freescale/ls1021aqds/ls1021aqds.c > @@ -377,15 +377,111 @@ int board_init(void) > return 0; > } > > +struct csu_ns_dev { > + unsigned long ind; > + uint32_t val; > +}; > > -void enable_ifc_ns_read_access(void) > +struct csu_ns_dev ns_dev[] = > { > - uint32_t *csu_csl2 = CONFIG_SYS_FSL_CSU_ADDR + CSU_CSL2_IFC_REG_OFFSET; > - uint32_t reg; > + CSU_CSLX_PCIE2_IO, CSU_NS_SUP_RW, > + CSU_CSLX_PCIE1_IO, CSU_NS_SUP_RW, > + CSU_CSLX_MG2TPR_IP, CSU_NS_SUP_RW, > + CSU_CSLX_IFC_MEM, CSU_NS_SUP_R | CSU_NS_USER_R, > + CSU_CSLX_OCRAM, CSU_NS_SUP_RW, > + CSU_CSLX_GIC, CSU_NS_SUP_RW, > + CSU_CSLX_PCIE1, CSU_NS_SUP_RW, > + CSU_CSLX_OCRAM2, CSU_NS_SUP_RW, > + CSU_CSLX_QSPI_MEM, CSU_NS_SUP_RW, > + CSU_CSLX_PCIE2, CSU_NS_SUP_RW, > + CSU_CSLX_SATA, CSU_NS_SUP_RW, > + CSU_CSLX_USB3, CSU_NS_SUP_RW, > + CSU_CSLX_SERDES, CSU_NS_SUP_RW, > + CSU_CSLX_QDMA, CSU_NS_SUP_RW, > + CSU_CSLX_LPUART2, CSU_NS_SUP_RW, > + CSU_CSLX_LPUART1, CSU_NS_SUP_RW, > + CSU_CSLX_LPUART4, CSU_NS_SUP_RW, > + CSU_CSLX_LPUART3, CSU_NS_SUP_RW, > + CSU_CSLX_LPUART6, CSU_NS_SUP_RW, > + CSU_CSLX_LPUART5, CSU_NS_SUP_RW, > + CSU_CSLX_DSPI2, CSU_NS_SUP_RW, > + CSU_CSLX_DSPI1, CSU_NS_SUP_RW, > + CSU_CSLX_QSPI, CSU_NS_SUP_RW, > + CSU_CSLX_ESDHC, CSU_NS_SUP_RW, > + CSU_CSLX_2D_ACE, CSU_NS_SUP_RW, > + CSU_CSLX_IFC, CSU_NS_SUP_RW, > + CSU_CSLX_I2C1, CSU_NS_SUP_RW, > + CSU_CSLX_USB2, CSU_NS_SUP_RW, > + CSU_CSLX_I2C3, CSU_NS_SUP_RW, > + CSU_CSLX_I2C2, CSU_NS_SUP_RW, > + CSU_CSLX_DUART2, CSU_NS_SUP_RW, > + CSU_CSLX_DUART1, CSU_NS_SUP_RW, > + CSU_CSLX_WDT2, CSU_NS_SUP_RW, > + CSU_CSLX_WDT1, CSU_NS_SUP_RW, > + CSU_CSLX_EDMA, CSU_NS_SUP_RW, > + CSU_CSLX_SYS_CNT, CSU_NS_SUP_RW, > + CSU_CSLX_DMA_MUX2, CSU_NS_SUP_RW, > + CSU_CSLX_DMA_MUX1, CSU_NS_SUP_RW, > + CSU_CSLX_DDR, CSU_NS_SUP_RW, > + CSU_CSLX_QUICC, CSU_NS_SUP_RW, > + CSU_CSLX_DCFG_CCU_RCPM, CSU_NS_SUP_RW, > + CSU_CSLX_SECURE_BOOTROM, CSU_NS_SUP_RW, > + CSU_CSLX_SFP, CSU_NS_SUP_RW, > + CSU_CSLX_TMU, CSU_NS_SUP_RW, > + CSU_CSLX_SECURE_MONITOR, CSU_NS_SUP_RW, > + CSU_CSLX_RESERVED0, CSU_NS_SUP_RW, > + CSU_CSLX_ETSEC1, CSU_NS_SUP_RW, > + CSU_CSLX_SEC5_5, CSU_NS_SUP_RW, > + CSU_CSLX_ETSEC3, CSU_NS_SUP_RW, > + CSU_CSLX_ETSEC2, CSU_NS_SUP_RW, > + CSU_CSLX_GPIO2, CSU_NS_SUP_RW, > + CSU_CSLX_GPIO1, CSU_NS_SUP_RW, > + CSU_CSLX_GPIO4, CSU_NS_SUP_RW, > + CSU_CSLX_GPIO3, CSU_NS_SUP_RW, > + CSU_CSLX_PLATFORM_CONT, CSU_NS_SUP_RW, > + CSU_CSLX_CSU, CSU_NS_SUP_RW, > + CSU_CSLX_ASRC, CSU_NS_SUP_RW, > + CSU_CSLX_SPDIF, CSU_NS_SUP_RW, > + CSU_CSLX_FLEXCAN2, CSU_NS_SUP_RW, > + CSU_CSLX_FLEXCAN1, CSU_NS_SUP_RW, > + CSU_CSLX_FLEXCAN4, CSU_NS_SUP_RW, > + CSU_CSLX_FLEXCAN3, CSU_NS_SUP_RW, > + CSU_CSLX_SAI2, CSU_NS_SUP_RW, > + CSU_CSLX_SAI1, CSU_NS_SUP_RW, > + CSU_CSLX_SAI4, CSU_NS_SUP_RW, > + CSU_CSLX_SAI3, CSU_NS_SUP_RW, > + CSU_CSLX_FTM2, CSU_NS_SUP_RW, > + CSU_CSLX_FTM1, CSU_NS_SUP_RW, > + CSU_CSLX_FTM4, CSU_NS_SUP_RW, > + CSU_CSLX_FTM3, CSU_NS_SUP_RW, > + CSU_CSLX_FTM6, CSU_NS_SUP_RW, > + CSU_CSLX_FTM5, CSU_NS_SUP_RW, > + CSU_CSLX_FTM8, CSU_NS_SUP_RW, > + CSU_CSLX_FTM7, CSU_NS_SUP_RW, > + CSU_CSLX_COP_DCSR, CSU_NS_SUP_RW, > + CSU_CSLX_EPU, CSU_NS_SUP_RW, > + CSU_CSLX_GDI, CSU_NS_SUP_RW, > + CSU_CSLX_DDI, CSU_NS_SUP_RW, > + CSU_CSLX_RESERVED1, CSU_NS_SUP_RW, > + CSU_CSLX_USB3_PHY, CSU_NS_SUP_RW, > + CSU_CSLX_RESERVED2, CSU_NS_SUP_RW, > +}; > > - reg = in_be32(csu_csl2); > - out_be32(csu_csl2, reg | CSU_CSL2x_NS_SUP_READ_ACCESS | > - CSU_CSL2x_NS_USER_READ_ACCESS); > +void enable_devices_ns_access(void) > +{ > + uint32_t *csu_csl; > + uint32_t reg; > + int i; > + > + for (i = 0; i < ARRAY_SIZE(ns_dev); i++) { > + csu_csl = CONFIG_SYS_FSL_CSU_ADDR + ns_dev[i].ind / 2 * 4; > + reg = in_be32(csu_csl); > + if (ns_dev[i].ind % 2 == 0) > + reg |= ns_dev[i].val << 16; > + else > + reg |= ns_dev[i].val; > + out_be32(csu_csl, reg); > + } > } > > int board_late_init(void) > @@ -403,7 +499,7 @@ int board_late_init(void) > > ahci_init(AHCI_BASE_ADDR); > scsi_scan(1); > - enable_ifc_ns_read_access(); > + enable_devices_ns_access(); > return 0; > } > > diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c > index d57fa77..f75b779 100644 > --- a/board/freescale/ls1021atwr/ls1021atwr.c > +++ b/board/freescale/ls1021atwr/ls1021atwr.c > @@ -458,14 +458,111 @@ int board_init(void) > return 0; > } > > -void enable_ifc_ns_read_access(void) > +struct csu_ns_dev { > + unsigned long ind; > + uint32_t val; > +}; > + > +struct csu_ns_dev ns_dev[] = > { > - uint32_t *csu_csl2 = CONFIG_SYS_FSL_CSU_ADDR + CSU_CSL2_IFC_REG_OFFSET; > - uint32_t reg; > + CSU_CSLX_PCIE2_IO, CSU_NS_SUP_RW, > + CSU_CSLX_PCIE1_IO, CSU_NS_SUP_RW, > + CSU_CSLX_MG2TPR_IP, CSU_NS_SUP_RW, > + CSU_CSLX_IFC_MEM, CSU_NS_SUP_R | CSU_NS_USER_R, > + CSU_CSLX_OCRAM, CSU_NS_SUP_RW, > + CSU_CSLX_GIC, CSU_NS_SUP_RW, > + CSU_CSLX_PCIE1, CSU_NS_SUP_RW, > + CSU_CSLX_OCRAM2, CSU_NS_SUP_RW, > + CSU_CSLX_QSPI_MEM, CSU_NS_SUP_RW, > + CSU_CSLX_PCIE2, CSU_NS_SUP_RW, > + CSU_CSLX_SATA, CSU_NS_SUP_RW, > + CSU_CSLX_USB3, CSU_NS_SUP_RW, > + CSU_CSLX_SERDES, CSU_NS_SUP_RW, > + CSU_CSLX_QDMA, CSU_NS_SUP_RW, > + CSU_CSLX_LPUART2, CSU_NS_SUP_RW, > + CSU_CSLX_LPUART1, CSU_NS_SUP_RW, > + CSU_CSLX_LPUART4, CSU_NS_SUP_RW, > + CSU_CSLX_LPUART3, CSU_NS_SUP_RW, > + CSU_CSLX_LPUART6, CSU_NS_SUP_RW, > + CSU_CSLX_LPUART5, CSU_NS_SUP_RW, > + CSU_CSLX_DSPI2, CSU_NS_SUP_RW, > + CSU_CSLX_DSPI1, CSU_NS_SUP_RW, > + CSU_CSLX_QSPI, CSU_NS_SUP_RW, > + CSU_CSLX_ESDHC, CSU_NS_SUP_RW, > + CSU_CSLX_2D_ACE, CSU_NS_SUP_RW, > + CSU_CSLX_IFC, CSU_NS_SUP_RW, > + CSU_CSLX_I2C1, CSU_NS_SUP_RW, > + CSU_CSLX_USB2, CSU_NS_SUP_RW, > + CSU_CSLX_I2C3, CSU_NS_SUP_RW, > + CSU_CSLX_I2C2, CSU_NS_SUP_RW, > + CSU_CSLX_DUART2, CSU_NS_SUP_RW, > + CSU_CSLX_DUART1, CSU_NS_SUP_RW, > + CSU_CSLX_WDT2, CSU_NS_SUP_RW, > + CSU_CSLX_WDT1, CSU_NS_SUP_RW, > + CSU_CSLX_EDMA, CSU_NS_SUP_RW, > + CSU_CSLX_SYS_CNT, CSU_NS_SUP_RW, > + CSU_CSLX_DMA_MUX2, CSU_NS_SUP_RW, > + CSU_CSLX_DMA_MUX1, CSU_NS_SUP_RW, > + CSU_CSLX_DDR, CSU_NS_SUP_RW, > + CSU_CSLX_QUICC, CSU_NS_SUP_RW, > + CSU_CSLX_DCFG_CCU_RCPM, CSU_NS_SUP_RW, > + CSU_CSLX_SECURE_BOOTROM, CSU_NS_SUP_RW, > + CSU_CSLX_SFP, CSU_NS_SUP_RW, > + CSU_CSLX_TMU, CSU_NS_SUP_RW, > + CSU_CSLX_SECURE_MONITOR, CSU_NS_SUP_RW, > + CSU_CSLX_RESERVED0, CSU_NS_SUP_RW, > + CSU_CSLX_ETSEC1, CSU_NS_SUP_RW, > + CSU_CSLX_SEC5_5, CSU_NS_SUP_RW, > + CSU_CSLX_ETSEC3, CSU_NS_SUP_RW, > + CSU_CSLX_ETSEC2, CSU_NS_SUP_RW, > + CSU_CSLX_GPIO2, CSU_NS_SUP_RW, > + CSU_CSLX_GPIO1, CSU_NS_SUP_RW, > + CSU_CSLX_GPIO4, CSU_NS_SUP_RW, > + CSU_CSLX_GPIO3, CSU_NS_SUP_RW, > + CSU_CSLX_PLATFORM_CONT, CSU_NS_SUP_RW, > + CSU_CSLX_CSU, CSU_NS_SUP_RW, > + CSU_CSLX_ASRC, CSU_NS_SUP_RW, > + CSU_CSLX_SPDIF, CSU_NS_SUP_RW, > + CSU_CSLX_FLEXCAN2, CSU_NS_SUP_RW, > + CSU_CSLX_FLEXCAN1, CSU_NS_SUP_RW, > + CSU_CSLX_FLEXCAN4, CSU_NS_SUP_RW, > + CSU_CSLX_FLEXCAN3, CSU_NS_SUP_RW, > + CSU_CSLX_SAI2, CSU_NS_SUP_RW, > + CSU_CSLX_SAI1, CSU_NS_SUP_RW, > + CSU_CSLX_SAI4, CSU_NS_SUP_RW, > + CSU_CSLX_SAI3, CSU_NS_SUP_RW, > + CSU_CSLX_FTM2, CSU_NS_SUP_RW, > + CSU_CSLX_FTM1, CSU_NS_SUP_RW, > + CSU_CSLX_FTM4, CSU_NS_SUP_RW, > + CSU_CSLX_FTM3, CSU_NS_SUP_RW, > + CSU_CSLX_FTM6, CSU_NS_SUP_RW, > + CSU_CSLX_FTM5, CSU_NS_SUP_RW, > + CSU_CSLX_FTM8, CSU_NS_SUP_RW, > + CSU_CSLX_FTM7, CSU_NS_SUP_RW, > + CSU_CSLX_COP_DCSR, CSU_NS_SUP_RW, > + CSU_CSLX_EPU, CSU_NS_SUP_RW, > + CSU_CSLX_GDI, CSU_NS_SUP_RW, > + CSU_CSLX_DDI, CSU_NS_SUP_RW, > + CSU_CSLX_RESERVED1, CSU_NS_SUP_RW, > + CSU_CSLX_USB3_PHY, CSU_NS_SUP_RW, > + CSU_CSLX_RESERVED2, CSU_NS_SUP_RW, > +}; > > - reg = in_be32(csu_csl2); > - out_be32(csu_csl2, reg | CSU_CSL2x_NS_SUP_READ_ACCESS | > - CSU_CSL2x_NS_USER_READ_ACCESS); > +void enable_devices_ns_access(void) This function is identical for twr and qds? Can't be just one in a common file? > +{ > + uint32_t *csu_csl; > + uint32_t reg; > + int i; > + > + for (i = 0; i < ARRAY_SIZE(ns_dev); i++) { > + csu_csl = CONFIG_SYS_FSL_CSU_ADDR + ns_dev[i].ind / 2 * 4; > + reg = in_be32(csu_csl); > + if (ns_dev[i].ind % 2 == 0) > + reg |= ns_dev[i].val << 16; > + else > + reg |= ns_dev[i].val; > + out_be32(csu_csl, reg); > + } > } > > int board_late_init(void) > @@ -483,7 +580,7 @@ int board_late_init(void) > > ahci_init(AHCI_BASE_ADDR); > scsi_scan(1); > - enable_ifc_ns_read_access(); > + enable_devices_ns_access(); > return 0; > } Diana Craciun >