From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Mon, 21 Jul 2014 14:06:46 -0700 Subject: [U-Boot] [PATCH v2 01/10] arm: ls102xa: Add Freescale LS102xA SoC support In-Reply-To: <1404372264-2301-2-git-send-email-b18965@freescale.com> References: <1404372264-2301-1-git-send-email-b18965@freescale.com> <1404372264-2301-2-git-send-email-b18965@freescale.com> Message-ID: <53CD80E6.3010709@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 07/03/2014 12:24 AM, Alison Wang wrote: > The QorIQ LS1 family is built on Layerscape architecture, > the industry's first software-aware, core-agnostic networking > architecture to offer unprecedented efficiency and scale. > > Freescale LS102xA is a set of SoCs combines two ARM > Cortex-A7 cores that have been optimized for high > reliability and pack the highest level of integration > available for sub-3 W embedded communications processors > with Layerscape architecture and with a comprehensive > enablement model focused on ease of programmability. > > Signed-off-by: Alison Wang > Signed-off-by: Jason Jin > Signed-off-by: Jingchang Lu > Signed-off-by: Prabhakar Kushwaha > --- > Change log: > v2: Add serdes support. > Update DDR frequency and data rate information. > Fix overflow condition error for the timer. > Albert, As you can see, Freescale starts to make ARM core SoCs on QorIQ product line. As previously discussed, I will maintain fsl-qoriq repository to host these patches. Beside ARMv8, I am new to ARM cores. To start, I would like to solicit your comments/ack for this series. It will be helpful if you can share how ARM maintainers do the daily jobs like sending notice, pull requests, etc. York