From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jaehoon Chung Date: Tue, 22 Jul 2014 12:22:53 +0900 Subject: [U-Boot] socfpga: initialize MMC In-Reply-To: <20140716123422.GA8844@amd.pavel.ucw.cz> References: <20140716123422.GA8844@amd.pavel.ucw.cz> Message-ID: <53CDD90D.7080704@samsung.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi, I don't know what differ with socfpga_dw_mmc.c. I think you can use it. Best Regards, Jaehoon Chung On 07/16/2014 09:34 PM, Pavel Machek wrote: > Hi! > > Once ethernet changes I merged, I can rediff mmc changes for > application. It will look something like this: > > Albert, can you apply the ethernet patch? I'd like to continue on top > of it... > Pavel > > diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c > index 2f1c716..7af384e 100644 > --- a/arch/arm/cpu/armv7/socfpga/misc.c > +++ b/arch/arm/cpu/armv7/socfpga/misc.c > @@ -14,3 +16,27 @@ int dram_init(void) > + > +#ifdef CONFIG_DWMMC > +/* > + * Initializes MMC controllers. > + * to override, implement board_mmc_init() > + */ > +int cpu_mmc_init(bd_t *bis) > +{ > + return altera_dwmmc_init(SOCFPGA_SDMMC_ADDRESS, 4, 0); > +} > +#endif > diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h > index f564046..9b488d9 100644 > --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h > +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h > @@ -14,5 +14,8 @@ > #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 > #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 > #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 > +#define SOCFPGA_SDMMC_ADDRESS 0xff704000 > > #endif /* _SOCFPGA_BASE_ADDRS_H_ */ > diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile > index 34febf5..5902105 100644 > --- a/drivers/mmc/Makefile > +++ b/drivers/mmc/Makefile > @@ -28,6 +28,7 @@ obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o > obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o > obj-$(CONFIG_DWMMC) += dw_mmc.o > obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o > +obj-$(CONFIG_ALTERA_DWMMC) += altera_dw_mmc.o > obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o > obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o > obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o > diff --git a/drivers/mmc/altera_dw_mmc.c b/drivers/mmc/altera_dw_mmc.c > new file mode 100644 > index 0000000..b22dc45 > --- /dev/null > +++ b/drivers/mmc/altera_dw_mmc.c > @@ -0,0 +1,74 @@ > +/* > + * Copyright (C) 2013 Altera Corporation > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA > + * > + */ > + > +#include > +#include > +#include > +#include > +#include > + > +#define CLKMGR_PERPLLGRP_EN_REG (SOCFPGA_CLKMGR_ADDRESS + 0xA0) > +#define CLKMGR_SDMMC_CLK_ENABLE (1 << 8) > +#define SYSMGR_SDMMCGRP_CTRL_REG (SOCFPGA_SYSMGR_ADDRESS + 0x108) > + > +static char *ALTERA_NAME = "ALTERA DWMMC"; > + > +static void altera_dwmci_clksel(struct dwmci_host *host) > +{ > + unsigned int drvsel; > + unsigned int smplsel; > + > + /* Disable SDMMC clock. */ > + clrbits_le32(CLKMGR_PERPLLGRP_EN_REG, CLKMGR_SDMMC_CLK_ENABLE); > + > + /* Configures drv_sel and smpl_sel */ > + drvsel = 3; > + smplsel = 0; > + > + debug("%s: drvsel %d smplsel %d\n", __FUNCTION__, drvsel, smplsel); > + writel((smplsel << 3) | drvsel, SYSMGR_SDMMCGRP_CTRL_REG); > + > + /* Enable SDMMC clock */ > + setbits_le32(CLKMGR_PERPLLGRP_EN_REG, CLKMGR_SDMMC_CLK_ENABLE); > +} > + > +int altera_dwmmc_init(u32 regbase, int bus_width, int index) > +{ > + struct dwmci_host *host = NULL; > + host = malloc(sizeof(struct dwmci_host)); > + if (!host) { > + printf("dwmci_host malloc failed!\n"); > + return -ENOMEM; > + } > + > + host->name = ALTERA_NAME; > + host->ioaddr = (void *)regbase; > + host->buswidth = bus_width; > + host->clksel = altera_dwmci_clksel; > + host->dev_index = index; > + host->bus_hz = 400000; > + host->fifoth_val = MSIZE(0x2) | > + RX_WMARK(CONFIG_DWMMC_FIFO_DEPTH / 2 - 1) | > + TX_WMARK(CONFIG_DWMMC_FIFO_DEPTH / 2); > + > + add_dwmci(host, host->bus_hz, host->bus_hz); > + > + return 0; > +} > + > diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h > index 0254249..189dcde 100644 > --- a/include/configs/socfpga_cyclone5.h > +++ b/include/configs/socfpga_cyclone5.h > @@ -180,13 +183,30 @@ > /* > * FLASH > */ > #define CONFIG_SYS_NO_FLASH > > + > +/* > + * MMC support > + */ > +#define CONFIG_MMC > +#ifdef CONFIG_MMC > +#define CONFIG_CMD_MMC > + > +#define CONFIG_BOUNCE_BUFFER > +#define CONFIG_GENERIC_MMC 1 > +#define CONFIG_DWMMC 1 > +#define CONFIG_ALTERA_DWMMC 1 > +#define CONFIG_DWMMC_FIFO_DEPTH 1024 > +/* using smaller max blk cnt to avoid flooding the limited stack we have */ > +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 > +#endif /* CONFIG_MMC */ > + > /* > * L4 OSC1 Timer 0 > */ >