[U-Boot] ODROID dynamic memory initialization

[Przemyslaw Marczak <p.marczak@samsung.com>]

Hi Daniel,

On 07/23/2014 02:27 PM, Daniel Drake wrote:
> On Tue, Jul 22, 2014 at 2:08 PM, Daniel Drake <drake@endlessm.com> wrote:
>> While looking at the old uboot from hardkernel, I'm curious about
>> CONFIG_CLK_BUS_DMC_220_440, which is set by default. This appears to
>> run the memory at a high speed, by writing certain registers in the
>> Dynamic Memory Controller (e.g. TIMINGROW), and clocking MPLL to
>> 880MHz.
>>
>> Your uboot patches don't seem to touch DMC regs like TIMINGROW, and
>> also clock the MPLL at 800MHz.

I used my private config from trats2 device, but there is Exynos4412 
rev. 1.1 - DMC freq is 400MHz.
I need to check the 880Mhz value for the MPLL and I will give you an info.

>
> I looked in more detail, and now understand better the SPL vs uboot division.
>
> The vendor code I was referring to above is SPL code.
>
> Since we are still using the same SPL as before, it means that MPLL
> and memory is already set up by the time the real/new uboot loads.
>
> So I think there should be no need to modify MPLL, and I wonder if
> most of the other clock configuration code in your patches is also
> unnecessary.
>
> Thoughts?
>
> Thanks
> Daniel
>

The BL2 is not a part of this patches, then maybe better is to configure 
the clocks for proper values by u-boot, moreover when I
disable the clock configuration in u-boot then it can't boot - probably 
because of bad uart config and maybe some more.

Thank you for testing this code, but I don't have too much time for play 
with this config now.

I will test the MPLL with 880MHz tomorrow and it should be good enough, 
but next if dev freq will be enabled in the kernel - then probably DMC 
dividers will change without TIMINGROW change.

Thanks,
-- 
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com