[U-Boot] [PATCH 0/2] sunxi: Single u-boot binary for Allwinner A10/A13/A20 devices

[U-Boot] [PATCH 0/2] sunxi: Single u-boot binary for Allwinner A10/A13/A20 devices

[Siarhei Siamashka]

This patchset introduces the initial rudimentary support for having
just a single u-boot binary for certain subsets of Allwinner A10/A13/A20
devices.

== Example 1: All Allwinner A10/A13/A20 devices

We are restricted to only a very basic common subset of peripherals
(anything that is supported by BROM should be fine). This provides
a possibility to at least boot from the SD card and use some slow
fail-safe DRAM settings. UART, USB and HDMI settings are also
relatively easy to detect at runtime. This provides a possibility
to implement universal installers, which would somehow boot the
system and allow the user to change u-boot and dtb to something
more suitable for his hardware.

Advantages: just works everywhere
Disadvantages: poor performance and very limited set of supported peripherals

== Example 2: Sibling A10/A20 boards (such as Cubieboard1/Cubieboard2)

Some development boards are using exactly the same PCB for one variant
with Allwinner A10 SoC and another variant with Allwinner A20 SoC.
Instead of having two u-boot configurations and two incompatible
u-boot binaries, it is possible to re-use the same u-boot binary
for both of these boards.

Advantages: no performance or feature sacrifices
Disadvantages: only two boards are supported by a single u-boot binary
               (not a big overall improvement)

== Example 3: Univarsal u-boot binary and the settings in non-volatile memory

Most of Allwinner devices have NAND. Booting from NAND is supported by
BROM, so there is no reason why u-boot SPL can't read it too. Some
reserved area in NAND can store the whole DTB file, or even just a
DTB name (a key for lookup somewhere else). Additionally, DRAM timings
and unit specific tuning may be stored there too. This might be implemented
in a (not so) distant future.

Advantages: no performance of feature sacrifices, support for a large
            subset of devices
Disadvantages: somebody has to prepare the correct information in NAND
               (it could be the device vendor, or maybe some reliability
               testing/validation tool, etc.)


Anyway, this is just the beginning. And we have to start with something
simple. These two patches just provide an option for a single universal
u-boot binary with just UART and MMC support (essentially, the example 1).

The patches depend on
    https://patchwork.ozlabs.org/patch/375971/
and
    http://lists.denx.de/pipermail/u-boot/2014-August/185200.html


Siarhei Siamashka (2):
  sunxi: Replace CONFIG_SUN[457]I ifdefs with SOC_IS_SUN[457]I() calls
  sunxi: Universal Allwinner A10/A13/A20 u-boot binary support

 arch/arm/Kconfig                                |   3 +
 arch/arm/cpu/armv7/sunxi/Makefile               |   2 +
 arch/arm/cpu/armv7/sunxi/board.c                |  98 +++++++++++---
 arch/arm/cpu/armv7/sunxi/clock_sun4i.c          |  10 +-
 arch/arm/cpu/armv7/sunxi/cpu_info.c             |  37 ++---
 arch/arm/cpu/armv7/sunxi/dram.c                 | 171 ++++++++++++------------
 arch/arm/include/asm/arch-sunxi/sys_proto.h     |   5 +
 board/sunxi/Kconfig                             |  20 +++
 board/sunxi/MAINTAINERS                         |   7 +
 board/sunxi/Makefile                            |   1 +
 board/sunxi/board.c                             |   1 +
 board/sunxi/dram_sunxi_ddr3_failsafe.c          |  28 ++++
 configs/sunxi-generic-a10-a13-a20_FEL_defconfig |   4 +
 configs/sunxi-generic-a10-a13-a20_defconfig     |   4 +
 include/configs/sun4i.h                         |   2 +
 include/configs/sun4i_sun5i_sun7i.h             |  38 ++++++
 include/configs/sun5i.h                         |   2 +
 include/configs/sun7i.h                         |   2 +
 include/configs/sunxi-common.h                  |  12 ++
 19 files changed, 322 insertions(+), 125 deletions(-)
 create mode 100644 board/sunxi/dram_sunxi_ddr3_failsafe.c
 create mode 100644 configs/sunxi-generic-a10-a13-a20_FEL_defconfig
 create mode 100644 configs/sunxi-generic-a10-a13-a20_defconfig
 create mode 100644 include/configs/sun4i_sun5i_sun7i.h

-- 
1.8.3.2

[U-Boot] [PATCH 1/2] sunxi: Replace CONFIG_SUN[457]I ifdefs with SOC_IS_SUN[457]I() calls

[Siarhei Siamashka]

This is a purely mechanical conversion, replacing the ifdefs and
preparing the code for the use of runtime Allwinner SoC type
detection (within Allwinner A10/A13/A20 family).

Similar 'board_is_xxx()' calls are used for TI hardware.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
---
 arch/arm/cpu/armv7/sunxi/board.c       |  52 +++++-----
 arch/arm/cpu/armv7/sunxi/clock_sun4i.c |   7 +-
 arch/arm/cpu/armv7/sunxi/cpu_info.c    |  36 ++++---
 arch/arm/cpu/armv7/sunxi/dram.c        | 171 +++++++++++++++++----------------
 include/configs/sun4i.h                |   2 +
 include/configs/sun5i.h                |   2 +
 include/configs/sun7i.h                |   2 +
 include/configs/sunxi-common.h         |  12 +++
 8 files changed, 160 insertions(+), 124 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index f2cedbb..90e957c 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -50,22 +50,23 @@ u32 spl_boot_mode(void)
 
 int gpio_init(void)
 {
-#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
-	sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
-	sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
-#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
-	sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
-#else
-#error Unsupported console port number. Please fix pin mux settings in board.c
-#endif
-
+	if (CONFIG_CONS_INDEX == 1 && (SOC_IS_SUN4I() || SOC_IS_SUN7I())) {
+		sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
+		sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
+		sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
+	} else if (CONFIG_CONS_INDEX == 1 && SOC_IS_SUN5I()) {
+		sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
+		sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
+		sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
+	} else if (CONFIG_CONS_INDEX == 2 && SOC_IS_SUN5I()) {
+		sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
+		sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
+		sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
+	} else {
+		/* Unsupported console port number.
+		 * Please fix pin mux settings in board.c */
+		hang();
+	}
 	return 0;
 }
 
@@ -87,12 +88,19 @@ void reset_cpu(ulong addr)
 /* do some early init */
 void s_init(void)
 {
-#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I)
-	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
-	asm volatile(
-		"mrc p15, 0, r0, c1, c0, 1\n"
-		"orr r0, r0, #1 << 6\n"
-		"mcr p15, 0, r0, c1, c0, 1\n");
+#if !defined CONFIG_SPL_BUILD
+	int soc_is_sun6i = 0;
+#ifdef CONFIG_SUN6I
+	soc_is_sun6i = 1;
+#endif
+	if (SOC_IS_SUN7I() || soc_is_sun6i) {
+		/* Enable SMP mode for CPU0, by setting bit 6 of
+		 * Auxiliary Ctl reg */
+		asm volatile(
+			"mrc p15, 0, r0, c1, c0, 1\n"
+			"orr r0, r0, #1 << 6\n"
+			"mcr p15, 0, r0, c1, c0, 1\n" : : : "r0");
+	}
 #endif
 
 	clock_init();
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index ecbdb01..1af285e 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -35,9 +35,10 @@ void clock_init_safe(void)
 	       APB0_DIV_1 << APB0_DIV_SHIFT |
 	       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
 	       &ccm->cpu_ahb_apb0_cfg);
-#ifdef CONFIG_SUN7I
-	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
-#endif
+
+	if (SOC_IS_SUN7I())
+		setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
+
 	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
 #ifdef CONFIG_SUNXI_AHCI
 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index 5cf35ac..1134b21 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -13,22 +13,28 @@
 #ifdef CONFIG_DISPLAY_CPUINFO
 int print_cpuinfo(void)
 {
-#ifdef CONFIG_SUN4I
-	puts("CPU:   Allwinner A10 (SUN4I)\n");
-#elif defined CONFIG_SUN5I
-	u32 val = readl(SUNXI_SID_BASE + 0x08);
-	switch ((val >> 12) & 0xf) {
-	case 0: puts("CPU:   Allwinner A12 (SUN5I)\n"); break;
-	case 3: puts("CPU:   Allwinner A13 (SUN5I)\n"); break;
-	case 7: puts("CPU:   Allwinner A10s (SUN5I)\n"); break;
-	default: puts("CPU:   Allwinner A1X (SUN5I)\n");
+	if (SOC_IS_SUN4I()) {
+		puts("CPU:   Allwinner A10 (SUN4I)\n");
+	} else if (SOC_IS_SUN5I()) {
+		u32 val = readl(SUNXI_SID_BASE + 0x08);
+		switch ((val >> 12) & 0xf) {
+		case 0:
+			puts("CPU:   Allwinner A12 (SUN5I)\n");
+			break;
+		case 3:
+			puts("CPU:   Allwinner A13 (SUN5I)\n");
+			break;
+		case 7:
+			puts("CPU:   Allwinner A10s (SUN5I)\n");
+			break;
+		default:
+			puts("CPU:   Allwinner A1X (SUN5I)\n");
+		}
+	} else if (SOC_IS_SUN7I()) {
+		puts("CPU:   Allwinner A20 (SUN7I)\n");
+	} else {
+		puts("CPU:   SUNXI Family\n");
 	}
-#elif defined CONFIG_SUN7I
-	puts("CPU:   Allwinner A20 (SUN7I)\n");
-#else
-#warning Please update cpu_info.c with correct CPU information
-	puts("CPU:   SUNXI Family\n");
-#endif
 	return 0;
 }
 #endif
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 584f742..05cd66f 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -74,22 +74,23 @@ static void mctl_ddr3_reset(void)
 	struct sunxi_dram_reg *dram =
 			(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 
-#ifdef CONFIG_SUN4I
 	struct sunxi_timer_reg *timer =
 			(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
 	u32 reg_val;
-
-	writel(0, &timer->cpu_cfg);
-	reg_val = readl(&timer->cpu_cfg);
-
-	if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
-	    CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
-		setbits_le32(&dram->mcr, DRAM_MCR_RESET);
-		udelay(200);
-		clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
-	} else
-#endif
-	{
+	int reset_done = 0;
+
+	if (SOC_IS_SUN4I()) {
+		writel(0, &timer->cpu_cfg);
+		reg_val = readl(&timer->cpu_cfg);
+		if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
+		    CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
+			setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+			udelay(200);
+			clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
+			reset_done = 1;
+		}
+	}
+	if (!reset_done) {
 		clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
 		udelay(200);
 		setbits_le32(&dram->mcr, DRAM_MCR_RESET);
@@ -112,14 +113,10 @@ static void mctl_ddr3_reset(void)
 static void mctl_set_drive(void)
 {
 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-
-#ifdef CONFIG_SUN7I
-	clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
-#else
-	clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
-#endif
-			DRAM_MCR_MODE_EN(0x3) |
-			0xffc);
+	clrsetbits_le32(&dram->mcr,
+			DRAM_MCR_MODE_NORM(0x3) |
+					(SOC_IS_SUN7I() ? (0x3 << 28) : 0),
+			DRAM_MCR_MODE_EN(0x3) | 0xffc);
 }
 
 static void mctl_itm_disable(void)
@@ -201,8 +198,7 @@ static void mctl_enable_dllx(u32 phase)
 	udelay(22);
 }
 
-static u32 hpcr_value[32] = {
-#ifdef CONFIG_SUN5I
+static u32 hpcr_value_sun5i[32] = {
 	0, 0, 0, 0,
 	0, 0, 0, 0,
 	0, 0, 0, 0,
@@ -211,8 +207,9 @@ static u32 hpcr_value[32] = {
 	0x1035, 0x0731, 0x1031, 0,
 	0x0301, 0x0301, 0x0301, 0x0301,
 	0x0301, 0x0301, 0x0301, 0
-#endif
-#ifdef CONFIG_SUN4I
+};
+
+static u32 hpcr_value_sun4i[32] = {
 	0x0301, 0x0301, 0x0301, 0x0301,
 	0x0301, 0x0301, 0, 0,
 	0, 0, 0, 0,
@@ -221,8 +218,9 @@ static u32 hpcr_value[32] = {
 	0x1035, 0x0731, 0x1031, 0x0735,
 	0x1035, 0x1031, 0x0731, 0x1035,
 	0x1031, 0x0301, 0x0301, 0x0731
-#endif
-#ifdef CONFIG_SUN7I
+};
+
+static u32 hpcr_value_sun7i[32] = {
 	0x0301, 0x0301, 0x0301, 0x0301,
 	0x0301, 0x0301, 0x0301, 0x0301,
 	0, 0, 0, 0,
@@ -236,13 +234,21 @@ static u32 hpcr_value[32] = {
 	 * but boot0 code skips #28 and #30, and sets #29 and #31 to the
 	 * value from #28 entry (0x1031)
 	 */
-#endif
 };
 
 static void mctl_configure_hostport(void)
 {
 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 	u32 i;
+	u32 *hpcr_value;
+	if (SOC_IS_SUN4I())
+		hpcr_value = hpcr_value_sun4i;
+	else if (SOC_IS_SUN5I())
+		hpcr_value = hpcr_value_sun5i;
+	else if (SOC_IS_SUN7I())
+		hpcr_value = hpcr_value_sun7i;
+	else
+		panic("Can't detect the SoC type");
 
 	for (i = 0; i < 32; i++)
 		writel(hpcr_value[i], &dram->hpcr[i]);
@@ -258,9 +264,8 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
 	u32 pll6x_clk = clock_get_pll6() / 1000000;
 	u32 pll5p_clk = clk / 24 * 48;
 	u32 pll5p_rate, pll6x_rate;
-#ifdef CONFIG_SUN7I
-	pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
-#endif
+	if (SOC_IS_SUN7I())
+		pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
 
 	/* setup DRAM PLL */
 	reg_val = readl(&ccm->pll5_cfg);
@@ -311,13 +316,14 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
 
 	setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK);
 
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
-	/* reset GPS */
-	clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);
-	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
-	udelay(1);
-	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
-#endif
+	if (SOC_IS_SUN4I() || SOC_IS_SUN7I()) {
+		/* reset GPS */
+		clrbits_le32(&ccm->gps_clk_cfg,
+			     CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);
+		setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
+		udelay(1);
+		clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
+	}
 
 	/* setup MBUS clock */
 	if (!mbus_clk)
@@ -348,19 +354,15 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
 	 * open DRAMC AHB & DLL register clock
 	 * close it first
 	 */
-#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
-	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
-#else
-	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
-#endif
+	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM |
+		((SOC_IS_SUN5I() || SOC_IS_SUN7I()) ? CCM_AHB_GATE_DLL : 0));
+
 	udelay(22);
 
 	/* then open it */
-#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
-	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
-#else
-	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
-#endif
+	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM |
+		((SOC_IS_SUN5I() || SOC_IS_SUN7I()) ? CCM_AHB_GATE_DLL : 0));
+
 	udelay(22);
 }
 
@@ -417,21 +419,23 @@ static int dramc_scan_readpipe(void)
 
 static void dramc_clock_output_en(u32 on)
 {
-#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-
-	if (on)
-		setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
-	else
-		clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
-#endif
-#ifdef CONFIG_SUN4I
 	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-	if (on)
-		setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
-	else
-		clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
-#endif
+
+	if (SOC_IS_SUN5I() || SOC_IS_SUN7I()) {
+		if (on)
+			setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
+		else
+			clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
+	}
+	if (SOC_IS_SUN4I()) {
+		if (on)
+			setbits_le32(&ccm->dram_clk_cfg,
+				     CCM_DRAM_CTRL_DCLK_OUT);
+		else
+			clrbits_le32(&ccm->dram_clk_cfg,
+				     CCM_DRAM_CTRL_DCLK_OUT);
+	}
 }
 
 /* tRFC in nanoseconds for different densities (from the DDR3 spec) */
@@ -527,27 +531,25 @@ static void mctl_set_impedance(u32 zq, u32 odt_en)
 	u32 reg_val;
 	u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF;
 
-#ifndef CONFIG_SUN7I
 	/* Appears that some kind of automatically initiated default
 	 * ZQ calibration is already in progress at this point on sun4i/sun5i
 	 * hardware, but not on sun7i. So it is reasonable to wait for its
 	 * completion before doing anything else. */
-	await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);
-#endif
+	if (!SOC_IS_SUN7I())
+		await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);
 
 	/* ZQ calibration is not really useful unless ODT is enabled */
 	if (!odt_en)
 		return;
 
-#ifdef CONFIG_SUN7I
 	/* Enabling ODT in SDR_IOCR on sun7i hardware results in a deadlock
 	 * unless bit 24 is set in SDR_ZQCR1. Not much is known about the
 	 * SDR_ZQCR1 register, but there are hints indicating that it might
 	 * be related to periodic impedance re-calibration. This particular
 	 * magic value is borrowed from the Allwinner boot0 bootloader, and
 	 * using it helps to avoid troubles */
-	writel((1 << 24) | (1 << 1), &dram->zqcr1);
-#endif
+	if (SOC_IS_SUN7I())
+		writel((1 << 24) | (1 << 1), &dram->zqcr1);
 
 	/* Needed at least for sun5i, because it does not self clear there */
 	clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);
@@ -597,10 +599,10 @@ static unsigned long dramc_init_helper(struct dram_para *para)
 	/* dram clock off */
 	dramc_clock_output_en(0);
 
-#ifdef CONFIG_SUN4I
-	/* select dram controller 1 */
-	writel(DRAM_CSEL_MAGIC, &dram->csel);
-#endif
+	if (SOC_IS_SUN4I()) {
+		/* select dram controller 1 */
+		writel(DRAM_CSEL_MAGIC, &dram->csel);
+	}
 
 	mctl_itm_disable();
 	mctl_enable_dll0(para->tpr3);
@@ -654,9 +656,8 @@ static unsigned long dramc_init_helper(struct dram_para *para)
 	writel(para->tpr2, &dram->tpr2);
 
 	reg_val = DRAM_MR_BURST_LENGTH(0x0);
-#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
-	reg_val |= DRAM_MR_POWER_DOWN;
-#endif
+	if (SOC_IS_SUN5I() || SOC_IS_SUN7I())
+		reg_val |= DRAM_MR_POWER_DOWN;
 	reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
 	reg_val |= DRAM_MR_WRITE_RECOVERY(ddr3_write_recovery(para->clock));
 	writel(reg_val, &dram->mr);
@@ -668,11 +669,10 @@ static unsigned long dramc_init_helper(struct dram_para *para)
 	/* disable drift compensation and set passive DQS window mode */
 	clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
 
-#ifdef CONFIG_SUN7I
 	/* Command rate timing mode 2T & 1T */
-	if (para->tpr4 & 0x1)
+	if (SOC_IS_SUN7I() && (para->tpr4 & 0x1))
 		setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
-#endif
+
 	/* initialize external DRAM */
 	mctl_ddr3_initialize();
 
@@ -718,13 +718,16 @@ unsigned long dramc_init(struct dram_para *para)
 	/* try to autodetect the DRAM bus width and density */
 	para->io_width  = 16;
 	para->bus_width = 32;
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I)
-	/* only A0-A14 address lines on A10/A13, limiting max density to 4096 */
-	para->density = 4096;
-#else
-	/* all A0-A15 address lines on A20, which allow density 8192 */
-	para->density = 8192;
-#endif
+
+	if (SOC_IS_SUN4I() || SOC_IS_SUN5I()) {
+		/* only A0-A14 address lines on A10/A13,
+		 * limiting max density to 4096 */
+		para->density = 4096;
+	} else {
+		/* all A0-A15 address lines on A20,
+		 * which allow density 8192 */
+		para->density = 8192;
+	}
 
 	dram_size = dramc_init_helper(para);
 	if (!dram_size) {
diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h
index 5611ecc..d08804c 100644
--- a/include/configs/sun4i.h
+++ b/include/configs/sun4i.h
@@ -14,6 +14,8 @@
 #define CONFIG_SUN4I		/* sun4i SoC generation */
 #define CONFIG_CLK_FULL_SPEED		1008000000
 
+#define SOC_IS_SUN4I() 1
+
 #define CONFIG_SYS_PROMPT		"sun4i# "
 
 #ifdef CONFIG_USB_EHCI
diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h
index 6066371..b6c0669 100644
--- a/include/configs/sun5i.h
+++ b/include/configs/sun5i.h
@@ -14,6 +14,8 @@
 #define CONFIG_SUN5I		/* sun5i SoC generation */
 #define CONFIG_CLK_FULL_SPEED		1008000000
 
+#define SOC_IS_SUN5I() 1
+
 #define CONFIG_SYS_PROMPT		"sun5i# "
 
 #ifdef CONFIG_USB_EHCI
diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
index a902b84..d3f0322 100644
--- a/include/configs/sun7i.h
+++ b/include/configs/sun7i.h
@@ -15,6 +15,8 @@
 #define CONFIG_SUN7I		/* sun7i SoC generation */
 #define CONFIG_CLK_FULL_SPEED		912000000
 
+#define SOC_IS_SUN7I() 1
+
 #define CONFIG_SYS_PROMPT		"sun7i# "
 
 #ifdef CONFIG_USB_EHCI
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 6a3044f..267bf2a 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -13,6 +13,18 @@
 #ifndef _SUNXI_COMMON_CONFIG_H
 #define _SUNXI_COMMON_CONFIG_H
 
+#ifndef SOC_IS_SUN4I
+#define SOC_IS_SUN4I() 0
+#endif
+
+#ifndef SOC_IS_SUN5I
+#define SOC_IS_SUN5I() 0
+#endif
+
+#ifndef SOC_IS_SUN7I
+#define SOC_IS_SUN7I() 0
+#endif
+
 /*
  * High Level Configuration Options
  */
-- 
1.8.3.2

[U-Boot] [PATCH 2/2] sunxi: Universal Allwinner A10/A13/A20 u-boot binary support

[Siarhei Siamashka]

Two new defconfigs ('sunxi-generic-a10-a13-a20_defconfig' and
'sunxi-generic-a10-a13-a20_FEL_defconfig') can be used to build
universal u-boot binaries, suitable for all Allwinner
A10/A13/A20 devices. The supported peripherals are just UART
and MMC (the lowest common denominator approach).

MMC support is completely problem free for runtime detection,
because it must be supported by BROM and no strange pin muxing
configurations are expected.

UART is a bit more difficult, but in practice very few
configurations exist. And they can be successfully detected
at runtime. CONFIG_CONS_INDEX=1 is used on almost all devices.
And CONFIG_CONS_INDEX=2 is only used on Allwinner A13, where
the SoC just does not have the B19/B20 pins on the package,
which are normally used for CONFIG_CONS_INDEX=1 UART on Allwiner
A10S. So it is a matter of necessity and not a random choice.

The universal u-boot binary should be sufficient for booting
the system from SD card and/or getting the u-boot command
prompt on the serial console.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
---
 arch/arm/Kconfig                                |  3 ++
 arch/arm/cpu/armv7/sunxi/Makefile               |  2 +
 arch/arm/cpu/armv7/sunxi/board.c                | 52 +++++++++++++++++++++++--
 arch/arm/cpu/armv7/sunxi/clock_sun4i.c          |  3 +-
 arch/arm/cpu/armv7/sunxi/cpu_info.c             |  1 +
 arch/arm/include/asm/arch-sunxi/sys_proto.h     |  5 +++
 board/sunxi/Kconfig                             | 20 ++++++++++
 board/sunxi/MAINTAINERS                         |  7 ++++
 board/sunxi/Makefile                            |  1 +
 board/sunxi/board.c                             |  1 +
 board/sunxi/dram_sunxi_ddr3_failsafe.c          | 28 +++++++++++++
 configs/sunxi-generic-a10-a13-a20_FEL_defconfig |  4 ++
 configs/sunxi-generic-a10-a13-a20_defconfig     |  4 ++
 include/configs/sun4i_sun5i_sun7i.h             | 38 ++++++++++++++++++
 14 files changed, 165 insertions(+), 4 deletions(-)
 create mode 100644 board/sunxi/dram_sunxi_ddr3_failsafe.c
 create mode 100644 configs/sunxi-generic-a10-a13-a20_FEL_defconfig
 create mode 100644 configs/sunxi-generic-a10-a13-a20_defconfig
 create mode 100644 include/configs/sun4i_sun5i_sun7i.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e385eda..95887f6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -650,6 +650,9 @@ config TARGET_SUN5I
 config TARGET_SUN7I
 	bool "Support sun7i"
 
+config TARGET_SUN4I_SUN5I_SUN7I
+	bool "Support sun4i/sun5i/sun7i"
+
 config TARGET_SNOWBALL
 	bool "Support snowball"
 
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index e9721b2..e8844ad 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -14,6 +14,7 @@ obj-y	+= pinmux.o
 obj-$(CONFIG_SUN4I)	+= clock_sun4i.o
 obj-$(CONFIG_SUN5I)	+= clock_sun4i.o
 obj-$(CONFIG_SUN7I)	+= clock_sun4i.o
+obj-$(CONFIG_SUN4I_SUN5I_SUN7I)	+= clock_sun4i.o
 
 ifndef CONFIG_SPL_BUILD
 obj-y	+= cpu_info.o
@@ -26,6 +27,7 @@ ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SUN4I)	+= dram.o
 obj-$(CONFIG_SUN5I)	+= dram.o
 obj-$(CONFIG_SUN7I)	+= dram.o
+obj-$(CONFIG_SUN4I_SUN5I_SUN7I)	+= dram.o
 ifdef CONFIG_SPL_FEL
 obj-y	+= start.o
 endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 90e957c..422d224 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -48,17 +48,62 @@ u32 spl_boot_mode(void)
 }
 #endif
 
+static void sunxi_soc_detect_init(void)
+{
+	/* Enable VER_REG (set the VER_R_EN bit) */
+	setbits_le32((u32 *)(SUNXI_SRAMC_BASE + 0x24), 1 << 15);
+}
+
+int soc_is_sun4i(void)
+{
+	return (readl((u32 *)(SUNXI_SRAMC_BASE + 0x24)) >> 16) == 0x1623;
+}
+
+int soc_is_sun5i(void)
+{
+	return (readl((u32 *)(SUNXI_SRAMC_BASE + 0x24)) >> 16) == 0x1625;
+}
+
+int soc_is_sun7i(void)
+{
+	return (readl((u32 *)(SUNXI_SRAMC_BASE + 0x24)) >> 16) == 0x1651;
+}
+
+int sunxi_cons_index(void)
+{
+	int cons_index = CONFIG_CONS_INDEX;
+
+	if (cons_index == 1 && SOC_IS_SUN5I()) {
+		u32 val = readl(SUNXI_SID_BASE + 0x08);
+		if (((val >> 12) & 0xf) == 3) {
+			/* Allwinner A13 */
+			cons_index = 2;
+		}
+	}
+	return cons_index;
+}
+
+struct serial_device *default_serial_console(void)
+{
+	if (sunxi_cons_index() == 1)
+		return &eserial1_device;
+	else
+		return &eserial2_device;
+}
+
 int gpio_init(void)
 {
-	if (CONFIG_CONS_INDEX == 1 && (SOC_IS_SUN4I() || SOC_IS_SUN7I())) {
+	int cons_index = sunxi_cons_index();
+
+	if (cons_index == 1 && (SOC_IS_SUN4I() || SOC_IS_SUN7I())) {
 		sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
 		sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
 		sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
-	} else if (CONFIG_CONS_INDEX == 1 && SOC_IS_SUN5I()) {
+	} else if (cons_index == 1 && SOC_IS_SUN5I()) {
 		sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
 		sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
 		sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
-	} else if (CONFIG_CONS_INDEX == 2 && SOC_IS_SUN5I()) {
+	} else if (cons_index == 2 && SOC_IS_SUN5I()) {
 		sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
 		sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
 		sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
@@ -88,6 +133,7 @@ void reset_cpu(ulong addr)
 /* do some early init */
 void s_init(void)
 {
+	sunxi_soc_detect_init();
 #if !defined CONFIG_SPL_BUILD
 	int soc_is_sun6i = 0;
 #ifdef CONFIG_SUN6I
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index 1af285e..3d0f1ad 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -51,6 +51,7 @@ void clock_init_uart(void)
 {
 	struct sunxi_ccm_reg *const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	int cons_index = sunxi_cons_index();
 
 	/* uart clock source is apb1 */
 	writel(APB1_CLK_SRC_OSC24M|
@@ -60,7 +61,7 @@ void clock_init_uart(void)
 
 	/* open the clock for uart */
 	setbits_le32(&ccm->apb1_gate,
-		CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX-1));
+		CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT + cons_index - 1));
 }
 
 int clock_twi_onoff(int port, int state)
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index 1134b21..483b98c 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
 
 #ifdef CONFIG_DISPLAY_CPUINFO
 int print_cpuinfo(void)
diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h
index c3e636e..b422581 100644
--- a/arch/arm/include/asm/arch-sunxi/sys_proto.h
+++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h
@@ -13,4 +13,9 @@
 
 void sdelay(unsigned long);
 
+int  sunxi_cons_index(void);
+int  soc_is_sun4i(void);
+int  soc_is_sun5i(void);
+int  soc_is_sun7i(void);
+
 #endif
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index b06b5e0..098b0df 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -57,3 +57,23 @@ config SYS_CONFIG_NAME
 	default "sun7i"
 
 endif
+
+if TARGET_SUN4I_SUN5I_SUN7I
+
+config SYS_CPU
+	string
+	default "armv7"
+
+config SYS_BOARD
+	string
+	default "sunxi"
+
+config SYS_SOC
+	string
+	default "sunxi"
+
+config SYS_CONFIG_NAME
+	string
+	default "sun4i_sun5i_sun7i"
+
+endif
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index b0b1804..e438bf2 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -32,3 +32,10 @@ F:	configs/Cubieboard2_defconfig
 F:	configs/Cubieboard2_FEL_defconfig
 F:	configs/Cubietruck_defconfig
 F:	configs/Cubietruck_FEL_defconfig
+
+SUNXI GENERIC
+M:	Siarhei Siamashka <siarhei.siamashka@gmail.com>
+S:	Maintained
+F:	include/configs/sun4i_sun5i_sun7i.h
+F:	configs/sunxi-generic-a10-a13-a20_defconfig
+F:	configs/sunxi-generic-a10-a13-a20_FEL_defconfig
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index cf001e7..dd70a95 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -11,6 +11,7 @@
 obj-y	+= board.o
 obj-$(CONFIG_SUNXI_GMAC)	+= gmac.o
 obj-$(CONFIG_SUNXI_AHCI)	+= ahci.o
+obj-$(CONFIG_SUNXI_GENERIC_A10_A13_A20) += dram_sunxi_ddr3_failsafe.o
 obj-$(CONFIG_A10_OLINUXINO_L)	+= dram_a10_olinuxino_l.o
 obj-$(CONFIG_A10S_OLINUXINO_M)	+= dram_a10s_olinuxino_m.o
 obj-$(CONFIG_A13_OLINUXINO)	+= dram_a13_olinuxino.o
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 2179e23..edbfc44 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -23,6 +23,7 @@
 #include <asm/arch/dram.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <net.h>
 
diff --git a/board/sunxi/dram_sunxi_ddr3_failsafe.c b/board/sunxi/dram_sunxi_ddr3_failsafe.c
new file mode 100644
index 0000000..348e0b9
--- /dev/null
+++ b/board/sunxi/dram_sunxi_ddr3_failsafe.c
@@ -0,0 +1,28 @@
+/* this file is generated, don't edit it yourself */
+
+#include "common.h"
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = { /* DRAM timings: 6-5-5-13 (360 MHz) */
+	.clock = 360,
+	.type = 3,
+	.rank_num = 1,
+	.cas = 6,
+	.zq = 0x7b,
+	.odt_en = 0,
+	.tpr0 = 0x248d5590,
+	.tpr1 = 0xa088,
+	.tpr2 = 0x22a00,
+	.tpr3 = 0x0,
+	.tpr4 = 0x0,
+	.tpr5 = 0x0,
+	.emr1 = 0x0,
+	.emr2 = 0x0,
+	.emr3 = 0x0,
+	.active_windowing = 1,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+	return dramc_init(&dram_para);
+}
diff --git a/configs/sunxi-generic-a10-a13-a20_FEL_defconfig b/configs/sunxi-generic-a10-a13-a20_FEL_defconfig
new file mode 100644
index 0000000..2a8a303
--- /dev/null
+++ b/configs/sunxi-generic-a10-a13-a20_FEL_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GENERIC_A10_A13_A20,SPL_FEL"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_SUN4I_SUN5I_SUN7I=y
diff --git a/configs/sunxi-generic-a10-a13-a20_defconfig b/configs/sunxi-generic-a10-a13-a20_defconfig
new file mode 100644
index 0000000..c42699c
--- /dev/null
+++ b/configs/sunxi-generic-a10-a13-a20_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GENERIC_A10_A13_A20,SPL"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_SUN4I_SUN5I_SUN7I=y
diff --git a/include/configs/sun4i_sun5i_sun7i.h b/include/configs/sun4i_sun5i_sun7i.h
new file mode 100644
index 0000000..16dbce1
--- /dev/null
+++ b/include/configs/sun4i_sun5i_sun7i.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * Configuration settings for the Allwinner A10 (sun4i) CPU
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define SOC_IS_SUN4I()			(soc_is_sun4i())
+#define SOC_IS_SUN5I()			(soc_is_sun5i())
+#define SOC_IS_SUN7I()			(soc_is_sun7i())
+
+#define CONFIG_SUN4I_SUN5I_SUN7I
+#define CONFIG_CLK_FULL_SPEED		(SOC_IS_SUN7I() ? 912000000 : \
+							  1008000000)
+
+#define CONFIG_SYS_PROMPT		"sunxi# "
+
+/* The Cortex-A8 CPU in sun4i/sun5i is going to fail runtime
+ * check and will fallback to booting the kernel in secure mode */
+#define CONFIG_ARMV7_ALLOW_SECURE_MODE_FALLBACK 1
+
+/* This is going to be used for sun7i */
+#define CONFIG_ARMV7_VIRT		1
+#define CONFIG_ARMV7_NONSEC		1
+#define CONFIG_ARMV7_PSCI		1
+#define CONFIG_ARMV7_PSCI_NR_CPUS	2
+#define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
+#define CONFIG_SYS_CLK_FREQ		24000000
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
-- 
1.8.3.2

[U-Boot] [linux-sunxi] [PATCH 0/2] sunxi: Single u-boot binary for Allwinner A10/A13/A20 devices

[jonsmirl at gmail.com]

Could this work...
Universal Allwinner uboot
uboot loads DTB (from same place it just booted)
restart with DRAM parameters (console, etc) from DTB

Is it possible to write a uboot app that measures the DRAM parameters?
Maybe something like this: pick a param, write to flash, try it out,
repeat. Set watchdog in case it fails. When watchdog fires pick up
last known working params and update the DTB. then alter uboot
evironment not to run this mem test app at boot anymore.


On Sat, Aug 2, 2014 at 11:26 PM, Siarhei Siamashka
<siarhei.siamashka@gmail.com> wrote:
> This patchset introduces the initial rudimentary support for having
> just a single u-boot binary for certain subsets of Allwinner A10/A13/A20
> devices.
>
> == Example 1: All Allwinner A10/A13/A20 devices
>
> We are restricted to only a very basic common subset of peripherals
> (anything that is supported by BROM should be fine). This provides
> a possibility to at least boot from the SD card and use some slow
> fail-safe DRAM settings. UART, USB and HDMI settings are also
> relatively easy to detect at runtime. This provides a possibility
> to implement universal installers, which would somehow boot the
> system and allow the user to change u-boot and dtb to something
> more suitable for his hardware.
>
> Advantages: just works everywhere
> Disadvantages: poor performance and very limited set of supported peripherals
>
> == Example 2: Sibling A10/A20 boards (such as Cubieboard1/Cubieboard2)
>
> Some development boards are using exactly the same PCB for one variant
> with Allwinner A10 SoC and another variant with Allwinner A20 SoC.
> Instead of having two u-boot configurations and two incompatible
> u-boot binaries, it is possible to re-use the same u-boot binary
> for both of these boards.
>
> Advantages: no performance or feature sacrifices
> Disadvantages: only two boards are supported by a single u-boot binary
>                (not a big overall improvement)
>
> == Example 3: Univarsal u-boot binary and the settings in non-volatile memory
>
> Most of Allwinner devices have NAND. Booting from NAND is supported by
> BROM, so there is no reason why u-boot SPL can't read it too. Some
> reserved area in NAND can store the whole DTB file, or even just a
> DTB name (a key for lookup somewhere else). Additionally, DRAM timings
> and unit specific tuning may be stored there too. This might be implemented
> in a (not so) distant future.
>
> Advantages: no performance of feature sacrifices, support for a large
>             subset of devices
> Disadvantages: somebody has to prepare the correct information in NAND
>                (it could be the device vendor, or maybe some reliability
>                testing/validation tool, etc.)
>
>
> Anyway, this is just the beginning. And we have to start with something
> simple. These two patches just provide an option for a single universal
> u-boot binary with just UART and MMC support (essentially, the example 1).
>
> The patches depend on
>     https://patchwork.ozlabs.org/patch/375971/
> and
>     http://lists.denx.de/pipermail/u-boot/2014-August/185200.html
>
>
> Siarhei Siamashka (2):
>   sunxi: Replace CONFIG_SUN[457]I ifdefs with SOC_IS_SUN[457]I() calls
>   sunxi: Universal Allwinner A10/A13/A20 u-boot binary support
>
>  arch/arm/Kconfig                                |   3 +
>  arch/arm/cpu/armv7/sunxi/Makefile               |   2 +
>  arch/arm/cpu/armv7/sunxi/board.c                |  98 +++++++++++---
>  arch/arm/cpu/armv7/sunxi/clock_sun4i.c          |  10 +-
>  arch/arm/cpu/armv7/sunxi/cpu_info.c             |  37 ++---
>  arch/arm/cpu/armv7/sunxi/dram.c                 | 171 ++++++++++++------------
>  arch/arm/include/asm/arch-sunxi/sys_proto.h     |   5 +
>  board/sunxi/Kconfig                             |  20 +++
>  board/sunxi/MAINTAINERS                         |   7 +
>  board/sunxi/Makefile                            |   1 +
>  board/sunxi/board.c                             |   1 +
>  board/sunxi/dram_sunxi_ddr3_failsafe.c          |  28 ++++
>  configs/sunxi-generic-a10-a13-a20_FEL_defconfig |   4 +
>  configs/sunxi-generic-a10-a13-a20_defconfig     |   4 +
>  include/configs/sun4i.h                         |   2 +
>  include/configs/sun4i_sun5i_sun7i.h             |  38 ++++++
>  include/configs/sun5i.h                         |   2 +
>  include/configs/sun7i.h                         |   2 +
>  include/configs/sunxi-common.h                  |  12 ++
>  19 files changed, 322 insertions(+), 125 deletions(-)
>  create mode 100644 board/sunxi/dram_sunxi_ddr3_failsafe.c
>  create mode 100644 configs/sunxi-generic-a10-a13-a20_FEL_defconfig
>  create mode 100644 configs/sunxi-generic-a10-a13-a20_defconfig
>  create mode 100644 include/configs/sun4i_sun5i_sun7i.h
>
> --
> 1.8.3.2
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe at googlegroups.com.
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-- 
Jon Smirl
jonsmirl at gmail.com

[U-Boot] [linux-sunxi] [PATCH 0/2] sunxi: Single u-boot binary for Allwinner A10/A13/A20 devices

[Henrik Nordström]

s?n 2014-08-03 klockan 06:26 +0300 skrev Siarhei Siamashka:

> Most of Allwinner devices have NAND. Booting from NAND is supported by
> BROM, so there is no reason why u-boot SPL can't read it too.

An alterantive is to let BROM load it. BROM has support for a custom
header on the loaded boot binary, and is where Allwinner store hardware
properties needed by the bootloader.

Today we do not use this area in the SPL, but it's trivial to add. Have
always been the intention to have DRAM parameters there.

Regards
Henrik

[U-Boot] [PATCH 1/2] sunxi: Replace CONFIG_SUN[457]I ifdefs with SOC_IS_SUN[457]I() calls

[Ian Campbell]

On Sun, 2014-08-03 at 06:26 +0300, Siarhei Siamashka wrote:
> This is a purely mechanical conversion, replacing the ifdefs and
> preparing the code for the use of runtime Allwinner SoC type
> detection (within Allwinner A10/A13/A20 family).
> 
> Similar 'board_is_xxx()' calls are used for TI hardware.

I think this should be either soc_is_sunXi() giving the appearance of a
function of SOC_IS_SUNxI giving the appearance of a variable.

Other than that assuming the conversion is mechanical I think it is
fine.

Ian.

[U-Boot] [PATCH 2/2] sunxi: Universal Allwinner A10/A13/A20 u-boot binary support

[Ian Campbell]

On Sun, 2014-08-03 at 06:26 +0300, Siarhei Siamashka wrote:

> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index e385eda..95887f6 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -650,6 +650,9 @@ config TARGET_SUN5I
>  config TARGET_SUN7I
>  	bool "Support sun7i"
>  
> +config TARGET_SUN4I_SUN5I_SUN7I
> +	bool "Support sun4i/sun5i/sun7i"

Is the intention to eventually support sun6i/sun8i etc here too? I think
we should try and avoid enumerating them in the names of everything
(Kconfig, filenames etc) and instead us TARGET_SUNXI_GENERIC or
TARGET_SUNXI_MULTI or something along those lines, or perhaps Kconfig
could present a bool for each of the subarches and enabling more than
one would enable multiple mode.

Not directly related to this series but probably arch/arm/Kconfig should
have TARGET_SUNXI and the 4i/5i/7i stuff ought to move down into
arch/arm/sunxi/Kconfig.

> @@ -48,17 +48,62 @@ u32 spl_boot_mode(void)
>  }
>  #endif
>  
> +static void sunxi_soc_detect_init(void)
> +{
> +	/* Enable VER_REG (set the VER_R_EN bit) */
> +	setbits_le32((u32 *)(SUNXI_SRAMC_BASE + 0x24), 1 << 15);

Please can you #define 0x24 and the various masks/shifts.
> +}
> +
> +int soc_is_sun4i(void)

All of these should use a common helper which takes the ID as a
parameter or the SOC_IS_xxx macros could just use that helper directly
if the wrappers turn out not that useful.

A bit of cpp trickery could also lead to:

#define SUNXI_SOC_ID_SUN4I 0x1623
#define SUNXO_SOC_ID...
#define SUNXI_SOC_IS(X) soc_is(SUNXI_SOC_ID_#X)

Used as SUNXI_SOC_IS(SUN4I) etc. What do you think?

> +
> +	if (cons_index == 1 && SOC_IS_SUN5I()) {
> +		u32 val = readl(SUNXI_SID_BASE + 0x08);
> +		if (((val >> 12) & 0xf) == 3) {

Can we use some #defines for the masks and shifts please.

> diff --git a/board/sunxi/dram_sunxi_ddr3_failsafe.c b/board/sunxi/dram_sunxi_ddr3_failsafe.c
> new file mode 100644
> index 0000000..348e0b9
> --- /dev/null
> +++ b/board/sunxi/dram_sunxi_ddr3_failsafe.c

How about putting this stuff in dram.c (or a new dram_default.c if you
prefer) marked as __weak? IOW make it the default for everything which
doesn't add a more specific dram_foo.c.

> @@ -0,0 +1,28 @@
> +/* this file is generated, don't edit it yourself */

I've had my doubts about this comment in the past, but here in
particular I was under the impression that you had manually selected the
safest values.

> +#define CONFIG_SYS_PROMPT		"sunxi# "

TBH I think we should just move this to -common.h and nuke the sun[457]i
ones, they don't serve much purpose, the specific SOC is identified in
the boot banner already.

FYI I'm now AFK until the 18th.

Ian.

[U-Boot] [PATCH 0/2] sunxi: Single u-boot binary for Allwinner A10/A13/A20 devices

[Hans de Goede]

Hi Siarhei,

On 08/03/2014 05:26 AM, Siarhei Siamashka wrote:
> This patchset introduces the initial rudimentary support for having
> just a single u-boot binary for certain subsets of Allwinner A10/A13/A20
> devices.
> 
> == Example 1: All Allwinner A10/A13/A20 devices
> 
> We are restricted to only a very basic common subset of peripherals
> (anything that is supported by BROM should be fine). This provides
> a possibility to at least boot from the SD card and use some slow
> fail-safe DRAM settings. UART, USB and HDMI settings are also
> relatively easy to detect at runtime. This provides a possibility
> to implement universal installers, which would somehow boot the
> system and allow the user to change u-boot and dtb to something
> more suitable for his hardware.
> 
> Advantages: just works everywhere
> Disadvantages: poor performance and very limited set of supported peripherals
> 
> == Example 2: Sibling A10/A20 boards (such as Cubieboard1/Cubieboard2)
> 
> Some development boards are using exactly the same PCB for one variant
> with Allwinner A10 SoC and another variant with Allwinner A20 SoC.
> Instead of having two u-boot configurations and two incompatible
> u-boot binaries, it is possible to re-use the same u-boot binary
> for both of these boards.
> 
> Advantages: no performance or feature sacrifices
> Disadvantages: only two boards are supported by a single u-boot binary
>                (not a big overall improvement)
> 
> == Example 3: Univarsal u-boot binary and the settings in non-volatile memory
> 
> Most of Allwinner devices have NAND. Booting from NAND is supported by
> BROM, so there is no reason why u-boot SPL can't read it too. Some
> reserved area in NAND can store the whole DTB file, or even just a
> DTB name (a key for lookup somewhere else). Additionally, DRAM timings
> and unit specific tuning may be stored there too. This might be implemented
> in a (not so) distant future.
> 
> Advantages: no performance of feature sacrifices, support for a large
>             subset of devices
> Disadvantages: somebody has to prepare the correct information in NAND
>                (it could be the device vendor, or maybe some reliability
>                testing/validation tool, etc.)
> 
> 
> Anyway, this is just the beginning. And we have to start with something
> simple. These two patches just provide an option for a single universal
> u-boot binary with just UART and MMC support (essentially, the example 1).

First of all many thanks for these patches.

I like the general principle, but I think we should go further then you do
and instead of introducing CONFIG_SUN4I_SUN5I_SUN7I and keeping
CONFIG_SUN4I and friends, we should merge all of them into a single
CONFIG_SUNXI. I see no reason why the board specific configs could not
still use the generic code paths.

Yes this means that a tiny amount of code which could otherwise be compiled
out because we know we will be on e.g. sun7i will not be compiled out, but it
is such a little amount of code that I don't think it is worth the hassle of
having 4 different CONFIG options, so I suggest that in the first patch
instead of uppercase names you use lower case ones to indicate that this
are (will be) normal functions, and then in the second patch instead
of adding CONFIG_SUN4I_SUN5I_SUN7I drop CONFIG_SUN4I SUN5I and SUN7I
and simply always call the functions checking the soc type even when build
for a specific board. This should lead to quite a nice cleanup (and potential
future cleanups).

We will still need separate board configs for optional dram settings, enabling
of optional pheriphials, etc. But we should be able keep the core code between
a generic board and a board specific build identical, rather then adding
more ifdefs.

This pretty much also summarizes my comments on the second patch.

I've some more specific comments on the first patch so I'll reply to that
one separately.

Regards,

Hans







> 
> The patches depend on
>     https://patchwork.ozlabs.org/patch/375971/
> and
>     http://lists.denx.de/pipermail/u-boot/2014-August/185200.html
> 
> 
> Siarhei Siamashka (2):
>   sunxi: Replace CONFIG_SUN[457]I ifdefs with SOC_IS_SUN[457]I() calls
>   sunxi: Universal Allwinner A10/A13/A20 u-boot binary support
> 
>  arch/arm/Kconfig                                |   3 +
>  arch/arm/cpu/armv7/sunxi/Makefile               |   2 +
>  arch/arm/cpu/armv7/sunxi/board.c                |  98 +++++++++++---
>  arch/arm/cpu/armv7/sunxi/clock_sun4i.c          |  10 +-
>  arch/arm/cpu/armv7/sunxi/cpu_info.c             |  37 ++---
>  arch/arm/cpu/armv7/sunxi/dram.c                 | 171 ++++++++++++------------
>  arch/arm/include/asm/arch-sunxi/sys_proto.h     |   5 +
>  board/sunxi/Kconfig                             |  20 +++
>  board/sunxi/MAINTAINERS                         |   7 +
>  board/sunxi/Makefile                            |   1 +
>  board/sunxi/board.c                             |   1 +
>  board/sunxi/dram_sunxi_ddr3_failsafe.c          |  28 ++++
>  configs/sunxi-generic-a10-a13-a20_FEL_defconfig |   4 +
>  configs/sunxi-generic-a10-a13-a20_defconfig     |   4 +
>  include/configs/sun4i.h                         |   2 +
>  include/configs/sun4i_sun5i_sun7i.h             |  38 ++++++
>  include/configs/sun5i.h                         |   2 +
>  include/configs/sun7i.h                         |   2 +
>  include/configs/sunxi-common.h                  |  12 ++
>  19 files changed, 322 insertions(+), 125 deletions(-)
>  create mode 100644 board/sunxi/dram_sunxi_ddr3_failsafe.c
>  create mode 100644 configs/sunxi-generic-a10-a13-a20_FEL_defconfig
>  create mode 100644 configs/sunxi-generic-a10-a13-a20_defconfig
>  create mode 100644 include/configs/sun4i_sun5i_sun7i.h
> 

[U-Boot] [PATCH 1/2] sunxi: Replace CONFIG_SUN[457]I ifdefs with SOC_IS_SUN[457]I() calls

[Hans de Goede]

Hi,

On 08/03/2014 05:26 AM, Siarhei Siamashka wrote:
> This is a purely mechanical conversion, replacing the ifdefs and
> preparing the code for the use of runtime Allwinner SoC type
> detection (within Allwinner A10/A13/A20 family).
> 
> Similar 'board_is_xxx()' calls are used for TI hardware.
> 
> Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
> ---
>  arch/arm/cpu/armv7/sunxi/board.c       |  52 +++++-----
>  arch/arm/cpu/armv7/sunxi/clock_sun4i.c |   7 +-
>  arch/arm/cpu/armv7/sunxi/cpu_info.c    |  36 ++++---
>  arch/arm/cpu/armv7/sunxi/dram.c        | 171 +++++++++++++++++----------------
>  include/configs/sun4i.h                |   2 +
>  include/configs/sun5i.h                |   2 +
>  include/configs/sun7i.h                |   2 +
>  include/configs/sunxi-common.h         |  12 +++
>  8 files changed, 160 insertions(+), 124 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
> index f2cedbb..90e957c 100644
> --- a/arch/arm/cpu/armv7/sunxi/board.c
> +++ b/arch/arm/cpu/armv7/sunxi/board.c
> @@ -50,22 +50,23 @@ u32 spl_boot_mode(void)
>  
>  int gpio_init(void)
>  {
> -#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
> -	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
> -	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
> -	sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
> -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
> -	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
> -	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
> -	sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
> -#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
> -	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
> -	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
> -	sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
> -#else
> -#error Unsupported console port number. Please fix pin mux settings in board.c
> -#endif
> -
> +	if (CONFIG_CONS_INDEX == 1 && (SOC_IS_SUN4I() || SOC_IS_SUN7I())) {
> +		sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
> +		sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
> +		sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
> +	} else if (CONFIG_CONS_INDEX == 1 && SOC_IS_SUN5I()) {
> +		sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
> +		sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
> +		sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
> +	} else if (CONFIG_CONS_INDEX == 2 && SOC_IS_SUN5I()) {
> +		sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
> +		sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
> +		sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
> +	} else {
> +		/* Unsupported console port number.
> +		 * Please fix pin mux settings in board.c */
> +		hang();
> +	}
>  	return 0;
>  }
>  
> @@ -87,12 +88,19 @@ void reset_cpu(ulong addr)
>  /* do some early init */
>  void s_init(void)
>  {
> -#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I)
> -	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
> -	asm volatile(
> -		"mrc p15, 0, r0, c1, c0, 1\n"
> -		"orr r0, r0, #1 << 6\n"
> -		"mcr p15, 0, r0, c1, c0, 1\n");
> +#if !defined CONFIG_SPL_BUILD
> +	int soc_is_sun6i = 0;
> +#ifdef CONFIG_SUN6I
> +	soc_is_sun6i = 1;
> +#endif
> +	if (SOC_IS_SUN7I() || soc_is_sun6i) {
> +		/* Enable SMP mode for CPU0, by setting bit 6 of
> +		 * Auxiliary Ctl reg */
> +		asm volatile(
> +			"mrc p15, 0, r0, c1, c0, 1\n"
> +			"orr r0, r0, #1 << 6\n"
> +			"mcr p15, 0, r0, c1, c0, 1\n" : : : "r0");
> +	}
>  #endif
>  
>  	clock_init();

Please just drop the sun6i support here, it got copied over from the sunxi repo
where there is some rudimentary sun6i support, but with your patch it clearly only
gets in the way, so please drop it and we'll re-add it when we add proper sun6i
support.


> diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
> index ecbdb01..1af285e 100644
> --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
> +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
> @@ -35,9 +35,10 @@ void clock_init_safe(void)
>  	       APB0_DIV_1 << APB0_DIV_SHIFT |
>  	       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
>  	       &ccm->cpu_ahb_apb0_cfg);
> -#ifdef CONFIG_SUN7I
> -	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
> -#endif
> +
> +	if (SOC_IS_SUN7I())
> +		setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
> +
>  	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
>  #ifdef CONFIG_SUNXI_AHCI
>  	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
> diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c
> index 5cf35ac..1134b21 100644
> --- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
> +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
> @@ -13,22 +13,28 @@
>  #ifdef CONFIG_DISPLAY_CPUINFO
>  int print_cpuinfo(void)
>  {
> -#ifdef CONFIG_SUN4I
> -	puts("CPU:   Allwinner A10 (SUN4I)\n");
> -#elif defined CONFIG_SUN5I
> -	u32 val = readl(SUNXI_SID_BASE + 0x08);
> -	switch ((val >> 12) & 0xf) {
> -	case 0: puts("CPU:   Allwinner A12 (SUN5I)\n"); break;
> -	case 3: puts("CPU:   Allwinner A13 (SUN5I)\n"); break;
> -	case 7: puts("CPU:   Allwinner A10s (SUN5I)\n"); break;
> -	default: puts("CPU:   Allwinner A1X (SUN5I)\n");
> +	if (SOC_IS_SUN4I()) {
> +		puts("CPU:   Allwinner A10 (SUN4I)\n");
> +	} else if (SOC_IS_SUN5I()) {
> +		u32 val = readl(SUNXI_SID_BASE + 0x08);
> +		switch ((val >> 12) & 0xf) {
> +		case 0:
> +			puts("CPU:   Allwinner A12 (SUN5I)\n");
> +			break;
> +		case 3:
> +			puts("CPU:   Allwinner A13 (SUN5I)\n");
> +			break;
> +		case 7:
> +			puts("CPU:   Allwinner A10s (SUN5I)\n");
> +			break;
> +		default:
> +			puts("CPU:   Allwinner A1X (SUN5I)\n");
> +		}

In the second patch you add a similar check for A13 to get the
console-index. I would like to see this re-factored to
look something like this:

		if (sunxi_is_a13())
			puts("CPU:   Allwinner A12 (SUN5I)\n");
		else if (sunxi_is_a10s())
			puts("CPU:   Allwinner A12 (SUN5I)\n");
		else
			puts("CPU:   Allwinner A1x (SUN5I)\n");


So add 2 new functions called sunxi_is_a13 and sunxi_is_a10s
to abstract away the SID check, and then also use
sunxi_is_a13 for the console_index setting. Instead of duplicating
the SID check code there.

Note I think this is best done in a separate patch, rather then
added to one of the 2 from this set.

> +	} else if (SOC_IS_SUN7I()) {
> +		puts("CPU:   Allwinner A20 (SUN7I)\n");
> +	} else {
> +		puts("CPU:   SUNXI Family\n");
>  	}
> -#elif defined CONFIG_SUN7I
> -	puts("CPU:   Allwinner A20 (SUN7I)\n");
> -#else
> -#warning Please update cpu_info.c with correct CPU information
> -	puts("CPU:   SUNXI Family\n");
> -#endif
>  	return 0;
>  }
>  #endif
> diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
> index 584f742..05cd66f 100644
> --- a/arch/arm/cpu/armv7/sunxi/dram.c
> +++ b/arch/arm/cpu/armv7/sunxi/dram.c
> @@ -74,22 +74,23 @@ static void mctl_ddr3_reset(void)
>  	struct sunxi_dram_reg *dram =
>  			(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
>  
> -#ifdef CONFIG_SUN4I
>  	struct sunxi_timer_reg *timer =
>  			(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
>  	u32 reg_val;
> -
> -	writel(0, &timer->cpu_cfg);
> -	reg_val = readl(&timer->cpu_cfg);
> -
> -	if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
> -	    CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
> -		setbits_le32(&dram->mcr, DRAM_MCR_RESET);
> -		udelay(200);
> -		clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
> -	} else
> -#endif
> -	{
> +	int reset_done = 0;
> +
> +	if (SOC_IS_SUN4I()) {
> +		writel(0, &timer->cpu_cfg);
> +		reg_val = readl(&timer->cpu_cfg);
> +		if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
> +		    CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
> +			setbits_le32(&dram->mcr, DRAM_MCR_RESET);
> +			udelay(200);
> +			clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
> +			reset_done = 1;
> +		}
> +	}
> +	if (!reset_done) {
>  		clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
>  		udelay(200);
>  		setbits_le32(&dram->mcr, DRAM_MCR_RESET);

I would prefer to see this refactored using a dram_mcr_reset_is_inverted
flag, set that for sun4i revision A and then have:

	if (dram_mcr_reset_is_inverted) {
  		setbits_le32(&dram->mcr, DRAM_MCR_RESET);
  		udelay(200);
  		clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
	} else {
  		clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
  		udelay(200);
  		setbits_le32(&dram->mcr, DRAM_MCR_RESET);
	}


> @@ -112,14 +113,10 @@ static void mctl_ddr3_reset(void)
>  static void mctl_set_drive(void)
>  {
>  	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
> -
> -#ifdef CONFIG_SUN7I
> -	clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
> -#else
> -	clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
> -#endif
> -			DRAM_MCR_MODE_EN(0x3) |
> -			0xffc);
> +	clrsetbits_le32(&dram->mcr,
> +			DRAM_MCR_MODE_NORM(0x3) |
> +					(SOC_IS_SUN7I() ? (0x3 << 28) : 0),
> +			DRAM_MCR_MODE_EN(0x3) | 0xffc);
>  }
>  
>  static void mctl_itm_disable(void)
> @@ -201,8 +198,7 @@ static void mctl_enable_dllx(u32 phase)
>  	udelay(22);
>  }
>  
> -static u32 hpcr_value[32] = {
> -#ifdef CONFIG_SUN5I
> +static u32 hpcr_value_sun5i[32] = {
>  	0, 0, 0, 0,
>  	0, 0, 0, 0,
>  	0, 0, 0, 0,
> @@ -211,8 +207,9 @@ static u32 hpcr_value[32] = {
>  	0x1035, 0x0731, 0x1031, 0,
>  	0x0301, 0x0301, 0x0301, 0x0301,
>  	0x0301, 0x0301, 0x0301, 0
> -#endif
> -#ifdef CONFIG_SUN4I
> +};
> +
> +static u32 hpcr_value_sun4i[32] = {
>  	0x0301, 0x0301, 0x0301, 0x0301,
>  	0x0301, 0x0301, 0, 0,
>  	0, 0, 0, 0,
> @@ -221,8 +218,9 @@ static u32 hpcr_value[32] = {
>  	0x1035, 0x0731, 0x1031, 0x0735,
>  	0x1035, 0x1031, 0x0731, 0x1035,
>  	0x1031, 0x0301, 0x0301, 0x0731
> -#endif
> -#ifdef CONFIG_SUN7I
> +};
> +
> +static u32 hpcr_value_sun7i[32] = {
>  	0x0301, 0x0301, 0x0301, 0x0301,
>  	0x0301, 0x0301, 0x0301, 0x0301,
>  	0, 0, 0, 0,
> @@ -236,13 +234,21 @@ static u32 hpcr_value[32] = {
>  	 * but boot0 code skips #28 and #30, and sets #29 and #31 to the
>  	 * value from #28 entry (0x1031)
>  	 */
> -#endif
>  };
>  
>  static void mctl_configure_hostport(void)
>  {
>  	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
>  	u32 i;
> +	u32 *hpcr_value;
> +	if (SOC_IS_SUN4I())
> +		hpcr_value = hpcr_value_sun4i;
> +	else if (SOC_IS_SUN5I())
> +		hpcr_value = hpcr_value_sun5i;
> +	else if (SOC_IS_SUN7I())
> +		hpcr_value = hpcr_value_sun7i;
> +	else
> +		panic("Can't detect the SoC type");
>  
>  	for (i = 0; i < 32; i++)
>  		writel(hpcr_value[i], &dram->hpcr[i]);
> @@ -258,9 +264,8 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
>  	u32 pll6x_clk = clock_get_pll6() / 1000000;
>  	u32 pll5p_clk = clk / 24 * 48;
>  	u32 pll5p_rate, pll6x_rate;
> -#ifdef CONFIG_SUN7I
> -	pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
> -#endif
> +	if (SOC_IS_SUN7I())
> +		pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
>  
>  	/* setup DRAM PLL */
>  	reg_val = readl(&ccm->pll5_cfg);
> @@ -311,13 +316,14 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
>  
>  	setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK);
>  
> -#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
> -	/* reset GPS */
> -	clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);
> -	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
> -	udelay(1);
> -	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
> -#endif
> +	if (SOC_IS_SUN4I() || SOC_IS_SUN7I()) {
> +		/* reset GPS */
> +		clrbits_le32(&ccm->gps_clk_cfg,
> +			     CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);
> +		setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
> +		udelay(1);
> +		clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
> +	}
>  
>  	/* setup MBUS clock */
>  	if (!mbus_clk)
> @@ -348,19 +354,15 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
>  	 * open DRAMC AHB & DLL register clock
>  	 * close it first
>  	 */
> -#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
> -	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
> -#else
> -	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
> -#endif
> +	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM |
> +		((SOC_IS_SUN5I() || SOC_IS_SUN7I()) ? CCM_AHB_GATE_DLL : 0));
> +
>  	udelay(22);
>  
>  	/* then open it */
> -#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
> -	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
> -#else
> -	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
> -#endif
> +	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM |
> +		((SOC_IS_SUN5I() || SOC_IS_SUN7I()) ? CCM_AHB_GATE_DLL : 0));
> +
>  	udelay(22);
>  }
>  
> @@ -417,21 +419,23 @@ static int dramc_scan_readpipe(void)
>  
>  static void dramc_clock_output_en(u32 on)
>  {
> -#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
>  	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
> -
> -	if (on)
> -		setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
> -	else
> -		clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
> -#endif
> -#ifdef CONFIG_SUN4I
>  	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> -	if (on)
> -		setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
> -	else
> -		clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
> -#endif
> +
> +	if (SOC_IS_SUN5I() || SOC_IS_SUN7I()) {
> +		if (on)
> +			setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
> +		else
> +			clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
> +	}
> +	if (SOC_IS_SUN4I()) {
> +		if (on)
> +			setbits_le32(&ccm->dram_clk_cfg,
> +				     CCM_DRAM_CTRL_DCLK_OUT);
> +		else
> +			clrbits_le32(&ccm->dram_clk_cfg,
> +				     CCM_DRAM_CTRL_DCLK_OUT);
> +	}
>  }
>  
>  /* tRFC in nanoseconds for different densities (from the DDR3 spec) */
> @@ -527,27 +531,25 @@ static void mctl_set_impedance(u32 zq, u32 odt_en)
>  	u32 reg_val;
>  	u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF;
>  
> -#ifndef CONFIG_SUN7I
>  	/* Appears that some kind of automatically initiated default
>  	 * ZQ calibration is already in progress at this point on sun4i/sun5i
>  	 * hardware, but not on sun7i. So it is reasonable to wait for its
>  	 * completion before doing anything else. */
> -	await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);
> -#endif
> +	if (!SOC_IS_SUN7I())
> +		await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);
>  
>  	/* ZQ calibration is not really useful unless ODT is enabled */
>  	if (!odt_en)
>  		return;
>  
> -#ifdef CONFIG_SUN7I
>  	/* Enabling ODT in SDR_IOCR on sun7i hardware results in a deadlock
>  	 * unless bit 24 is set in SDR_ZQCR1. Not much is known about the
>  	 * SDR_ZQCR1 register, but there are hints indicating that it might
>  	 * be related to periodic impedance re-calibration. This particular
>  	 * magic value is borrowed from the Allwinner boot0 bootloader, and
>  	 * using it helps to avoid troubles */
> -	writel((1 << 24) | (1 << 1), &dram->zqcr1);
> -#endif
> +	if (SOC_IS_SUN7I())
> +		writel((1 << 24) | (1 << 1), &dram->zqcr1);
>  
>  	/* Needed at least for sun5i, because it does not self clear there */
>  	clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);
> @@ -597,10 +599,10 @@ static unsigned long dramc_init_helper(struct dram_para *para)
>  	/* dram clock off */
>  	dramc_clock_output_en(0);
>  
> -#ifdef CONFIG_SUN4I
> -	/* select dram controller 1 */
> -	writel(DRAM_CSEL_MAGIC, &dram->csel);
> -#endif
> +	if (SOC_IS_SUN4I()) {
> +		/* select dram controller 1 */
> +		writel(DRAM_CSEL_MAGIC, &dram->csel);
> +	}
>  
>  	mctl_itm_disable();
>  	mctl_enable_dll0(para->tpr3);
> @@ -654,9 +656,8 @@ static unsigned long dramc_init_helper(struct dram_para *para)
>  	writel(para->tpr2, &dram->tpr2);
>  
>  	reg_val = DRAM_MR_BURST_LENGTH(0x0);
> -#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
> -	reg_val |= DRAM_MR_POWER_DOWN;
> -#endif
> +	if (SOC_IS_SUN5I() || SOC_IS_SUN7I())
> +		reg_val |= DRAM_MR_POWER_DOWN;
>  	reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
>  	reg_val |= DRAM_MR_WRITE_RECOVERY(ddr3_write_recovery(para->clock));
>  	writel(reg_val, &dram->mr);
> @@ -668,11 +669,10 @@ static unsigned long dramc_init_helper(struct dram_para *para)
>  	/* disable drift compensation and set passive DQS window mode */
>  	clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
>  
> -#ifdef CONFIG_SUN7I
>  	/* Command rate timing mode 2T & 1T */
> -	if (para->tpr4 & 0x1)
> +	if (SOC_IS_SUN7I() && (para->tpr4 & 0x1))
>  		setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
> -#endif
> +
>  	/* initialize external DRAM */
>  	mctl_ddr3_initialize();
>  
> @@ -718,13 +718,16 @@ unsigned long dramc_init(struct dram_para *para)
>  	/* try to autodetect the DRAM bus width and density */
>  	para->io_width  = 16;
>  	para->bus_width = 32;
> -#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I)
> -	/* only A0-A14 address lines on A10/A13, limiting max density to 4096 */
> -	para->density = 4096;
> -#else
> -	/* all A0-A15 address lines on A20, which allow density 8192 */
> -	para->density = 8192;
> -#endif
> +
> +	if (SOC_IS_SUN4I() || SOC_IS_SUN5I()) {
> +		/* only A0-A14 address lines on A10/A13,
> +		 * limiting max density to 4096 */
> +		para->density = 4096;
> +	} else {
> +		/* all A0-A15 address lines on A20,
> +		 * which allow density 8192 */
> +		para->density = 8192;
> +	}
>  
>  	dram_size = dramc_init_helper(para);
>  	if (!dram_size) {
> diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h
> index 5611ecc..d08804c 100644
> --- a/include/configs/sun4i.h
> +++ b/include/configs/sun4i.h
> @@ -14,6 +14,8 @@
>  #define CONFIG_SUN4I		/* sun4i SoC generation */
>  #define CONFIG_CLK_FULL_SPEED		1008000000
>  
> +#define SOC_IS_SUN4I() 1
> +
>  #define CONFIG_SYS_PROMPT		"sun4i# "
>  
>  #ifdef CONFIG_USB_EHCI
> diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h
> index 6066371..b6c0669 100644
> --- a/include/configs/sun5i.h
> +++ b/include/configs/sun5i.h
> @@ -14,6 +14,8 @@
>  #define CONFIG_SUN5I		/* sun5i SoC generation */
>  #define CONFIG_CLK_FULL_SPEED		1008000000
>  
> +#define SOC_IS_SUN5I() 1
> +
>  #define CONFIG_SYS_PROMPT		"sun5i# "
>  
>  #ifdef CONFIG_USB_EHCI
> diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
> index a902b84..d3f0322 100644
> --- a/include/configs/sun7i.h
> +++ b/include/configs/sun7i.h
> @@ -15,6 +15,8 @@
>  #define CONFIG_SUN7I		/* sun7i SoC generation */
>  #define CONFIG_CLK_FULL_SPEED		912000000
>  
> +#define SOC_IS_SUN7I() 1
> +
>  #define CONFIG_SYS_PROMPT		"sun7i# "
>  
>  #ifdef CONFIG_USB_EHCI
> diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
> index 6a3044f..267bf2a 100644
> --- a/include/configs/sunxi-common.h
> +++ b/include/configs/sunxi-common.h
> @@ -13,6 +13,18 @@
>  #ifndef _SUNXI_COMMON_CONFIG_H
>  #define _SUNXI_COMMON_CONFIG_H
>  
> +#ifndef SOC_IS_SUN4I
> +#define SOC_IS_SUN4I() 0
> +#endif
> +
> +#ifndef SOC_IS_SUN5I
> +#define SOC_IS_SUN5I() 0
> +#endif
> +
> +#ifndef SOC_IS_SUN7I
> +#define SOC_IS_SUN7I() 0
> +#endif
> +
>  /*
>   * High Level Configuration Options
>   */
> 


Regards,

Hans