From: Stefano Babic <sbabic@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 09/11] imx: ventana: enable SION bit on gpio outputs
Date: Wed, 20 Aug 2014 13:02:48 +0200 [thread overview]
Message-ID: <53F48058.8090703@denx.de> (raw)
In-Reply-To: <1407476151-5603-10-git-send-email-tharvey@gateworks.com>
Hi Tim,
On 08/08/2014 07:35, Tim Harvey wrote:
> Enable the SION bit on gpio outputs that we wish to be able to read the
> value of.
>
> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
> ---
> board/gateworks/gw_ventana/gw_ventana.c | 133 +++++++++++++++++---------------
> 1 file changed, 70 insertions(+), 63 deletions(-)
>
> diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
> index 98ee9df..d57ede4 100644
> --- a/board/gateworks/gw_ventana/gw_ventana.c
> +++ b/board/gateworks/gw_ventana/gw_ventana.c
> @@ -74,6 +74,13 @@ DECLARE_GLOBAL_DATA_PTR;
> PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
> PAD_CTL_ODE | PAD_CTL_SRE_FAST)
>
> +#define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
> +
> +#define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION)
> +
> +
> /*
> * EEPROM board info struct populated by read_eeprom so that we only have to
> * read it once.
> @@ -183,7 +190,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
> IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> /* CD */
> - IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
> };
>
> /* ENET */
> @@ -207,7 +214,7 @@ iomux_v3_cfg_t const enet_pads[] = {
> IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> /* PHY nRST */
> - IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
> };
>
> /* NAND */
> @@ -277,10 +284,10 @@ static void setup_iomux_uart(void)
>
> #ifdef CONFIG_USB_EHCI_MX6
> iomux_v3_cfg_t const usb_pads[] = {
> - IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(DIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL)),
> + IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
> + IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
> /* OTG PWR */
> - IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(DIO_PAD_CTRL)),
> + IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
> };
>
> int board_ehci_hcd_init(int port)
> @@ -292,15 +299,13 @@ int board_ehci_hcd_init(int port)
> /* Reset USB HUB (present on GW54xx/GW53xx) */
> switch (info->model[3]) {
> case '3': /* GW53xx */
> - SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 |
> - MUX_PAD_CTRL(NO_PAD_CTRL));
> + SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
> gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
> mdelay(2);
> gpio_set_value(IMX_GPIO_NR(1, 9), 1);
> break;
> case '4': /* GW54xx */
> - SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 |
> - MUX_PAD_CTRL(NO_PAD_CTRL));
> + SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG);
> gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
> mdelay(2);
> gpio_set_value(IMX_GPIO_NR(1, 16), 1);
> @@ -422,7 +427,7 @@ static void enable_lvds(struct display_info_t const *dev)
> writel(reg, &iomux->gpr[2]);
>
> /* Enable Backlight */
> - SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL));
> + SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
> gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
> }
>
> @@ -519,7 +524,7 @@ static void setup_display(void)
> writel(reg, &iomux->gpr[3]);
>
> /* Backlight CABEN on LVDS connector */
> - SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL));
> + SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
> gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
> }
> #endif /* CONFIG_VIDEO_IPUV3 */
> @@ -531,120 +536,120 @@ static void setup_display(void)
> /* common to add baseboards */
> static iomux_v3_cfg_t const gw_gpio_pads[] = {
> /* MSATA_EN */
> - IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
> /* RS232_EN# */
> - IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
> };
>
> /* prototype */
> static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
> /* PANLEDG# */
> - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
> /* PANLEDR# */
> - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
> /* LOCLED# */
> - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
> /* RS485_EN */
> - IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
> /* IOEXP_PWREN# */
> - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
> /* IOEXP_IRQ# */
> - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
> /* VID_EN */
> - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
> /* DIOI2C_DIS# */
> - IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
> /* PCICK_SSON */
> - IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
> /* PCI_RST# */
> - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
> };
>
> static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
> /* PANLEDG# */
> - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
> /* PANLEDR# */
> - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
> /* IOEXP_PWREN# */
> - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
> /* IOEXP_IRQ# */
> - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
>
> /* GPS_SHDN */
> - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
> /* VID_PWR */
> - IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
> /* PCI_RST# */
> - IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
> };
>
> static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
> /* PANLEDG# */
> - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
> /* PANLEDR# */
> - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
> /* IOEXP_PWREN# */
> - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
> /* IOEXP_IRQ# */
> - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
>
> /* MX6_LOCLED# */
> - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
> /* GPS_SHDN */
> - IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
> /* USBOTG_SEL */
> - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
> /* VID_PWR */
> - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
> /* PCI_RST# */
> - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
> };
>
> static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
> /* PANLEDG# */
> - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
> /* PANLEDR# */
> - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
> /* IOEXP_PWREN# */
> - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
> /* IOEXP_IRQ# */
> - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
> /* DIOI2C_DIS# */
> - IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
>
> /* MX6_LOCLED# */
> - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
> /* GPS_SHDN */
> - IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
> /* VID_EN */
> - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
> /* PCI_RST# */
> - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
> };
>
> static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
> /* PANLEDG# */
> - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
> /* PANLEDR# */
> - IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
> /* MX6_LOCLED# */
> - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
> /* MIPI_DIO */
> - IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
> /* RS485_EN */
> - IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
> /* IOEXP_PWREN# */
> - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
> /* IOEXP_IRQ# */
> - IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
> /* DIOI2C_DIS# */
> - IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
> /* PCICK_SSON */
> - IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
> /* PCI_RST# */
> - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
> /* VID_EN */
> - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
> };
>
> /*
> @@ -1020,15 +1025,17 @@ static void setup_board_gpio(int board)
> */
> for (i = 0; i < 4; i++) {
> struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
> - unsigned ctrl = DIO_PAD_CTRL;
> + iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
> unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
>
> sprintf(arg, "dio%d", i);
> if (!hwconfig(arg))
> continue;
> s = hwconfig_subarg(arg, "padctrl", &len);
> - if (s)
> - ctrl = simple_strtoul(s, NULL, 16) & 0x3ffff;
> + if (s) {
> + ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16)
> + & 0x1ffff) | MUX_MODE_SION;
> + }
> if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
> if (!quiet) {
> printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
> @@ -1037,7 +1044,7 @@ static void setup_board_gpio(int board)
> cfg->gpio_param);
> }
> imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
> - MUX_PAD_CTRL(ctrl));
> + ctrl);
> gpio_direction_input(cfg->gpio_param);
> } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
> cfg->pwm_padmux) {
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
next prev parent reply other threads:[~2014-08-20 11:02 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-08 5:35 [U-Boot] [PATCH 00/11] imx: ventana: misc patches Tim Harvey
2014-08-08 5:35 ` [U-Boot] [PATCH 01/11] imx: ventana: set dynamic env var for flash layout Tim Harvey
2014-08-20 10:52 ` Stefano Babic
2014-08-08 5:35 ` [U-Boot] [PATCH 02/11] imx: ventana: added cputype env var Tim Harvey
2014-08-14 15:23 ` Stefano Babic
2014-08-18 13:52 ` Tim Harvey
2014-08-20 10:51 ` Stefano Babic
2014-09-09 13:19 ` Stefano Babic
2014-08-08 5:35 ` [U-Boot] [PATCH 03/11] imx: ventana: remove caam disable per eeprom bit Tim Harvey
2014-08-20 10:53 ` Stefano Babic
2014-08-08 5:35 ` [U-Boot] [PATCH 04/11] imx: ventana: add appropriate delay following GSC i2c write Tim Harvey
2014-08-20 10:54 ` Stefano Babic
2014-08-08 5:35 ` [U-Boot] [PATCH 05/11] imx: ventana: add econfig command Tim Harvey
2014-08-20 11:09 ` Stefano Babic
2014-08-08 5:35 ` [U-Boot] [PATCH 06/11] imx: ventana: add video enable gpio pinmux for GW54xx Tim Harvey
2014-08-20 10:59 ` Stefano Babic
2014-08-08 5:35 ` [U-Boot] [PATCH 07/11] imx: ventana: add missing crlf to print Tim Harvey
2014-08-20 11:00 ` Stefano Babic
2014-08-08 5:35 ` [U-Boot] [PATCH 08/11] imx: ventana: configure i2c_dis# pin properly for gw53xx Tim Harvey
2014-08-20 11:02 ` Stefano Babic
2014-08-08 5:35 ` [U-Boot] [PATCH 09/11] imx: ventana: enable SION bit on gpio outputs Tim Harvey
2014-08-20 11:02 ` Stefano Babic [this message]
2014-08-08 5:35 ` [U-Boot] [PATCH 10/11] imx: ventana: add iomux for PCISKT_WDIS# gpio Tim Harvey
2014-08-20 11:03 ` Stefano Babic
2014-08-08 5:35 ` [U-Boot] [PATCH 11/11] imx: ventana: leave PCI reset de-asserted if PCI enabled Tim Harvey
2014-08-20 11:05 ` Stefano Babic
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