[U-Boot] [PATCH 1/2] mx6sx: Adjust enable_fec_anatop_clock() for mx6solox

[Stefano Babic <sbabic@denx.de>]

Hi Fabio,

On 15/08/2014 05:24, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
> 
> Configure and enable the ethernet clock for mx6solox.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
>  arch/arm/cpu/armv7/mx6/clock.c | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
> index abd9d61..820b8d5 100644
> --- a/arch/arm/cpu/armv7/mx6/clock.c
> +++ b/arch/arm/cpu/armv7/mx6/clock.c
> @@ -373,6 +373,27 @@ int enable_fec_anatop_clock(enum enet_freq freq)
>  	reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
>  	writel(reg, &anatop->pll_enet);
>  
> +#ifdef CONFIG_MX6SX
> +	/*
> +	 * Set enet ahb clock to 200MHz
> +	 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
> +	 */
> +	reg = readl(&imx_ccm->chsccdr);
> +	reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
> +		 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
> +		 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
> +	/* PLL2 PFD2 */
> +	reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
> +	/* Div = 2*/
> +	reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
> +	reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
> +	writel(reg, &imx_ccm->chsccdr);
> +
> +	/* Enable enet system clock */
> +	reg = readl(&imx_ccm->CCGR3);
> +	reg |= MXC_CCM_CCGR3_ENET_MASK;
> +	writel(reg, &imx_ccm->CCGR3);
> +#endif
>  	return 0;
>  }
>  #endif
> 

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

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