From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tuomas Tynkkynen Date: Wed, 27 Aug 2014 19:52:36 +0300 Subject: [U-Boot] [PATCH 23/23] ARM: tegra: Enable PCIe on Jetson TK1 In-Reply-To: <20140827143431.GD32243@ulmo> References: <1408346196-30419-1-git-send-email-thierry.reding@gmail.com> <1408346196-30419-24-git-send-email-thierry.reding@gmail.com> <53FC839A.7030108@nvidia.com> <20140827132800.GA32243@ulmo> <20140827143431.GD32243@ulmo> Message-ID: <53FE0CD4.9060700@nvidia.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 27/08/14 17:34, Thierry Reding wrote: [...] >>> On my board, this call results in UART corruption, like this: >>> >>> tegra-pcie: non-prefetchable memory: 0x13000000-0x20000000 >>> tegra-pcie: prefetchable memory: 0x20000000-0x40000000 >>> ??????b????b2x1, 1x1 configuration >>> ??5R?tegra-pcie: probing port 1, using 1 lanes >>> >>> Likely because GPIO#2 controls the +3.3V_LP0 rail, which powers the UART >>> level shifters. Commenting the function call out fixes the corruption and >>> PCI-E still works fine. >> >> If I add a udelay(500) after the above I'm not able to reproduce the >> UART breakage anymore. But I guess making the AS3722 GPIO code smarter >> would be helpful. In the kernel this is done by checking the invert bit >> and then setting the value accordingly. I suppose the same could be done >> for the mode bits. I'll see if I can work up a patch. > > How about this: [...] Yes, that helps. -- nvpublic