* [U-Boot] [U-boot] [Patch 0/6] Add support for k2e SoC and EVM
@ 2014-07-15 21:59 Ivan Khoronzhuk
2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 1/6] ARM: keystone2: add K2E SoC hardware definitions Ivan Khoronzhuk
` (5 more replies)
0 siblings, 6 replies; 16+ messages in thread
From: Ivan Khoronzhuk @ 2014-07-15 21:59 UTC (permalink / raw)
To: u-boot
This series adds support for Keystone2 K2E SoC and k2e_evm evaluation board.
Based on "Generalize Keystone2 code for other SoC types" series.
https://www.mail-archive.com/u-boot at lists.denx.de/msg142007.html
Hao Zhang (4):
ARM: keystone2: add K2E SoC hardware definitions
ARM: keystone2: clock: add K2E clock support
ARM: keystone2: add MSMC cache coherency support for K2E SOC
board: k2e-evm: add board support
Ivan Khoronzhuk (2):
keystone2: use CONFIG_SOC_KEYSTONE in common places
ARM: keystone2: spl: add K2E SoC support
arch/arm/cpu/armv7/keystone/Makefile | 1 +
arch/arm/cpu/armv7/keystone/clock-k2e.c | 101 +++++++++++++++++++++
arch/arm/cpu/armv7/keystone/clock.c | 2 +
arch/arm/cpu/armv7/keystone/cmd_clock.c | 31 ++++++-
arch/arm/cpu/armv7/keystone/init.c | 12 ++-
arch/arm/cpu/armv7/keystone/msmc.c | 4 +-
arch/arm/cpu/armv7/keystone/spl.c | 8 ++
arch/arm/include/asm/arch-keystone/clock-k2e.h | 68 ++++++++++++++
arch/arm/include/asm/arch-keystone/clock.h | 4 +
arch/arm/include/asm/arch-keystone/hardware-k2e.h | 44 +++++++++
arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 44 ---------
arch/arm/include/asm/arch-keystone/hardware.h | 63 ++++++++++++-
arch/arm/include/asm/arch-keystone/msmc.h | 17 ++++
board/ti/ks2_evm/Makefile | 2 +
board/ti/ks2_evm/board_k2e.c | 39 ++++++++
board/ti/ks2_evm/ddr3_cfg.c | 40 ++++++++
board/ti/ks2_evm/ddr3_cfg.h | 3 +
board/ti/ks2_evm/ddr3_k2e.c | 55 +++++++++++
boards.cfg | 1 +
common/image-fdt.c | 2 +-
drivers/serial/ns16550.c | 4 +-
include/configs/k2e_evm.h | 37 ++++++++
include/configs/ks2_evm.h | 2 +-
23 files changed, 523 insertions(+), 61 deletions(-)
create mode 100644 arch/arm/cpu/armv7/keystone/clock-k2e.c
create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2e.h
create mode 100644 arch/arm/include/asm/arch-keystone/hardware-k2e.h
create mode 100644 arch/arm/include/asm/arch-keystone/msmc.h
create mode 100644 board/ti/ks2_evm/board_k2e.c
create mode 100644 board/ti/ks2_evm/ddr3_k2e.c
create mode 100644 include/configs/k2e_evm.h
--
1.8.3.2
^ permalink raw reply [flat|nested] 16+ messages in thread* [U-Boot] [U-boot] [Patch 1/6] ARM: keystone2: add K2E SoC hardware definitions 2014-07-15 21:59 [U-Boot] [U-boot] [Patch 0/6] Add support for k2e SoC and EVM Ivan Khoronzhuk @ 2014-07-15 21:59 ` Ivan Khoronzhuk 2014-07-26 1:27 ` [U-Boot] [U-Boot, U-boot, " Tom Rini 2014-07-26 1:27 ` Tom Rini 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 2/6] ARM: keystone2: clock: add K2E clock support Ivan Khoronzhuk ` (4 subsequent siblings) 5 siblings, 2 replies; 16+ messages in thread From: Ivan Khoronzhuk @ 2014-07-15 21:59 UTC (permalink / raw) To: u-boot From: Hao Zhang <hzhang@ti.com> This patch adds hardware definitions specific to Keystone II K2E device. It has a lot common definitions with k2hk SoC, so move them to common hardware.h. This is preparation patch for adding K2E SoC support. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> --- arch/arm/include/asm/arch-keystone/hardware-k2e.h | 44 ++++++++++++++++ arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 44 ---------------- arch/arm/include/asm/arch-keystone/hardware.h | 61 ++++++++++++++++++++++ 3 files changed, 105 insertions(+), 44 deletions(-) create mode 100644 arch/arm/include/asm/arch-keystone/hardware-k2e.h diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h new file mode 100644 index 0000000..62172a4 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/hardware-k2e.h @@ -0,0 +1,44 @@ +/* + * K2E: SoC definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_HARDWARE_K2E_H +#define __ASM_ARCH_HARDWARE_K2E_H + +/* PA SS Registers */ +#define KS2_PASS_BASE 0x24000000 + +/* Power and Sleep Controller (PSC) Domains */ +#define KS2_LPSC_MOD_RST 0 +#define KS2_LPSC_USB_1 1 +#define KS2_LPSC_USB 2 +#define KS2_LPSC_EMIF25_SPI 3 +#define KS2_LPSC_TSIP 4 +#define KS2_LPSC_DEBUGSS_TRC 5 +#define KS2_LPSC_TETB_TRC 6 +#define KS2_LPSC_PKTPROC 7 +#define KS2_LPSC_PA KS2_LPSC_PKTPROC +#define KS2_LPSC_SGMII 8 +#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII +#define KS2_LPSC_CRYPTO 9 +#define KS2_LPSC_PCIE 10 +#define KS2_LPSC_VUSR0 12 +#define KS2_LPSC_CHIP_SRSS 13 +#define KS2_LPSC_MSMC 14 +#define KS2_LPSC_EMIF4F_DDR3 23 +#define KS2_LPSC_PCIE_1 27 +#define KS2_LPSC_XGE 50 + +/* Chip Interrupt Controller */ +#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */ +#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */ + +/* Number of DSP cores */ +#define KS2_NUM_DSPS 1 + +#endif diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h index e7dff05..eb132f7 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h @@ -10,46 +10,16 @@ #ifndef __ASM_ARCH_HARDWARE_K2HK_H #define __ASM_ARCH_HARDWARE_K2HK_H -#define KS2_PLL_CNTRL_BASE 0x02310000 -#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE -#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8) -#define KS2_RSTCTRL_KEY 0x5a69 -#define KS2_RSTCTRL_MASK 0xffff0000 -#define KS2_RSTCTRL_SWRST 0xfffe0000 - -#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000 -#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18) -#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20) - #define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c) #define KS2_ARM_PLL_EN BIT(13) -#define KS2_SPI0_BASE 0x21000400 -#define KS2_SPI1_BASE 0x21000600 -#define KS2_SPI2_BASE 0x21000800 -#define KS2_SPI_BASE KS2_SPI0_BASE - -/* Chip configuration unlock codes and registers */ -#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38) -#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c) -#define KS2_KICK0_MAGIC 0x83e70b13 -#define KS2_KICK1_MAGIC 0x95a4f1e0 - /* PA SS Registers */ #define KS2_PASS_BASE 0x02000000 /* PLL control registers */ -#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350) -#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354) -#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358) -#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C) -#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360) -#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364) #define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368) #define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C) -#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370) -#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374) /* Power and Sleep Controller (PSC) Domains */ #define KS2_LPSC_MOD 0 @@ -106,25 +76,11 @@ #define KS2_LPSC_XGE 50 #define KS2_LPSC_ARM_SREFLEX 51 -/* DDR3A definitions */ -#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000 -#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000 -#define KS2_DDR3A_DDRPHYC 0x02329000 /* DDR3B definitions */ #define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000 #define KS2_DDR3B_EMIF_DATA_BASE 0x60000000 #define KS2_DDR3B_DDRPHYC 0x02328000 -/* Queue manager */ -#define KS2_QM_MANAGER_BASE 0x02a02000 -#define KS2_QM_DESC_SETUP_BASE 0x02a03000 -#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000 -#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000 -#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000 - -/* MSMC control */ -#define KS2_MSMC_CTRL_BASE 0x0bc00000 - /* Number of DSP cores */ #define KS2_NUM_DSPS 8 diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index 133edad..9c86b69 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -69,6 +69,11 @@ typedef volatile unsigned int *dv_reg_p; #define NOSRA_MASK 0x08000000 #define ECC_MASK 0x00000001 +/* DDR3 definitions */ +#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000 +#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000 +#define KS2_DDR3A_DDRPHYC 0x02329000 + #define KS2_DDR3_MIDR_OFFSET 0x00 #define KS2_DDR3_STATUS_OFFSET 0x04 #define KS2_DDR3_SDCFG_OFFSET 0x08 @@ -85,12 +90,46 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_UART0_BASE 0x02530c00 #define KS2_UART1_BASE 0x02531000 +/* Boot Config */ +#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000 +#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18) +#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20) + /* PSC */ #define KS2_PSC_BASE 0x02350000 #define KS2_LPSC_GEM_0 15 #define KS2_LPSC_TETRIS 52 #define KS2_TETRIS_PWR_DOMAIN 31 +/* Chip configuration unlock codes and registers */ +#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38) +#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c) +#define KS2_KICK0_MAGIC 0x83e70b13 +#define KS2_KICK1_MAGIC 0x95a4f1e0 + +/* PLL control registers */ +#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350) +#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354) +#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358) +#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C) +#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360) +#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364) +#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370) +#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374) + +#define KS2_PLL_CNTRL_BASE 0x02310000 +#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE +#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8) +#define KS2_RSTCTRL_KEY 0x5a69 +#define KS2_RSTCTRL_MASK 0xffff0000 +#define KS2_RSTCTRL_SWRST 0xfffe0000 + +/* SPI */ +#define KS2_SPI0_BASE 0x21000400 +#define KS2_SPI1_BASE 0x21000600 +#define KS2_SPI2_BASE 0x21000800 +#define KS2_SPI_BASE KS2_SPI0_BASE + /* AEMIF */ #define KS2_AEMIF_CNTRL_BASE 0x21000a00 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE @@ -98,10 +137,24 @@ typedef volatile unsigned int *dv_reg_p; /* Flag from ks2_debug options to check if DSPs need to stay ON */ #define DBG_LEAVE_DSPS_ON 0x1 +/* Queue manager */ +#define KS2_QM_MANAGER_BASE 0x02a02000 +#define KS2_QM_DESC_SETUP_BASE 0x02a03000 +#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000 +#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000 +#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000 + +/* MSMC control */ +#define KS2_MSMC_CTRL_BASE 0x0bc00000 + #ifdef CONFIG_SOC_K2HK #include <asm/arch/hardware-k2hk.h> #endif +#ifdef CONFIG_SOC_K2E +#include <asm/arch/hardware-k2e.h> +#endif + #ifndef __ASSEMBLY__ static inline int cpu_is_k2hk(void) { @@ -111,6 +164,14 @@ static inline int cpu_is_k2hk(void) return (part_no == 0xb981) ? 1 : 0; } +static inline int cpu_is_k2e(void) +{ + unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); + unsigned int part_no = (jtag_id >> 12) & 0xffff; + + return (part_no == 0xb9a6) ? 1 : 0; +} + static inline int cpu_revision(void) { unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [U-Boot, U-boot, 1/6] ARM: keystone2: add K2E SoC hardware definitions 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 1/6] ARM: keystone2: add K2E SoC hardware definitions Ivan Khoronzhuk @ 2014-07-26 1:27 ` Tom Rini 2014-07-26 1:27 ` Tom Rini 1 sibling, 0 replies; 16+ messages in thread From: Tom Rini @ 2014-07-26 1:27 UTC (permalink / raw) To: u-boot On Wed, Jul 16, 2014 at 12:59:22AM +0300, Khoronzhuk, Ivan wrote: > From: Hao Zhang <hzhang@ti.com> > > This patch adds hardware definitions specific to Keystone II > K2E device. It has a lot common definitions with k2hk SoC, so > move them to common hardware.h. This is preparation patch for > adding K2E SoC support. > > Acked-by: Murali Karicheri <m-karicheri2@ti.com> > Signed-off-by: Hao Zhang <hzhang@ti.com> > Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Applied to u-boot-ti/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20140725/df91976a/attachment.pgp> ^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [U-Boot, U-boot, 1/6] ARM: keystone2: add K2E SoC hardware definitions 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 1/6] ARM: keystone2: add K2E SoC hardware definitions Ivan Khoronzhuk 2014-07-26 1:27 ` [U-Boot] [U-Boot, U-boot, " Tom Rini @ 2014-07-26 1:27 ` Tom Rini 1 sibling, 0 replies; 16+ messages in thread From: Tom Rini @ 2014-07-26 1:27 UTC (permalink / raw) To: u-boot On Wed, Jul 16, 2014 at 12:59:22AM +0300, Khoronzhuk, Ivan wrote: > From: Hao Zhang <hzhang@ti.com> > > This patch adds hardware definitions specific to Keystone II > K2E device. It has a lot common definitions with k2hk SoC, so > move them to common hardware.h. This is preparation patch for > adding K2E SoC support. > > Acked-by: Murali Karicheri <m-karicheri2@ti.com> > Signed-off-by: Hao Zhang <hzhang@ti.com> > Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Applied to u-boot-ti/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20140725/66b8825d/attachment.pgp> ^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [U-boot] [Patch 2/6] ARM: keystone2: clock: add K2E clock support 2014-07-15 21:59 [U-Boot] [U-boot] [Patch 0/6] Add support for k2e SoC and EVM Ivan Khoronzhuk 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 1/6] ARM: keystone2: add K2E SoC hardware definitions Ivan Khoronzhuk @ 2014-07-15 21:59 ` Ivan Khoronzhuk 2014-07-26 1:27 ` [U-Boot] [U-Boot, U-boot, " Tom Rini 2014-09-04 14:08 ` [U-Boot] [U-boot] [Patch " Murali Karicheri 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 3/6] ARM: keystone2: add MSMC cache coherency support for K2E SOC Ivan Khoronzhuk ` (3 subsequent siblings) 5 siblings, 2 replies; 16+ messages in thread From: Ivan Khoronzhuk @ 2014-07-15 21:59 UTC (permalink / raw) To: u-boot From: Hao Zhang <hzhang@ti.com> This patch adds clock definitions and commands to support Keystone2 K2E SOC. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> --- arch/arm/cpu/armv7/keystone/Makefile | 1 + arch/arm/cpu/armv7/keystone/clock-k2e.c | 101 +++++++++++++++++++++++++ arch/arm/cpu/armv7/keystone/clock.c | 2 + arch/arm/cpu/armv7/keystone/cmd_clock.c | 31 ++++++-- arch/arm/include/asm/arch-keystone/clock-k2e.h | 68 +++++++++++++++++ arch/arm/include/asm/arch-keystone/clock.h | 4 + include/configs/ks2_evm.h | 2 +- 7 files changed, 203 insertions(+), 6 deletions(-) create mode 100644 arch/arm/cpu/armv7/keystone/clock-k2e.c create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2e.h diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile index 74c5160..f8519c0 100644 --- a/arch/arm/cpu/armv7/keystone/Makefile +++ b/arch/arm/cpu/armv7/keystone/Makefile @@ -9,6 +9,7 @@ obj-y += init.o obj-y += psc.o obj-y += clock.o obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o +obj-$(CONFIG_SOC_K2E) += clock-k2e.o obj-y += cmd_clock.o obj-y += cmd_mon.o obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c b/arch/arm/cpu/armv7/keystone/clock-k2e.c new file mode 100644 index 0000000..42092e1 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/clock-k2e.c @@ -0,0 +1,101 @@ +/* + * Keystone2: get clk rate for K2E + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/arch/clock_defs.h> + +const struct keystone_pll_regs keystone_pll_regs[] = { + [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, + [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, + [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, +}; + +/** + * pll_freq_get - get pll frequency + * Fout = Fref * NF(mult) / NR(prediv) / OD + * @pll: pll identifier + */ +static unsigned long pll_freq_get(int pll) +{ + unsigned long mult = 1, prediv = 1, output_div = 2; + unsigned long ret; + u32 tmp, reg; + + if (pll == CORE_PLL) { + ret = external_clk[sys_clk]; + if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) { + /* PLL mode */ + tmp = __raw_readl(KS2_MAINPLLCTL0); + prediv = (tmp & PLL_DIV_MASK) + 1; + mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) | + (pllctl_reg_read(pll, mult) & + PLLM_MULT_LO_MASK)) + 1; + output_div = ((pllctl_reg_read(pll, secctl) >> + PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1; + + ret = ret / prediv / output_div * mult; + } + } else { + switch (pll) { + case PASS_PLL: + ret = external_clk[pa_clk]; + reg = KS2_PASSPLLCTL0; + break; + case DDR3_PLL: + ret = external_clk[ddr3_clk]; + reg = KS2_DDR3APLLCTL0; + break; + default: + return 0; + } + + tmp = __raw_readl(reg); + + if (!(tmp & PLLCTL_BYPASS)) { + /* Bypass disabled */ + prediv = (tmp & PLL_DIV_MASK) + 1; + mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1; + output_div = ((tmp >> PLL_CLKOD_SHIFT) & + PLL_CLKOD_MASK) + 1; + ret = ((ret / prediv) * mult) / output_div; + } + } + + return ret; +} + +unsigned long clk_get_rate(unsigned int clk) +{ + switch (clk) { + case core_pll_clk: return pll_freq_get(CORE_PLL); + case pass_pll_clk: return pll_freq_get(PASS_PLL); + case ddr3_pll_clk: return pll_freq_get(DDR3_PLL); + case sys_clk0_1_clk: + case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1); + case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2); + case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3); + case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4); + case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2; + case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3; + case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4; + case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6; + case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8; + case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12; + case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24; + case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3; + case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4; + case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6; + case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12; + default: + break; + } + + return 0; +} diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c index 42b664b..03c1d9f 100644 --- a/arch/arm/cpu/armv7/keystone/clock.c +++ b/arch/arm/cpu/armv7/keystone/clock.c @@ -106,6 +106,7 @@ void init_pll(const struct pll_init_data *data) tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN); +#ifndef CONFIG_SOC_K2E } else if (data->pll == TETRIS_PLL) { bwadj = pllm >> 1; /* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */ @@ -156,6 +157,7 @@ void init_pll(const struct pll_init_data *data) * only applicable for Kepler */ setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN); +#endif } else { setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT); /* diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c index afd30f3..d97c95b 100644 --- a/arch/arm/cpu/armv7/keystone/cmd_clock.c +++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c @@ -14,10 +14,10 @@ #include <asm/arch/psc_defs.h> struct pll_init_data cmd_pll_data = { - .pll = MAIN_PLL, - .pll_m = 16, - .pll_d = 1, - .pll_od = 2, + .pll = MAIN_PLL, + .pll_m = 16, + .pll_d = 1, + .pll_od = 2, }; int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -27,12 +27,19 @@ int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (strncmp(argv[1], "pa", 2) == 0) cmd_pll_data.pll = PASS_PLL; +#ifndef CONFIG_SOC_K2E else if (strncmp(argv[1], "arm", 3) == 0) cmd_pll_data.pll = TETRIS_PLL; +#endif +#ifdef CONFIG_SOC_K2HK else if (strncmp(argv[1], "ddr3a", 5) == 0) cmd_pll_data.pll = DDR3A_PLL; else if (strncmp(argv[1], "ddr3b", 5) == 0) cmd_pll_data.pll = DDR3B_PLL; +#else + else if (strncmp(argv[1], "ddr3", 4) == 0) + cmd_pll_data.pll = DDR3_PLL; +#endif else goto pll_cmd_usage; @@ -51,11 +58,20 @@ pll_cmd_usage: return cmd_usage(cmdtp); } +#ifdef CONFIG_SOC_K2HK U_BOOT_CMD( pllset, 5, 0, do_pll_cmd, "set pll multiplier and pre divider", "<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n" ); +#endif +#ifdef CONFIG_SOC_K2E +U_BOOT_CMD( + pllset, 5, 0, do_pll_cmd, + "set pll multiplier and pre divider", + "<pa|ddr3> <mult> <div> <OD>\n" +); +#endif int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -79,7 +95,12 @@ U_BOOT_CMD( getclk, 2, 0, do_getclk_cmd, "get clock rate", "<clk index>\n" - "See the 'enum clk_e' in the k2hk clock.h for clk indexes\n" +#ifdef CONFIG_SOC_K2HK + "See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n" +#endif +#ifdef CONFIG_SOC_K2E + "See the 'enum clk_e' in the clock-k2e.h for clk indexes\n" +#endif ); int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h b/arch/arm/include/asm/arch-keystone/clock-k2e.h new file mode 100644 index 0000000..4147811 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/clock-k2e.h @@ -0,0 +1,68 @@ +/* + * K2E: Clock management APIs + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_CLOCK_K2E_H +#define __ASM_ARCH_CLOCK_K2E_H + +enum ext_clk_e { + sys_clk, + alt_core_clk, + pa_clk, + ddr3_clk, + mcm_clk, + pcie_clk, + sgmii_clk, + xgmii_clk, + usb_clk, + ext_clk_count /* number of external clocks */ +}; + +extern unsigned int external_clk[ext_clk_count]; + +enum clk_e { + core_pll_clk, + pass_pll_clk, + ddr3_pll_clk, + sys_clk0_clk, + sys_clk0_1_clk, + sys_clk0_2_clk, + sys_clk0_3_clk, + sys_clk0_4_clk, + sys_clk0_6_clk, + sys_clk0_8_clk, + sys_clk0_12_clk, + sys_clk0_24_clk, + sys_clk1_clk, + sys_clk1_3_clk, + sys_clk1_4_clk, + sys_clk1_6_clk, + sys_clk1_12_clk, + sys_clk2_clk, + sys_clk3_clk +}; + +#define KS2_CLK1_6 sys_clk0_6_clk + +/* PLL identifiers */ +enum pll_type_e { + CORE_PLL, + PASS_PLL, + DDR3_PLL, +}; + +#define CORE_PLL_800 {CORE_PLL, 16, 1, 2} +#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2} +#define CORE_PLL_1200 {CORE_PLL, 24, 1, 2} +#define PASS_PLL_1000 {PASS_PLL, 20, 1, 2} +#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} +#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} +#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} +#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6} + +#endif diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h index c7da352..1513c76 100644 --- a/arch/arm/include/asm/arch-keystone/clock.h +++ b/arch/arm/include/asm/arch-keystone/clock.h @@ -16,6 +16,10 @@ #include <asm/arch/clock-k2hk.h> #endif +#ifdef CONFIG_SOC_K2E +#include <asm/arch/clock-k2e.h> +#endif + #define MAIN_PLL CORE_PLL #include <asm/types.h> diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index 29f0b9b..43db581 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -80,7 +80,7 @@ #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_DAVINCI_SPI #define CONFIG_CMD_SPI -#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_LPSC_EMIF25_SPI) +#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6) #define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED #define CONFIG_SYS_SPI0 -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [U-Boot, U-boot, 2/6] ARM: keystone2: clock: add K2E clock support 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 2/6] ARM: keystone2: clock: add K2E clock support Ivan Khoronzhuk @ 2014-07-26 1:27 ` Tom Rini 2014-09-04 14:08 ` [U-Boot] [U-boot] [Patch " Murali Karicheri 1 sibling, 0 replies; 16+ messages in thread From: Tom Rini @ 2014-07-26 1:27 UTC (permalink / raw) To: u-boot On Wed, Jul 16, 2014 at 12:59:23AM +0300, Khoronzhuk, Ivan wrote: > From: Hao Zhang <hzhang@ti.com> > > This patch adds clock definitions and commands to support Keystone2 > K2E SOC. > > Signed-off-by: Hao Zhang <hzhang@ti.com> > Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Applied to u-boot-ti/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20140725/0bc5c2a7/attachment.pgp> ^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [U-boot] [Patch 2/6] ARM: keystone2: clock: add K2E clock support 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 2/6] ARM: keystone2: clock: add K2E clock support Ivan Khoronzhuk 2014-07-26 1:27 ` [U-Boot] [U-Boot, U-boot, " Tom Rini @ 2014-09-04 14:08 ` Murali Karicheri 2014-09-04 15:04 ` Ivan Khoronzhuk 1 sibling, 1 reply; 16+ messages in thread From: Murali Karicheri @ 2014-09-04 14:08 UTC (permalink / raw) To: u-boot On 07/15/2014 05:59 PM, Ivan Khoronzhuk wrote: > From: Hao Zhang<hzhang@ti.com> > > This patch adds clock definitions and commands to support Keystone2 > K2E SOC. > > Signed-off-by: Hao Zhang<hzhang@ti.com> > Signed-off-by: Ivan Khoronzhuk<ivan.khoronzhuk@ti.com> > --- > arch/arm/cpu/armv7/keystone/Makefile | 1 + > arch/arm/cpu/armv7/keystone/clock-k2e.c | 101 +++++++++++++++++++++++++ > arch/arm/cpu/armv7/keystone/clock.c | 2 + > arch/arm/cpu/armv7/keystone/cmd_clock.c | 31 ++++++-- > arch/arm/include/asm/arch-keystone/clock-k2e.h | 68 +++++++++++++++++ > arch/arm/include/asm/arch-keystone/clock.h | 4 + > include/configs/ks2_evm.h | 2 +- > 7 files changed, 203 insertions(+), 6 deletions(-) > create mode 100644 arch/arm/cpu/armv7/keystone/clock-k2e.c > create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2e.h > > diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile > index 74c5160..f8519c0 100644 > --- a/arch/arm/cpu/armv7/keystone/Makefile > +++ b/arch/arm/cpu/armv7/keystone/Makefile > @@ -9,6 +9,7 @@ obj-y += init.o > obj-y += psc.o > obj-y += clock.o > obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o > +obj-$(CONFIG_SOC_K2E) += clock-k2e.o > obj-y += cmd_clock.o > obj-y += cmd_mon.o > obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o > diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c b/arch/arm/cpu/armv7/keystone/clock-k2e.c > new file mode 100644 > index 0000000..42092e1 > --- /dev/null > +++ b/arch/arm/cpu/armv7/keystone/clock-k2e.c > @@ -0,0 +1,101 @@ > +/* > + * Keystone2: get clk rate for K2E > + * > + * (C) Copyright 2012-2014 > + * Texas Instruments Incorporated,<www.ti.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include<common.h> > +#include<asm/arch/clock.h> > +#include<asm/arch/clock_defs.h> > + > +const struct keystone_pll_regs keystone_pll_regs[] = { > + [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, > + [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, > + [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, > +}; > + > +/** > + * pll_freq_get - get pll frequency > + * Fout = Fref * NF(mult) / NR(prediv) / OD > + * @pll: pll identifier > + */ > +static unsigned long pll_freq_get(int pll) > +{ > + unsigned long mult = 1, prediv = 1, output_div = 2; > + unsigned long ret; > + u32 tmp, reg; > + > + if (pll == CORE_PLL) { > + ret = external_clk[sys_clk]; > + if (pllctl_reg_read(pll, ctl)& PLLCTL_PLLEN) { > + /* PLL mode */ > + tmp = __raw_readl(KS2_MAINPLLCTL0); > + prediv = (tmp& PLL_DIV_MASK) + 1; > + mult = (((tmp& PLLM_MULT_HI_SMASK)>> 6) | > + (pllctl_reg_read(pll, mult)& > + PLLM_MULT_LO_MASK)) + 1; > + output_div = ((pllctl_reg_read(pll, secctl)>> > + PLL_CLKOD_SHIFT)& PLL_CLKOD_MASK) + 1; > + > + ret = ret / prediv / output_div * mult; > + } > + } else { > + switch (pll) { > + case PASS_PLL: > + ret = external_clk[pa_clk]; > + reg = KS2_PASSPLLCTL0; > + break; > + case DDR3_PLL: > + ret = external_clk[ddr3_clk]; > + reg = KS2_DDR3APLLCTL0; > + break; > + default: > + return 0; > + } > + > + tmp = __raw_readl(reg); > + Please remove this line as below is part of this and should be in a block IMO. With this change, Acked-by: Murali Karicheri <m-karicheri2@ti.com> > + if (!(tmp& PLLCTL_BYPASS)) { > + /* Bypass disabled */ > + prediv = (tmp& PLL_DIV_MASK) + 1; > + mult = ((tmp>> PLL_MULT_SHIFT)& PLL_MULT_MASK) + 1; > + output_div = ((tmp>> PLL_CLKOD_SHIFT)& > + PLL_CLKOD_MASK) + 1; > + ret = ((ret / prediv) * mult) / output_div; > + } > + } > + > + return ret; > +} > + > +unsigned long clk_get_rate(unsigned int clk) > +{ > + switch (clk) { > + case core_pll_clk: return pll_freq_get(CORE_PLL); > + case pass_pll_clk: return pll_freq_get(PASS_PLL); > + case ddr3_pll_clk: return pll_freq_get(DDR3_PLL); > + case sys_clk0_1_clk: > + case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1); > + case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2); > + case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3); > + case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4); > + case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2; > + case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3; > + case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4; > + case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6; > + case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8; > + case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12; > + case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24; > + case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3; > + case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4; > + case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6; > + case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12; > + default: > + break; > + } > + > + return 0; > +} > diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c > index 42b664b..03c1d9f 100644 > --- a/arch/arm/cpu/armv7/keystone/clock.c > +++ b/arch/arm/cpu/armv7/keystone/clock.c > @@ -106,6 +106,7 @@ void init_pll(const struct pll_init_data *data) > > tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN); > > +#ifndef CONFIG_SOC_K2E > } else if (data->pll == TETRIS_PLL) { > bwadj = pllm>> 1; > /* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */ > @@ -156,6 +157,7 @@ void init_pll(const struct pll_init_data *data) > * only applicable for Kepler > */ > setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN); > +#endif > } else { > setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT); > /* > diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c > index afd30f3..d97c95b 100644 > --- a/arch/arm/cpu/armv7/keystone/cmd_clock.c > +++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c > @@ -14,10 +14,10 @@ > #include<asm/arch/psc_defs.h> > > struct pll_init_data cmd_pll_data = { > - .pll = MAIN_PLL, > - .pll_m = 16, > - .pll_d = 1, > - .pll_od = 2, > + .pll = MAIN_PLL, > + .pll_m = 16, > + .pll_d = 1, > + .pll_od = 2, > }; > > int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) > @@ -27,12 +27,19 @@ int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) > > if (strncmp(argv[1], "pa", 2) == 0) > cmd_pll_data.pll = PASS_PLL; > +#ifndef CONFIG_SOC_K2E > else if (strncmp(argv[1], "arm", 3) == 0) > cmd_pll_data.pll = TETRIS_PLL; > +#endif > +#ifdef CONFIG_SOC_K2HK > else if (strncmp(argv[1], "ddr3a", 5) == 0) > cmd_pll_data.pll = DDR3A_PLL; > else if (strncmp(argv[1], "ddr3b", 5) == 0) > cmd_pll_data.pll = DDR3B_PLL; > +#else > + else if (strncmp(argv[1], "ddr3", 4) == 0) > + cmd_pll_data.pll = DDR3_PLL; > +#endif > else > goto pll_cmd_usage; > > @@ -51,11 +58,20 @@ pll_cmd_usage: > return cmd_usage(cmdtp); > } > > +#ifdef CONFIG_SOC_K2HK > U_BOOT_CMD( > pllset, 5, 0, do_pll_cmd, > "set pll multiplier and pre divider", > "<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n" > ); > +#endif > +#ifdef CONFIG_SOC_K2E > +U_BOOT_CMD( > + pllset, 5, 0, do_pll_cmd, > + "set pll multiplier and pre divider", > + "<pa|ddr3> <mult> <div> <OD>\n" > +); > +#endif > > int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) > { > @@ -79,7 +95,12 @@ U_BOOT_CMD( > getclk, 2, 0, do_getclk_cmd, > "get clock rate", > "<clk index>\n" > - "See the 'enum clk_e' in the k2hk clock.h for clk indexes\n" > +#ifdef CONFIG_SOC_K2HK > + "See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n" > +#endif > +#ifdef CONFIG_SOC_K2E > + "See the 'enum clk_e' in the clock-k2e.h for clk indexes\n" > +#endif > ); > > int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) > diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h b/arch/arm/include/asm/arch-keystone/clock-k2e.h > new file mode 100644 > index 0000000..4147811 > --- /dev/null > +++ b/arch/arm/include/asm/arch-keystone/clock-k2e.h > @@ -0,0 +1,68 @@ > +/* > + * K2E: Clock management APIs > + * > + * (C) Copyright 2012-2014 > + * Texas Instruments Incorporated,<www.ti.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __ASM_ARCH_CLOCK_K2E_H > +#define __ASM_ARCH_CLOCK_K2E_H > + > +enum ext_clk_e { > + sys_clk, > + alt_core_clk, > + pa_clk, > + ddr3_clk, > + mcm_clk, > + pcie_clk, > + sgmii_clk, > + xgmii_clk, > + usb_clk, > + ext_clk_count /* number of external clocks */ > +}; > + > +extern unsigned int external_clk[ext_clk_count]; > + > +enum clk_e { > + core_pll_clk, > + pass_pll_clk, > + ddr3_pll_clk, > + sys_clk0_clk, > + sys_clk0_1_clk, > + sys_clk0_2_clk, > + sys_clk0_3_clk, > + sys_clk0_4_clk, > + sys_clk0_6_clk, > + sys_clk0_8_clk, > + sys_clk0_12_clk, > + sys_clk0_24_clk, > + sys_clk1_clk, > + sys_clk1_3_clk, > + sys_clk1_4_clk, > + sys_clk1_6_clk, > + sys_clk1_12_clk, > + sys_clk2_clk, > + sys_clk3_clk > +}; > + > +#define KS2_CLK1_6 sys_clk0_6_clk > + > +/* PLL identifiers */ > +enum pll_type_e { > + CORE_PLL, > + PASS_PLL, > + DDR3_PLL, > +}; > + > +#define CORE_PLL_800 {CORE_PLL, 16, 1, 2} > +#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2} > +#define CORE_PLL_1200 {CORE_PLL, 24, 1, 2} > +#define PASS_PLL_1000 {PASS_PLL, 20, 1, 2} > +#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} > +#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} > +#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} > +#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6} > + > +#endif > diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h > index c7da352..1513c76 100644 > --- a/arch/arm/include/asm/arch-keystone/clock.h > +++ b/arch/arm/include/asm/arch-keystone/clock.h > @@ -16,6 +16,10 @@ > #include<asm/arch/clock-k2hk.h> > #endif > > +#ifdef CONFIG_SOC_K2E > +#include<asm/arch/clock-k2e.h> > +#endif > + > #define MAIN_PLL CORE_PLL > > #include<asm/types.h> > diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h > index 29f0b9b..43db581 100644 > --- a/include/configs/ks2_evm.h > +++ b/include/configs/ks2_evm.h > @@ -80,7 +80,7 @@ > #define CONFIG_SPI_FLASH_STMICRO > #define CONFIG_DAVINCI_SPI > #define CONFIG_CMD_SPI > -#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_LPSC_EMIF25_SPI) > +#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6) > #define CONFIG_SF_DEFAULT_SPEED 30000000 > #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED > #define CONFIG_SYS_SPI0 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [U-boot] [Patch 2/6] ARM: keystone2: clock: add K2E clock support 2014-09-04 14:08 ` [U-Boot] [U-boot] [Patch " Murali Karicheri @ 2014-09-04 15:04 ` Ivan Khoronzhuk 0 siblings, 0 replies; 16+ messages in thread From: Ivan Khoronzhuk @ 2014-09-04 15:04 UTC (permalink / raw) To: u-boot On 09/04/2014 05:08 PM, Murali Karicheri wrote: > On 07/15/2014 05:59 PM, Ivan Khoronzhuk wrote: >> From: Hao Zhang<hzhang@ti.com> >> >> This patch adds clock definitions and commands to support Keystone2 >> K2E SOC. >> >> Signed-off-by: Hao Zhang<hzhang@ti.com> >> Signed-off-by: Ivan Khoronzhuk<ivan.khoronzhuk@ti.com> >> --- >> arch/arm/cpu/armv7/keystone/Makefile | 1 + >> arch/arm/cpu/armv7/keystone/clock-k2e.c | 101 >> +++++++++++++++++++++++++ >> arch/arm/cpu/armv7/keystone/clock.c | 2 + >> arch/arm/cpu/armv7/keystone/cmd_clock.c | 31 ++++++-- >> arch/arm/include/asm/arch-keystone/clock-k2e.h | 68 +++++++++++++++++ >> arch/arm/include/asm/arch-keystone/clock.h | 4 + >> include/configs/ks2_evm.h | 2 +- >> 7 files changed, 203 insertions(+), 6 deletions(-) >> create mode 100644 arch/arm/cpu/armv7/keystone/clock-k2e.c >> create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2e.h >> >> diff --git a/arch/arm/cpu/armv7/keystone/Makefile >> b/arch/arm/cpu/armv7/keystone/Makefile >> index 74c5160..f8519c0 100644 >> --- a/arch/arm/cpu/armv7/keystone/Makefile >> +++ b/arch/arm/cpu/armv7/keystone/Makefile >> @@ -9,6 +9,7 @@ obj-y += init.o >> obj-y += psc.o >> obj-y += clock.o >> obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o >> +obj-$(CONFIG_SOC_K2E) += clock-k2e.o >> obj-y += cmd_clock.o >> obj-y += cmd_mon.o >> obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o >> diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c >> b/arch/arm/cpu/armv7/keystone/clock-k2e.c >> new file mode 100644 >> index 0000000..42092e1 >> --- /dev/null >> +++ b/arch/arm/cpu/armv7/keystone/clock-k2e.c >> @@ -0,0 +1,101 @@ >> +/* >> + * Keystone2: get clk rate for K2E >> + * >> + * (C) Copyright 2012-2014 >> + * Texas Instruments Incorporated,<www.ti.com> >> + * >> + * SPDX-License-Identifier: GPL-2.0+ >> + */ >> + >> +#include<common.h> >> +#include<asm/arch/clock.h> >> +#include<asm/arch/clock_defs.h> >> + >> +const struct keystone_pll_regs keystone_pll_regs[] = { >> + [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, >> + [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, >> + [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, >> +}; >> + >> +/** >> + * pll_freq_get - get pll frequency >> + * Fout = Fref * NF(mult) / NR(prediv) / OD >> + * @pll: pll identifier >> + */ >> +static unsigned long pll_freq_get(int pll) >> +{ >> + unsigned long mult = 1, prediv = 1, output_div = 2; >> + unsigned long ret; >> + u32 tmp, reg; >> + >> + if (pll == CORE_PLL) { >> + ret = external_clk[sys_clk]; >> + if (pllctl_reg_read(pll, ctl)& PLLCTL_PLLEN) { >> + /* PLL mode */ >> + tmp = __raw_readl(KS2_MAINPLLCTL0); >> + prediv = (tmp& PLL_DIV_MASK) + 1; >> + mult = (((tmp& PLLM_MULT_HI_SMASK)>> 6) | >> + (pllctl_reg_read(pll, mult)& >> + PLLM_MULT_LO_MASK)) + 1; >> + output_div = ((pllctl_reg_read(pll, secctl)>> >> + PLL_CLKOD_SHIFT)& PLL_CLKOD_MASK) + 1; >> + >> + ret = ret / prediv / output_div * mult; >> + } >> + } else { >> + switch (pll) { >> + case PASS_PLL: >> + ret = external_clk[pa_clk]; >> + reg = KS2_PASSPLLCTL0; >> + break; >> + case DDR3_PLL: >> + ret = external_clk[ddr3_clk]; >> + reg = KS2_DDR3APLLCTL0; >> + break; >> + default: >> + return 0; >> + } >> + >> + tmp = __raw_readl(reg); >> + > Please remove this line as below is part of this and should be in a > block IMO. With this change, > > Acked-by: Murali Karicheri <m-karicheri2@ti.com> Murali, This patch is already applied. I will remove this line in separate patch. Thanks. > + if (!(tmp& PLLCTL_BYPASS)) { >> + /* Bypass disabled */ >> + prediv = (tmp& PLL_DIV_MASK) + 1; >> + mult = ((tmp>> PLL_MULT_SHIFT)& PLL_MULT_MASK) + 1; >> + output_div = ((tmp>> PLL_CLKOD_SHIFT)& >> + PLL_CLKOD_MASK) + 1; >> + ret = ((ret / prediv) * mult) / output_div; >> + } >> + } >> + >> + return ret; >> +} >> + >> +unsigned long clk_get_rate(unsigned int clk) >> +{ >> + switch (clk) { >> + case core_pll_clk: return pll_freq_get(CORE_PLL); >> + case pass_pll_clk: return pll_freq_get(PASS_PLL); >> + case ddr3_pll_clk: return pll_freq_get(DDR3_PLL); >> + case sys_clk0_1_clk: >> + case sys_clk0_clk: return pll_freq_get(CORE_PLL) / >> pll0div_read(1); >> + case sys_clk1_clk: return pll_freq_get(CORE_PLL) / >> pll0div_read(2); >> + case sys_clk2_clk: return pll_freq_get(CORE_PLL) / >> pll0div_read(3); >> + case sys_clk3_clk: return pll_freq_get(CORE_PLL) / >> pll0div_read(4); >> + case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2; >> + case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3; >> + case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4; >> + case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6; >> + case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8; >> + case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12; >> + case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24; >> + case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3; >> + case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4; >> + case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6; >> + case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12; >> + default: >> + break; >> + } >> + >> + return 0; >> +} >> diff --git a/arch/arm/cpu/armv7/keystone/clock.c >> b/arch/arm/cpu/armv7/keystone/clock.c >> index 42b664b..03c1d9f 100644 >> --- a/arch/arm/cpu/armv7/keystone/clock.c >> +++ b/arch/arm/cpu/armv7/keystone/clock.c >> @@ -106,6 +106,7 @@ void init_pll(const struct pll_init_data *data) >> >> tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN); >> >> +#ifndef CONFIG_SOC_K2E >> } else if (data->pll == TETRIS_PLL) { >> bwadj = pllm>> 1; >> /* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */ >> @@ -156,6 +157,7 @@ void init_pll(const struct pll_init_data *data) >> * only applicable for Kepler >> */ >> setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN); >> +#endif >> } else { >> setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT); >> /* >> diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c >> b/arch/arm/cpu/armv7/keystone/cmd_clock.c >> index afd30f3..d97c95b 100644 >> --- a/arch/arm/cpu/armv7/keystone/cmd_clock.c >> +++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c >> @@ -14,10 +14,10 @@ >> #include<asm/arch/psc_defs.h> >> >> struct pll_init_data cmd_pll_data = { >> - .pll = MAIN_PLL, >> - .pll_m = 16, >> - .pll_d = 1, >> - .pll_od = 2, >> + .pll = MAIN_PLL, >> + .pll_m = 16, >> + .pll_d = 1, >> + .pll_od = 2, >> }; >> >> int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const >> argv[]) >> @@ -27,12 +27,19 @@ int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int >> argc, char * const argv[]) >> >> if (strncmp(argv[1], "pa", 2) == 0) >> cmd_pll_data.pll = PASS_PLL; >> +#ifndef CONFIG_SOC_K2E >> else if (strncmp(argv[1], "arm", 3) == 0) >> cmd_pll_data.pll = TETRIS_PLL; >> +#endif >> +#ifdef CONFIG_SOC_K2HK >> else if (strncmp(argv[1], "ddr3a", 5) == 0) >> cmd_pll_data.pll = DDR3A_PLL; >> else if (strncmp(argv[1], "ddr3b", 5) == 0) >> cmd_pll_data.pll = DDR3B_PLL; >> +#else >> + else if (strncmp(argv[1], "ddr3", 4) == 0) >> + cmd_pll_data.pll = DDR3_PLL; >> +#endif >> else >> goto pll_cmd_usage; >> >> @@ -51,11 +58,20 @@ pll_cmd_usage: >> return cmd_usage(cmdtp); >> } >> >> +#ifdef CONFIG_SOC_K2HK >> U_BOOT_CMD( >> pllset, 5, 0, do_pll_cmd, >> "set pll multiplier and pre divider", >> "<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n" >> ); >> +#endif >> +#ifdef CONFIG_SOC_K2E >> +U_BOOT_CMD( >> + pllset, 5, 0, do_pll_cmd, >> + "set pll multiplier and pre divider", >> + "<pa|ddr3> <mult> <div> <OD>\n" >> +); >> +#endif >> >> int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * >> const argv[]) >> { >> @@ -79,7 +95,12 @@ U_BOOT_CMD( >> getclk, 2, 0, do_getclk_cmd, >> "get clock rate", >> "<clk index>\n" >> - "See the 'enum clk_e' in the k2hk clock.h for clk indexes\n" >> +#ifdef CONFIG_SOC_K2HK >> + "See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n" >> +#endif >> +#ifdef CONFIG_SOC_K2E >> + "See the 'enum clk_e' in the clock-k2e.h for clk indexes\n" >> +#endif >> ); >> >> int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const >> argv[]) >> diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h >> b/arch/arm/include/asm/arch-keystone/clock-k2e.h >> new file mode 100644 >> index 0000000..4147811 >> --- /dev/null >> +++ b/arch/arm/include/asm/arch-keystone/clock-k2e.h >> @@ -0,0 +1,68 @@ >> +/* >> + * K2E: Clock management APIs >> + * >> + * (C) Copyright 2012-2014 >> + * Texas Instruments Incorporated,<www.ti.com> >> + * >> + * SPDX-License-Identifier: GPL-2.0+ >> + */ >> + >> +#ifndef __ASM_ARCH_CLOCK_K2E_H >> +#define __ASM_ARCH_CLOCK_K2E_H >> + >> +enum ext_clk_e { >> + sys_clk, >> + alt_core_clk, >> + pa_clk, >> + ddr3_clk, >> + mcm_clk, >> + pcie_clk, >> + sgmii_clk, >> + xgmii_clk, >> + usb_clk, >> + ext_clk_count /* number of external clocks */ >> +}; >> + >> +extern unsigned int external_clk[ext_clk_count]; >> + >> +enum clk_e { >> + core_pll_clk, >> + pass_pll_clk, >> + ddr3_pll_clk, >> + sys_clk0_clk, >> + sys_clk0_1_clk, >> + sys_clk0_2_clk, >> + sys_clk0_3_clk, >> + sys_clk0_4_clk, >> + sys_clk0_6_clk, >> + sys_clk0_8_clk, >> + sys_clk0_12_clk, >> + sys_clk0_24_clk, >> + sys_clk1_clk, >> + sys_clk1_3_clk, >> + sys_clk1_4_clk, >> + sys_clk1_6_clk, >> + sys_clk1_12_clk, >> + sys_clk2_clk, >> + sys_clk3_clk >> +}; >> + >> +#define KS2_CLK1_6 sys_clk0_6_clk >> + >> +/* PLL identifiers */ >> +enum pll_type_e { >> + CORE_PLL, >> + PASS_PLL, >> + DDR3_PLL, >> +}; >> + >> +#define CORE_PLL_800 {CORE_PLL, 16, 1, 2} >> +#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2} >> +#define CORE_PLL_1200 {CORE_PLL, 24, 1, 2} >> +#define PASS_PLL_1000 {PASS_PLL, 20, 1, 2} >> +#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} >> +#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} >> +#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} >> +#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6} >> + >> +#endif >> diff --git a/arch/arm/include/asm/arch-keystone/clock.h >> b/arch/arm/include/asm/arch-keystone/clock.h >> index c7da352..1513c76 100644 >> --- a/arch/arm/include/asm/arch-keystone/clock.h >> +++ b/arch/arm/include/asm/arch-keystone/clock.h >> @@ -16,6 +16,10 @@ >> #include<asm/arch/clock-k2hk.h> >> #endif >> >> +#ifdef CONFIG_SOC_K2E >> +#include<asm/arch/clock-k2e.h> >> +#endif >> + >> #define MAIN_PLL CORE_PLL >> >> #include<asm/types.h> >> diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h >> index 29f0b9b..43db581 100644 >> --- a/include/configs/ks2_evm.h >> +++ b/include/configs/ks2_evm.h >> @@ -80,7 +80,7 @@ >> #define CONFIG_SPI_FLASH_STMICRO >> #define CONFIG_DAVINCI_SPI >> #define CONFIG_CMD_SPI >> -#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_LPSC_EMIF25_SPI) >> +#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6) >> #define CONFIG_SF_DEFAULT_SPEED 30000000 >> #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED >> #define CONFIG_SYS_SPI0 > -- Regards, Ivan Khoronzhuk ^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [U-boot] [Patch 3/6] ARM: keystone2: add MSMC cache coherency support for K2E SOC 2014-07-15 21:59 [U-Boot] [U-boot] [Patch 0/6] Add support for k2e SoC and EVM Ivan Khoronzhuk 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 1/6] ARM: keystone2: add K2E SoC hardware definitions Ivan Khoronzhuk 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 2/6] ARM: keystone2: clock: add K2E clock support Ivan Khoronzhuk @ 2014-07-15 21:59 ` Ivan Khoronzhuk 2014-07-26 1:27 ` [U-Boot] [U-Boot, U-boot, " Tom Rini 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 4/6] keystone2: use CONFIG_SOC_KEYSTONE in common places Ivan Khoronzhuk ` (2 subsequent siblings) 5 siblings, 1 reply; 16+ messages in thread From: Ivan Khoronzhuk @ 2014-07-15 21:59 UTC (permalink / raw) To: u-boot From: Hao Zhang <hzhang@ti.com> This patch adds Keystone2 K2E SOC specific code to support MSMC cache coherency. Also create header file for msmc to hold its API. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> --- arch/arm/cpu/armv7/keystone/init.c | 12 +++++++----- arch/arm/cpu/armv7/keystone/msmc.c | 4 ++-- arch/arm/include/asm/arch-keystone/hardware.h | 1 - arch/arm/include/asm/arch-keystone/msmc.h | 17 +++++++++++++++++ 4 files changed, 26 insertions(+), 8 deletions(-) create mode 100644 arch/arm/include/asm/arch-keystone/msmc.h diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c index f4c293a..a8f8aee 100644 --- a/arch/arm/cpu/armv7/keystone/init.c +++ b/arch/arm/cpu/armv7/keystone/init.c @@ -10,6 +10,7 @@ #include <common.h> #include <ns16550.h> #include <asm/io.h> +#include <asm/arch/msmc.h> #include <asm/arch/clock.h> #include <asm/arch/hardware.h> @@ -24,11 +25,12 @@ int arch_cpu_init(void) chip_configuration_unlock(); icache_enable(); -#ifdef CONFIG_SOC_K2HK - share_all_segments(8); - share_all_segments(9); - share_all_segments(10); /* QM PDSP */ - share_all_segments(11); /* PCIE */ + msmc_share_all_segments(8); /* TETRIS */ + msmc_share_all_segments(9); /* NETCP */ + msmc_share_all_segments(10); /* QM PDSP */ + msmc_share_all_segments(11); /* PCIE 0 */ +#ifdef CONFIG_SOC_K2E + msmc_share_all_segments(13); /* PCIE 1 */ #endif /* diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c index af858fa..7d8e597 100644 --- a/arch/arm/cpu/armv7/keystone/msmc.c +++ b/arch/arm/cpu/armv7/keystone/msmc.c @@ -8,7 +8,7 @@ */ #include <common.h> -#include <asm/arch/hardware.h> +#include <asm/arch/msmc.h> struct mpax { u32 mpaxl; @@ -56,7 +56,7 @@ struct msms_regs { }; -void share_all_segments(int priv_id) +void msmc_share_all_segments(int priv_id) { struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE; int j; diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index 9c86b69..bcfb551 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -180,7 +180,6 @@ static inline int cpu_revision(void) return rev; } -void share_all_segments(int priv_id); int cpu_to_bus(u32 *ptr, u32 length); void sdelay(unsigned long); diff --git a/arch/arm/include/asm/arch-keystone/msmc.h b/arch/arm/include/asm/arch-keystone/msmc.h new file mode 100644 index 0000000..c320db5 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/msmc.h @@ -0,0 +1,17 @@ +/* + * MSMC controller + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MSMC_H_ +#define _MSMC_H_ + +#include <asm/arch/hardware.h> + +void msmc_share_all_segments(int priv_id); + +#endif -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [U-Boot, U-boot, 3/6] ARM: keystone2: add MSMC cache coherency support for K2E SOC 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 3/6] ARM: keystone2: add MSMC cache coherency support for K2E SOC Ivan Khoronzhuk @ 2014-07-26 1:27 ` Tom Rini 0 siblings, 0 replies; 16+ messages in thread From: Tom Rini @ 2014-07-26 1:27 UTC (permalink / raw) To: u-boot On Wed, Jul 16, 2014 at 12:59:24AM +0300, Khoronzhuk, Ivan wrote: > From: Hao Zhang <hzhang@ti.com> > > This patch adds Keystone2 K2E SOC specific code to support > MSMC cache coherency. Also create header file for msmc to hold > its API. > > Acked-by: Murali Karicheri <m-karicheri2@ti.com> > Signed-off-by: Hao Zhang <hzhang@ti.com> > Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Applied to u-boot-ti/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20140725/977d2545/attachment.pgp> ^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [U-boot] [Patch 4/6] keystone2: use CONFIG_SOC_KEYSTONE in common places 2014-07-15 21:59 [U-Boot] [U-boot] [Patch 0/6] Add support for k2e SoC and EVM Ivan Khoronzhuk ` (2 preceding siblings ...) 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 3/6] ARM: keystone2: add MSMC cache coherency support for K2E SOC Ivan Khoronzhuk @ 2014-07-15 21:59 ` Ivan Khoronzhuk 2014-07-26 1:27 ` [U-Boot] [U-Boot, U-boot, " Tom Rini 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 5/6] ARM: keystone2: spl: add K2E SoC support Ivan Khoronzhuk 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 6/6] board: k2e-evm: add board support Ivan Khoronzhuk 5 siblings, 1 reply; 16+ messages in thread From: Ivan Khoronzhuk @ 2014-07-15 21:59 UTC (permalink / raw) To: u-boot Use CONFIG_SOC_KEYSTONE in common places instead of defining a lot of "if def .. || if def " for different Keystone2 SoC types. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> --- common/image-fdt.c | 2 +- drivers/serial/ns16550.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/common/image-fdt.c b/common/image-fdt.c index 5d64009..f87cc5a 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -487,7 +487,7 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, if (!ft_verify_fdt(blob)) return -1; -#ifdef CONFIG_SOC_K2HK +#if defined(CONFIG_SOC_KEYSTONE) if (IMAGE_OF_BOARD_SETUP) ft_board_setup_ex(blob, gd->bd); #endif diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index f26979d..8e7052d 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -30,7 +30,7 @@ #define serial_in(y) readb(y) #endif -#if defined(CONFIG_K2HK_EVM) +#if defined(CONFIG_SOC_KEYSTONE) #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0)) #undef UART_MCRVAL @@ -88,7 +88,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) /* /16 is proper to hit 115200 with 48MHz */ serial_out(0, &com_port->mdr1); #endif /* CONFIG_OMAP */ -#if defined(CONFIG_K2HK_EVM) +#if defined(CONFIG_SOC_KEYSTONE) serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC); #endif } -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [U-Boot, U-boot, 4/6] keystone2: use CONFIG_SOC_KEYSTONE in common places 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 4/6] keystone2: use CONFIG_SOC_KEYSTONE in common places Ivan Khoronzhuk @ 2014-07-26 1:27 ` Tom Rini 0 siblings, 0 replies; 16+ messages in thread From: Tom Rini @ 2014-07-26 1:27 UTC (permalink / raw) To: u-boot On Wed, Jul 16, 2014 at 12:59:25AM +0300, Khoronzhuk, Ivan wrote: > Use CONFIG_SOC_KEYSTONE in common places instead of defining > a lot of "if def .. || if def " for different Keystone2 SoC types. > > Acked-by: Murali Karicheri <m-karicheri2@ti.com> > Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Applied to u-boot-ti/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20140725/71f7b3ed/attachment.pgp> ^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [U-boot] [Patch 5/6] ARM: keystone2: spl: add K2E SoC support 2014-07-15 21:59 [U-Boot] [U-boot] [Patch 0/6] Add support for k2e SoC and EVM Ivan Khoronzhuk ` (3 preceding siblings ...) 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 4/6] keystone2: use CONFIG_SOC_KEYSTONE in common places Ivan Khoronzhuk @ 2014-07-15 21:59 ` Ivan Khoronzhuk 2014-07-26 1:27 ` [U-Boot] [U-Boot, U-boot, " Tom Rini 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 6/6] board: k2e-evm: add board support Ivan Khoronzhuk 5 siblings, 1 reply; 16+ messages in thread From: Ivan Khoronzhuk @ 2014-07-15 21:59 UTC (permalink / raw) To: u-boot Keystone2 K2E SoC has slightly different spl pll settings then K2HK, so correct this. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> --- arch/arm/cpu/armv7/keystone/spl.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/cpu/armv7/keystone/spl.c b/arch/arm/cpu/armv7/keystone/spl.c index e07b64d..d4b0e9b 100644 --- a/arch/arm/cpu/armv7/keystone/spl.c +++ b/arch/arm/cpu/armv7/keystone/spl.c @@ -18,10 +18,18 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_K2HK_EVM static struct pll_init_data spl_pll_config[] = { CORE_PLL_799, TETRIS_PLL_500, }; +#endif + +#ifdef CONFIG_K2E_EVM +static struct pll_init_data spl_pll_config[] = { + CORE_PLL_800, +}; +#endif void spl_init_keystone_plls(void) { -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [U-Boot, U-boot, 5/6] ARM: keystone2: spl: add K2E SoC support 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 5/6] ARM: keystone2: spl: add K2E SoC support Ivan Khoronzhuk @ 2014-07-26 1:27 ` Tom Rini 0 siblings, 0 replies; 16+ messages in thread From: Tom Rini @ 2014-07-26 1:27 UTC (permalink / raw) To: u-boot On Wed, Jul 16, 2014 at 12:59:26AM +0300, Khoronzhuk, Ivan wrote: > Keystone2 K2E SoC has slightly different spl pll settings then > K2HK, so correct this. > > Acked-by: Murali Karicheri <m-karicheri2@ti.com> > Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Applied to u-boot-ti/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20140725/8b2a66eb/attachment.pgp> ^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [U-boot] [Patch 6/6] board: k2e-evm: add board support 2014-07-15 21:59 [U-Boot] [U-boot] [Patch 0/6] Add support for k2e SoC and EVM Ivan Khoronzhuk ` (4 preceding siblings ...) 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 5/6] ARM: keystone2: spl: add K2E SoC support Ivan Khoronzhuk @ 2014-07-15 21:59 ` Ivan Khoronzhuk 2014-07-26 1:28 ` [U-Boot] [U-Boot,U-boot,6/6] " Tom Rini 5 siblings, 1 reply; 16+ messages in thread From: Ivan Khoronzhuk @ 2014-07-15 21:59 UTC (permalink / raw) To: u-boot From: Hao Zhang <hzhang@ti.com> This patch adds Keystone2 k2e_evm evaluation board support. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> --- arch/arm/include/asm/arch-keystone/hardware.h | 1 + board/ti/ks2_evm/Makefile | 2 + board/ti/ks2_evm/board_k2e.c | 39 +++++++++++++++++++ board/ti/ks2_evm/ddr3_cfg.c | 40 +++++++++++++++++++ board/ti/ks2_evm/ddr3_cfg.h | 3 ++ board/ti/ks2_evm/ddr3_k2e.c | 55 +++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/k2e_evm.h | 37 ++++++++++++++++++ 8 files changed, 178 insertions(+) create mode 100644 board/ti/ks2_evm/board_k2e.c create mode 100644 board/ti/ks2_evm/ddr3_k2e.c create mode 100644 include/configs/k2e_evm.h diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index bcfb551..ddeb06e 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -119,6 +119,7 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_PLL_CNTRL_BASE 0x02310000 #define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE +#define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4) #define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8) #define KS2_RSTCTRL_KEY 0x5a69 #define KS2_RSTCTRL_MASK 0xffff0000 diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile index 774a7d5..00f1164 100644 --- a/board/ti/ks2_evm/Makefile +++ b/board/ti/ks2_evm/Makefile @@ -9,3 +9,5 @@ obj-y += board.o obj-y += ddr3_cfg.o obj-$(CONFIG_K2HK_EVM) += board_k2hk.o obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o +obj-$(CONFIG_K2E_EVM) += board_k2e.o +obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c new file mode 100644 index 0000000..d2499b7 --- /dev/null +++ b/board/ti/ks2_evm/board_k2e.c @@ -0,0 +1,39 @@ +/* + * K2E EVM : Board initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/ddr3.h> +#include <asm/arch/hardware.h> + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int external_clk[ext_clk_count] = { + [sys_clk] = 100000000, + [alt_core_clk] = 100000000, + [pa_clk] = 100000000, + [ddr3_clk] = 100000000, + [mcm_clk] = 312500000, + [pcie_clk] = 100000000, + [sgmii_clk] = 156250000, + [xgmii_clk] = 156250000, + [usb_clk] = 100000000, +}; + +static struct pll_init_data pll_config[] = { + CORE_PLL_1200, + PASS_PLL_1000, +}; + +#if defined(CONFIG_BOARD_EARLY_INIT_F) +int board_early_init_f(void) +{ + init_plls(ARRAY_SIZE(pll_config), pll_config); + return 0; +} +#endif diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c index 6e55af9..f7da9f2 100644 --- a/board/ti/ks2_evm/ddr3_cfg.c +++ b/board/ti/ks2_evm/ddr3_cfg.c @@ -93,6 +93,46 @@ struct ddr3_emif_config ddr3_1333_2g = { }; #endif +#ifdef CONFIG_K2E_EVM +/* DDR3 PHY configuration data with 1600M rate, and 4GB size */ +struct ddr3_phy_config ddr3phy_1600_4g = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x08861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x9D9CBB66ul, + .dtpr1 = 0x12840300ul, + .dtpr2 = 0x5002D200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +/* DDR3 EMIF configuration data with 1600M rate, and 4GB size */ +struct ddr3_emif_config ddr3_1600_4g = { + .sdcfg = 0x6200CE62ul, + .sdtim1 = 0x166C9855ul, + .sdtim2 = 0x00001D4Aul, + .sdtim3 = 0x421DFF53ul, + .sdtim4 = 0x543F07FFul, + .zqcfg = 0x70073200ul, + .sdrfc = 0x00001869ul, +}; +#endif + int ddr3_get_dimm_params(char *dimm_name) { int ret; diff --git a/board/ti/ks2_evm/ddr3_cfg.h b/board/ti/ks2_evm/ddr3_cfg.h index d14bac3..15fcf52 100644 --- a/board/ti/ks2_evm/ddr3_cfg.h +++ b/board/ti/ks2_evm/ddr3_cfg.h @@ -16,6 +16,9 @@ extern struct ddr3_emif_config ddr3_1600_8g; extern struct ddr3_phy_config ddr3phy_1333_2g; extern struct ddr3_emif_config ddr3_1333_2g; +extern struct ddr3_phy_config ddr3phy_1600_4g; +extern struct ddr3_emif_config ddr3_1600_4g; + int ddr3_get_dimm_params(char *dimm_name); #endif /* __DDR3_CFG_H */ diff --git a/board/ti/ks2_evm/ddr3_k2e.c b/board/ti/ks2_evm/ddr3_k2e.c new file mode 100644 index 0000000..40fd966 --- /dev/null +++ b/board/ti/ks2_evm/ddr3_k2e.c @@ -0,0 +1,55 @@ +/* + * Keystone2: DDR3 initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include "ddr3_cfg.h" +#include <asm/arch/ddr3.h> + +static int ddr3_size; +static struct pll_init_data ddr3_400 = DDR3_PLL_400; + +void ddr3_init(void) +{ + char dimm_name[32]; + + if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1)) + init_pll(&ddr3_400); + + ddr3_get_dimm_params(dimm_name); + + printf("Detected SO-DIMM [%s]\n", dimm_name); + + /* Reset DDR3 PHY after PLL enabled */ + ddr3_reset_ddrphy(); + + if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { + /* 8G SO-DIMM */ + ddr3_size = 8; + printf("DRAM: 8 GiB\n"); + ddr3phy_1600_8g.zq0cr1 |= 0x10000; + ddr3phy_1600_8g.zq1cr1 |= 0x10000; + ddr3phy_1600_8g.zq2cr1 |= 0x10000; + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g); + } else if (!strcmp(dimm_name, "18KSF51272HZ-1G6K2")) { + /* 4G SO-DIMM */ + ddr3_size = 4; + printf("DRAM: 4 GiB\n"); + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g); + } +} + +/** + * ddr3_get_size - return ddr3 size in GiB + */ +int ddr3_get_size(void) +{ + return ddr3_size; +} diff --git a/boards.cfg b/boards.cfg index e08ccae..24dab91 100644 --- a/boards.cfg +++ b/boards.cfg @@ -299,6 +299,7 @@ Active arm armv7 exynos samsung trats2 Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Przemyslaw Marczak <p.marczak@samsung.com> Active arm armv7 highbank - highbank highbank - Rob Herring <robh@kernel.org> Active arm armv7 keystone ti ks2_evm k2hk_evm - Vitaly Andrianov <vitalya@ti.com> +Active arm armv7 keystone ti ks2_evm k2e_evm - Vitaly Andrianov <vitalya@ti.com> Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut <marek.vasut@gmail.com> Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg - Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic <sbabic@denx.de> diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h new file mode 100644 index 0000000..3502d10 --- /dev/null +++ b/include/configs/k2e_evm.h @@ -0,0 +1,37 @@ +/* + * Configuration header file for TI's k2e-evm + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_K2E_EVM_H +#define __CONFIG_K2E_EVM_H + +/* Platform type */ +#define CONFIG_SOC_K2E +#define CONFIG_K2E_EVM + +/* U-Boot general configuration */ +#define CONFIG_SYS_PROMPT "K2E EVM # " + +#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" + +#define KS2_FDT_NAME "name_fdt=k2e-evm.dtb\0" +#define KS2_ADDR_MON "addr_mon=0x0c140000\0" +#define KS2_NAME_MON "name_mon=skern-k2e-evm.bin\0" +#define NAME_UBOOT "name_uboot=u-boot-spi-k2e-evm.gph\0" +#define NAME_UBI "name_ubi=k2e-evm-ubifs.ubi\0" + +#include <configs/ks2_evm.h> + +/* SPL SPI Loader Configuration */ +#define CONFIG_SPL_TEXT_BASE 0x0c100000 + +/* NAND Configuration */ +#define CONFIG_SYS_NAND_PAGE_2K + +#endif /* __CONFIG_K2E_EVM_H */ -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [U-Boot,U-boot,6/6] board: k2e-evm: add board support 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 6/6] board: k2e-evm: add board support Ivan Khoronzhuk @ 2014-07-26 1:28 ` Tom Rini 0 siblings, 0 replies; 16+ messages in thread From: Tom Rini @ 2014-07-26 1:28 UTC (permalink / raw) To: u-boot On Wed, Jul 16, 2014 at 12:59:27AM +0300, Khoronzhuk, Ivan wrote: > From: Hao Zhang <hzhang@ti.com> > > This patch adds Keystone2 k2e_evm evaluation board support. > > Signed-off-by: Hao Zhang <hzhang@ti.com> > Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Applied to u-boot-ti/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20140725/779916f9/attachment.pgp> ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2014-09-04 15:04 UTC | newest] Thread overview: 16+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-07-15 21:59 [U-Boot] [U-boot] [Patch 0/6] Add support for k2e SoC and EVM Ivan Khoronzhuk 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 1/6] ARM: keystone2: add K2E SoC hardware definitions Ivan Khoronzhuk 2014-07-26 1:27 ` [U-Boot] [U-Boot, U-boot, " Tom Rini 2014-07-26 1:27 ` Tom Rini 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 2/6] ARM: keystone2: clock: add K2E clock support Ivan Khoronzhuk 2014-07-26 1:27 ` [U-Boot] [U-Boot, U-boot, " Tom Rini 2014-09-04 14:08 ` [U-Boot] [U-boot] [Patch " Murali Karicheri 2014-09-04 15:04 ` Ivan Khoronzhuk 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 3/6] ARM: keystone2: add MSMC cache coherency support for K2E SOC Ivan Khoronzhuk 2014-07-26 1:27 ` [U-Boot] [U-Boot, U-boot, " Tom Rini 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 4/6] keystone2: use CONFIG_SOC_KEYSTONE in common places Ivan Khoronzhuk 2014-07-26 1:27 ` [U-Boot] [U-Boot, U-boot, " Tom Rini 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 5/6] ARM: keystone2: spl: add K2E SoC support Ivan Khoronzhuk 2014-07-26 1:27 ` [U-Boot] [U-Boot, U-boot, " Tom Rini 2014-07-15 21:59 ` [U-Boot] [U-boot] [Patch 6/6] board: k2e-evm: add board support Ivan Khoronzhuk 2014-07-26 1:28 ` [U-Boot] [U-Boot,U-boot,6/6] " Tom Rini
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