[U-Boot] [PATCH v7 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox

[U-Boot] [PATCH v7 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox

[Fabio Estevam]

mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
Other SoCs work with the standard 32 bytes alignment.

Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, 
which addresses the needs from mx6solox and also works for the other SoCs.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v6:
- Only use FEC_DMA_RX_MINALIGN for the RX buffers
Changes since v5:
- Add Stefan's Ack
Changes since v4:
- None

Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
 drivers/net/fec_mxc.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 4cefda4..d310016 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -28,6 +28,14 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 #define FEC_XFER_TIMEOUT	5000
 
+/*
+ * The standard 32-byte DMA alignment does not work on mx6solox, which requires
+ * 64-byte alignment in the DMA RX FEC buffer.
+ * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
+ * satisfies the alignment on other SoCs (32-bytes)
+ */
+#define FEC_DMA_RX_MINALIGN	64
+
 #ifndef CONFIG_MII
 #error "CONFIG_MII has to be defined!"
 #endif
@@ -881,9 +889,9 @@ static int fec_alloc_descs(struct fec_priv *fec)
 	/* Allocate RX buffers. */
 
 	/* Maximum RX buffer size. */
-	size = roundup(FEC_MAX_PKT_SIZE, ARCH_DMA_MINALIGN);
+	size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
 	for (i = 0; i < FEC_RBD_NUM; i++) {
-		data = memalign(ARCH_DMA_MINALIGN, size);
+		data = memalign(FEC_DMA_RX_MINALIGN, size);
 		if (!data) {
 			printf("%s: error allocating rxbuf %d\n", __func__, i);
 			goto err_ring;
-- 
1.9.1

[U-Boot] [PATCH v7 2/2] net: fec_mxc: Poll FEC_TBD_READY after polling TDAR

[Fabio Estevam]

When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
always cleared prior then the READY bit is cleared in the last BD, which causes
FEC packets reception to always fail.

As explained by Ye Li:

"The TDAR bit is cleared when the descriptors are all out from TX ring, but on 
mx6solox we noticed that the READY bit is still not cleared right after TDAR. 
These are two distinct signals, and in IC simulation, we found that TDAR always
gets cleared prior than the READY bit of last BD becomes cleared. 
In mx6solox, we use a later version of FEC IP. It looks like that this 
intrinsic behaviour of TDAR bit has changed in this newer FEC version."

Fix this by polling the READY bit of BD after the TDAR polling, which covers the
mx6solox case and does not harm the other SoCs.

No performance drop has been noticed with this patch applied when testing TFTP
transfers on several boards of different i.mx SoCs.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v6:
- Fix checkpatch complaint about >80 colummn
Changes since v5:
- Put explanation why we need to poll READY bit after TDAR into the code

 drivers/net/fec_mxc.c | 30 +++++++++++++++++++++++++++---
 1 file changed, 27 insertions(+), 3 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index d310016..549d648 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -719,13 +719,37 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
 			break;
 	}
 
-	if (!timeout)
+	if (!timeout) {
 		ret = -EINVAL;
+		goto out;
+	}
 
-	invalidate_dcache_range(addr, addr + size);
-	if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY)
+	/*
+	 * The TDAR bit is cleared when the descriptors are all out from TX
+	 * but on mx6solox we noticed that the READY bit is still not cleared
+	 * right after TDAR.
+	 * These are two distinct signals, and in IC simulation, we found that
+	 * TDAR always gets cleared prior than the READY bit of last BD becomes
+	 * cleared.
+	 * In mx6solox, we use a later version of FEC IP. It looks like that
+	 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
+	 * version.
+	 *
+	 * Fix this by polling the READY bit of BD after the TDAR polling,
+	 * which covers the mx6solox case and does not harm the other SoCs.
+	 */
+	timeout = FEC_XFER_TIMEOUT;
+	while (--timeout) {
+		invalidate_dcache_range(addr, addr + size);
+		if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
+		    FEC_TBD_READY))
+			break;
+	}
+
+	if (!timeout)
 		ret = -EINVAL;
 
+out:
 	debug("fec_send: status 0x%x index %d ret %i\n",
 			readw(&fec->tbd_base[fec->tbd_index].status),
 			fec->tbd_index, ret);
-- 
1.9.1

[U-Boot] [PATCH v7 2/2] net: fec_mxc: Poll FEC_TBD_READY after polling TDAR

[Marek Vasut]

On Monday, August 25, 2014 at 06:34:17 PM, Fabio Estevam wrote:
> When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
> always cleared prior then the READY bit is cleared in the last BD, which
> causes FEC packets reception to always fail.
> 
> As explained by Ye Li:
> 
> "The TDAR bit is cleared when the descriptors are all out from TX ring, but
> on mx6solox we noticed that the READY bit is still not cleared right after
> TDAR. These are two distinct signals, and in IC simulation, we found that
> TDAR always gets cleared prior than the READY bit of last BD becomes
> cleared.
> In mx6solox, we use a later version of FEC IP. It looks like that this
> intrinsic behaviour of TDAR bit has changed in this newer FEC version."
> 
> Fix this by polling the READY bit of BD after the TDAR polling, which
> covers the mx6solox case and does not harm the other SoCs.
> 
> No performance drop has been noticed with this patch applied when testing
> TFTP transfers on several boards of different i.mx SoCs.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Acked-by: Marek Vasut <marex@denx.de>

Best regards,
Marek Vasut

[U-Boot] [PATCH v7 2/2] net: fec_mxc: Poll FEC_TBD_READY after polling TDAR

[Stefano Babic]

On 25/08/2014 18:34, Fabio Estevam wrote:
> When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
> always cleared prior then the READY bit is cleared in the last BD, which causes
> FEC packets reception to always fail.
> 
> As explained by Ye Li:
> 
> "The TDAR bit is cleared when the descriptors are all out from TX ring, but on 
> mx6solox we noticed that the READY bit is still not cleared right after TDAR. 
> These are two distinct signals, and in IC simulation, we found that TDAR always
> gets cleared prior than the READY bit of last BD becomes cleared. 
> In mx6solox, we use a later version of FEC IP. It looks like that this 
> intrinsic behaviour of TDAR bit has changed in this newer FEC version."
> 
> Fix this by polling the READY bit of BD after the TDAR polling, which covers the
> mx6solox case and does not harm the other SoCs.
> 
> No performance drop has been noticed with this patch applied when testing TFTP
> transfers on several boards of different i.mx SoCs.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v7 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox

[Marek Vasut]

On Monday, August 25, 2014 at 06:34:16 PM, Fabio Estevam wrote:
> mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
> Other SoCs work with the standard 32 bytes alignment.
> 
> Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
> which addresses the needs from mx6solox and also works for the other SoCs.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Acked-by: Marek Vasut <marex@denx.de>

Best regards,
Marek Vasut

[U-Boot] [PATCH v7 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox

[Fabio Estevam]

Tom, Joe or Stefano,

On Mon, Aug 25, 2014 at 4:51 PM, Marek Vasut <marex@denx.de> wrote:
> On Monday, August 25, 2014 at 06:34:16 PM, Fabio Estevam wrote:
>> mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
>> Other SoCs work with the standard 32 bytes alignment.
>>
>> Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
>> which addresses the needs from mx6solox and also works for the other SoCs.
>>
>> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
>
> Acked-by: Marek Vasut <marex@denx.de>

Could this one be applied for 2014.10-rc?

Thanks

[U-Boot] [PATCH v7 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox

[Tom Rini]

On Sat, Aug 30, 2014 at 02:22:22PM -0300, Fabio Estevam wrote:
> Tom, Joe or Stefano,
> 
> On Mon, Aug 25, 2014 at 4:51 PM, Marek Vasut <marex@denx.de> wrote:
> > On Monday, August 25, 2014 at 06:34:16 PM, Fabio Estevam wrote:
> >> mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
> >> Other SoCs work with the standard 32 bytes alignment.
> >>
> >> Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
> >> which addresses the needs from mx6solox and also works for the other SoCs.
> >>
> >> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> >
> > Acked-by: Marek Vasut <marex@denx.de>
> 
> Could this one be applied for 2014.10-rc?

I'd like this via the imx tree.

-- 
Tom
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[U-Boot] [PATCH v7 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox

[Fabio Estevam]

Hi Tom,

On Sat, Aug 30, 2014 at 4:21 PM, Tom Rini <trini@ti.com> wrote:
> On Sat, Aug 30, 2014 at 02:22:22PM -0300, Fabio Estevam wrote:
>> Tom, Joe or Stefano,
>>
>> On Mon, Aug 25, 2014 at 4:51 PM, Marek Vasut <marex@denx.de> wrote:
>> > On Monday, August 25, 2014 at 06:34:16 PM, Fabio Estevam wrote:
>> >> mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
>> >> Other SoCs work with the standard 32 bytes alignment.
>> >>
>> >> Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
>> >> which addresses the needs from mx6solox and also works for the other SoCs.
>> >>
>> >> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
>> >
>> > Acked-by: Marek Vasut <marex@denx.de>
>>
>> Could this one be applied for 2014.10-rc?
>
> I'd like this via the imx tree.

Unfortunately, I am not getting any response from Stefano for quite some time.

Can you apply this series as we are already in rc2 now?

[U-Boot] [PATCH v7 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox

[Stefano Babic]

Hi Fabio,

On 09/09/2014 01:52, Fabio Estevam wrote:
> Hi Tom,
> 
> On Sat, Aug 30, 2014 at 4:21 PM, Tom Rini <trini@ti.com> wrote:
>> On Sat, Aug 30, 2014 at 02:22:22PM -0300, Fabio Estevam wrote:
>>> Tom, Joe or Stefano,
>>>
>>> On Mon, Aug 25, 2014 at 4:51 PM, Marek Vasut <marex@denx.de> wrote:
>>>> On Monday, August 25, 2014 at 06:34:16 PM, Fabio Estevam wrote:
>>>>> mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
>>>>> Other SoCs work with the standard 32 bytes alignment.
>>>>>
>>>>> Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
>>>>> which addresses the needs from mx6solox and also works for the other SoCs.
>>>>>
>>>>> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
>>>>
>>>> Acked-by: Marek Vasut <marex@denx.de>
>>>
>>> Could this one be applied for 2014.10-rc?
>>
>> I'd like this via the imx tree.
> 
> Unfortunately, I am not getting any response from Stefano for quite some time.
> 

Sorry, I was not in office in last two weeks.

> Can you apply this series as we are already in rc2 now?

Applied to u-boot-imx, thanks !

Fabio, I will try to dig in all patches that queue in last two weeks. If
you can, please take a look next week what is still missing and send me
a remind - thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v7 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox

[Fabio Estevam]

Hi Stefano,

On Tue, Sep 9, 2014 at 10:09 AM, Stefano Babic <sbabic@denx.de> wrote:

> Fabio, I will try to dig in all patches that queue in last two weeks. If
> you can, please take a look next week what is still missing and send me
> a remind - thanks !

Excellent, thanks!

[U-Boot] [PATCH v7 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox

[Fabio Estevam]

Hi Stefano,

On Mon, Aug 25, 2014 at 1:34 PM, Fabio Estevam
<fabio.estevam@freescale.com> wrote:
> mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
> Other SoCs work with the standard 32 bytes alignment.
>
> Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
> which addresses the needs from mx6solox and also works for the other SoCs.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Could we have this series applied for 2014.10-rc ?