From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Tue, 09 Sep 2014 15:10:24 +0200 Subject: [U-Boot] [PATCH v7 2/2] net: fec_mxc: Poll FEC_TBD_READY after polling TDAR In-Reply-To: <1408984457-10272-2-git-send-email-fabio.estevam@freescale.com> References: <1408984457-10272-1-git-send-email-fabio.estevam@freescale.com> <1408984457-10272-2-git-send-email-fabio.estevam@freescale.com> Message-ID: <540EFC40.2070802@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 25/08/2014 18:34, Fabio Estevam wrote: > When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets > always cleared prior then the READY bit is cleared in the last BD, which causes > FEC packets reception to always fail. > > As explained by Ye Li: > > "The TDAR bit is cleared when the descriptors are all out from TX ring, but on > mx6solox we noticed that the READY bit is still not cleared right after TDAR. > These are two distinct signals, and in IC simulation, we found that TDAR always > gets cleared prior than the READY bit of last BD becomes cleared. > In mx6solox, we use a later version of FEC IP. It looks like that this > intrinsic behaviour of TDAR bit has changed in this newer FEC version." > > Fix this by polling the READY bit of BD after the TDAR polling, which covers the > mx6solox case and does not harm the other SoCs. > > No performance drop has been noticed with this patch applied when testing TFTP > transfers on several boards of different i.mx SoCs. > > Signed-off-by: Fabio Estevam > --- Applied to u-boot-imx, thanks ! Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================