From mboxrd@z Thu Jan  1 00:00:00 1970
From: Dinh Nguyen <dinguyen@opensource.altera.com>
Date: Mon, 15 Sep 2014 14:25:09 -0500
Subject: [U-Boot] [PATCH 13/35] arm: socfpga: clock: Drop nonsense
 inlining from clock manager code
In-Reply-To: <1410779188-6880-14-git-send-email-marex@denx.de>
References: <1410779188-6880-1-git-send-email-marex@denx.de>
	<1410779188-6880-14-git-send-email-marex@denx.de>
Message-ID: <54173D15.8060405@opensource.altera.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

On 09/15/2014 06:06 AM, Marek Vasut wrote:
> The inlining is done by GCC whe needed, there is no need to do it

s/whe/when.

Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>

thanks...
> explicitly. Furthermore, the inline keyword does not force-inline
> the code, but is only a hint for the compiler. Scrub this hint.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Tom Rini <trini@ti.com>
> Cc: Wolfgang Denk <wd@denx.de>
> Cc: Pavel Machek <pavel@denx.de>
> ---
>  arch/arm/cpu/armv7/socfpga/clock_manager.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c
> index 158501a..d032bbd 100644
> --- a/arch/arm/cpu/armv7/socfpga/clock_manager.c
> +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
> @@ -30,7 +30,7 @@ static const struct socfpga_clock_manager *clock_manager_base =
>  	CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
>  	CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
>  
> -static inline void cm_wait_for_lock(uint32_t mask)
> +static void cm_wait_for_lock(uint32_t mask)
>  {
>  	register uint32_t inter_val;
>  	do {
> @@ -39,7 +39,7 @@ static inline void cm_wait_for_lock(uint32_t mask)
>  }
>  
>  /* function to poll in the fsm busy bit */
> -static inline void cm_wait_for_fsm(void)
> +static void cm_wait_for_fsm(void)
>  {
>  	while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
>  		;
> @@ -49,22 +49,22 @@ static inline void cm_wait_for_fsm(void)
>   * function to write the bypass register which requires a poll of the
>   * busy bit
>   */
> -static inline void cm_write_bypass(uint32_t val)
> +static void cm_write_bypass(uint32_t val)
>  {
>  	writel(val, &clock_manager_base->bypass);
>  	cm_wait_for_fsm();
>  }
>  
>  /* function to write the ctrl register which requires a poll of the busy bit */
> -static inline void cm_write_ctrl(uint32_t val)
> +static void cm_write_ctrl(uint32_t val)
>  {
>  	writel(val, &clock_manager_base->ctrl);
>  	cm_wait_for_fsm();
>  }
>  
>  /* function to write a clock register that has phase information */
> -static inline void cm_write_with_phase(uint32_t value,
> -	uint32_t reg_address, uint32_t mask)
> +static void cm_write_with_phase(uint32_t value,
> +				uint32_t reg_address, uint32_t mask)
>  {
>  	/* poll until phase is zero */
>  	while (readl(reg_address) & mask)
>