From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stefan Roese <sr@denx.de>
Date: Tue, 23 Sep 2014 17:20:33 +0200
Subject: [U-Boot] [WIP PATCH 4/4 v2] arm: socfpga: Don't enable dcache
 (because of cadence SPI driver problem)
In-Reply-To: <201409231632.13016.marex@denx.de>
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	<1411481312-9929-5-git-send-email-sr@denx.de>
	<201409231632.13016.marex@denx.de>
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On 23.09.2014 16:32, Marek Vasut wrote:
>> diff --git a/board/altera/socfpga/socfpga_cyclone5.c
>> b/board/altera/socfpga/socfpga_cyclone5.c index 10f15e0..3f19d89 100644
>> --- a/board/altera/socfpga/socfpga_cyclone5.c
>> +++ b/board/altera/socfpga/socfpga_cyclone5.c
>> @@ -76,7 +76,9 @@ int board_phy_config(struct phy_device *phydev)
>>   int board_init(void)
>>   {
>>   	icache_enable();
>> +#if 0 // test-only: disable dcache for now as it causes problems with the
>> SPI driver dcache_enable();
>> +#endif
>
> This means the DMA code in cadence driver is not flushing/invalidating cache
> as it should.

I am aware of this. Caching related issues are definitely not new to me. ;)

I didn't spot any DMA controller related code in the driver. Only some 
FIFO stuff which is most likely the problematic code part. But since 
I've no deeper insight in this IP core right now, I just wanted to offer 
this info to others for now.

> Are you planning to fix it proper eventually?

Not right now, sorry. As I explained in my cover letter, I have to move 
to other projects. At least for a few days.

> But this is really a good thing that you found this out! That's an important
> information, thanks!

Yes, thats exactly why I posted it in this stage.

Thanks,
Stefan