From mboxrd@z Thu Jan  1 00:00:00 1970
From: Aaron Williams <awilliams@marvell.com>
Date: Thu, 31 Oct 2019 18:01:34 +0000
Subject: [U-Boot] [EXT] Re: Cavium/Marvell Octeon Support
In-Reply-To: <20191031104027.C1FEC240060@gemini.denx.de>
References: <BYAPR18MB2440FCA78BE210E053A159E4B16B0@BYAPR18MB2440.namprd18.prod.outlook.com>
 <1889679.7FQr5zsBR1@flash> <20191031104027.C1FEC240060@gemini.denx.de>
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To: u-boot@lists.denx.de

Hi Wolfgang,

On Thursday, October 31, 2019 3:40:27 AM PDT Wolfgang Denk wrote:
> Dear Aaron,
> 
> In message <1889679.7FQr5zsBR1@flash> you wrote:
> > Currently we are using 39MB under arch/mips. I think I can easily cut this
> > down to 15MB or smaller, especially by moving some code here to the
> > appropriate driver directories (i.e. DRAM,  pcie, watchdog, etc.)
> > 
> > It will still be a large SoC, though.
> 
> Have you already looked at formal requirements, like coding style
> etc.?   Did you ever run your additions through checkpatch.pl, for
> example?

We did follow the formal coding style. Everything will go through checkpatch. 
My biggest complaint about it is the 80 columns for debug and other print 
statements.
> 
> Best regards,
> 
> Wolfgang Denk

-Aaron