[U-Boot] [PATCH 0/7] ARM: sunxi: Add basic support for Allwinner A31 (sun6i)

[U-Boot] [PATCH 0/7] ARM: sunxi: Add basic support for Allwinner A31 (sun6i)

[Chen-Yu Tsai]

Hi everyone,

This series add basic support for Allwinner's A31 SoC. The patches,
excluding the first one, were cherry-picked from u-boot-sunxi. Due to
the difference between u-boot mainline and u-boot-sunxi, some patches
were rearranged or squashed to better fit the current state of u-boot,
and not introduce any build breaks. It follows Ian's initial merge
method of sun7i support: introducing various components first, then
enabling them in the last commit. I tried to keep the commits separate,
thus retaining the original author and Signed-off-bys.

Patch 1 adds a wrapper around "func(USB, usb, 0)" in BOOT_TARGET_DEVICES
to deal with breakage when USB support is not enabled.

Patch 2 adds memory addresses for some hardware blocks new in sun6i.

Patch 3 adds support for the new PRCM (power reset and clock management)
block, which also contains PLL bias voltage control.

Patch 4 adds support for the clock module. This patch is a bunch of
different sun6i related patches on the clock code, from when sun6i
support was introduced to u-boot-sunxi, up to its current form.
This is done to avoid various conflicts and needlessly introducing
then removing macros.

Patch 5 adds mmc support on sun6i.

Patch 6 adds uart0 muxing on sun6i.

Patch 7 enables sun6i support and adds defconfig for the Colombus board.



Cheers
ChenYu


Chen-Yu Tsai (2):
  ARM: sunxi: Fix build break when CONFIG_USB_EHCI is not defined
  ARM: sun6i: Add clock support

Hans de Goede (1):
  ARM: sunxi-mmc: Add mmc support for sun6i / A31

Maxime Ripard (2):
  ARM: sun6i: Setup the A31 UART0 muxing
  ARM: sunxi: Add basic A31 support

Oliver Schinagl (2):
  ARM: sun6i: Add base address for the new controllers in A31
  ARM: sun6i: Add support for the new power control module found on the
    A31

 arch/arm/Kconfig                              |   3 +
 arch/arm/cpu/armv7/sunxi/Makefile             |   2 +
 arch/arm/cpu/armv7/sunxi/board.c              |   4 +
 arch/arm/cpu/armv7/sunxi/clock_sun6i.c        | 107 ++++++++++++
 arch/arm/cpu/armv7/sunxi/cpu_info.c           |   2 +
 arch/arm/cpu/armv7/sunxi/prcm.c               |  37 ++++
 arch/arm/include/asm/arch-sunxi/clock.h       |   4 +
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 205 ++++++++++++++++++++++
 arch/arm/include/asm/arch-sunxi/cpu.h         |   9 +
 arch/arm/include/asm/arch-sunxi/mmc.h         |   2 -
 arch/arm/include/asm/arch-sunxi/prcm.h        | 238 ++++++++++++++++++++++++++
 board/sunxi/Kconfig                           |  10 +-
 configs/Colombus_defconfig                    |   4 +
 drivers/mmc/sunxi_mmc.c                       |   9 +
 include/configs/sun6i.h                       |  26 +++
 include/configs/sunxi-common.h                |   8 +-
 16 files changed, 666 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/sunxi/clock_sun6i.c
 create mode 100644 arch/arm/cpu/armv7/sunxi/prcm.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/clock_sun6i.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/prcm.h
 create mode 100644 configs/Colombus_defconfig
 create mode 100644 include/configs/sun6i.h

-- 
2.1.0

[U-Boot] [PATCH 1/7] ARM: sunxi: Fix build break when CONFIG_USB_EHCI is not defined

[Chen-Yu Tsai]

BOOT_TARGET_DEVICES includes USB unconditionally. This breaks when
CONFIG_CMD_USB is not defined. Use a secondary macro to conditionally
include it when CONFIG_EHCI is enabled, as we do for CONFIG_AHCI.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 include/configs/sunxi-common.h | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 1d947d7..a31656e 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -233,10 +233,16 @@
 #define BOOT_TARGET_DEVICES_SCSI(func)
 #endif
 
+#ifdef CONFIG_USB_EHCI
+#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0) \
 	BOOT_TARGET_DEVICES_SCSI(func) \
-	func(USB, usb, 0) \
+	BOOT_TARGET_DEVICES_USB(func) \
 	func(PXE, pxe, na) \
 	func(DHCP, dhcp, na)
 
-- 
2.1.0

[U-Boot] [PATCH 1/7] ARM: sunxi: Fix build break when CONFIG_USB_EHCI is not defined

[Chen-Yu Tsai]

Hi Ian, Hans,

On Mon, Sep 8, 2014 at 9:28 PM, Chen-Yu Tsai <wens@csie.org> wrote:
> BOOT_TARGET_DEVICES includes USB unconditionally. This breaks when
> CONFIG_CMD_USB is not defined. Use a secondary macro to conditionally
> include it when CONFIG_EHCI is enabled, as we do for CONFIG_AHCI.

The other patches are for the next release, but maybe this fix could
go into 2014.10?

Thanks

ChenYu

>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  include/configs/sunxi-common.h | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
> index 1d947d7..a31656e 100644
> --- a/include/configs/sunxi-common.h
> +++ b/include/configs/sunxi-common.h
> @@ -233,10 +233,16 @@
>  #define BOOT_TARGET_DEVICES_SCSI(func)
>  #endif
>
> +#ifdef CONFIG_USB_EHCI
> +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
> +#else
> +#define BOOT_TARGET_DEVICES_USB(func)
> +#endif
> +
>  #define BOOT_TARGET_DEVICES(func) \
>         func(MMC, mmc, 0) \
>         BOOT_TARGET_DEVICES_SCSI(func) \
> -       func(USB, usb, 0) \
> +       BOOT_TARGET_DEVICES_USB(func) \
>         func(PXE, pxe, na) \
>         func(DHCP, dhcp, na)
>
> --
> 2.1.0
>

[U-Boot] [PATCH 1/7] ARM: sunxi: Fix build break when CONFIG_USB_EHCI is not defined

[Hans de Goede]

Hi Chen,

On 09/11/2014 07:07 PM, Chen-Yu Tsai wrote:
> Hi Ian, Hans,
> 
> On Mon, Sep 8, 2014 at 9:28 PM, Chen-Yu Tsai <wens@csie.org> wrote:
>> BOOT_TARGET_DEVICES includes USB unconditionally. This breaks when
>> CONFIG_CMD_USB is not defined. Use a secondary macro to conditionally
>> include it when CONFIG_EHCI is enabled, as we do for CONFIG_AHCI.
> 
> The other patches are for the next release, but maybe this fix could
> go into 2014.10?

I agree that this is a benign bug fix, but since we don't have any
boards not setting CONFIG_EHCI atm I don't really see the value
for getting it into 2014.10.

Regards,

Hans

> 
> Thanks
> 
> ChenYu
> 
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>>  include/configs/sunxi-common.h | 8 +++++++-
>>  1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
>> index 1d947d7..a31656e 100644
>> --- a/include/configs/sunxi-common.h
>> +++ b/include/configs/sunxi-common.h
>> @@ -233,10 +233,16 @@
>>  #define BOOT_TARGET_DEVICES_SCSI(func)
>>  #endif
>>
>> +#ifdef CONFIG_USB_EHCI
>> +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
>> +#else
>> +#define BOOT_TARGET_DEVICES_USB(func)
>> +#endif
>> +
>>  #define BOOT_TARGET_DEVICES(func) \
>>         func(MMC, mmc, 0) \
>>         BOOT_TARGET_DEVICES_SCSI(func) \
>> -       func(USB, usb, 0) \
>> +       BOOT_TARGET_DEVICES_USB(func) \
>>         func(PXE, pxe, na) \
>>         func(DHCP, dhcp, na)
>>
>> --
>> 2.1.0
>>

[U-Boot] [PATCH 1/7] ARM: sunxi: Fix build break when CONFIG_USB_EHCI is not defined

[Ian Campbell]

On Thu, 2014-09-11 at 19:19 +0200, Hans de Goede wrote:
> Hi Chen,
> 
> On 09/11/2014 07:07 PM, Chen-Yu Tsai wrote:
> > Hi Ian, Hans,
> > 
> > On Mon, Sep 8, 2014 at 9:28 PM, Chen-Yu Tsai <wens@csie.org> wrote:
> >> BOOT_TARGET_DEVICES includes USB unconditionally. This breaks when
> >> CONFIG_CMD_USB is not defined. Use a secondary macro to conditionally
> >> include it when CONFIG_EHCI is enabled, as we do for CONFIG_AHCI.
> > 
> > The other patches are for the next release, but maybe this fix could
> > go into 2014.10?
> 
> I agree that this is a benign bug fix, but since we don't have any
> boards not setting CONFIG_EHCI atm I don't really see the value
> for getting it into 2014.10.

FWIW I was planning on putting the whole series in #next until the next
merge window as soon as I find a some spare moments to look through it
(sorry, might take me a few more days, I'm travelling at the w/e).

Ian.

[U-Boot] [PATCH 1/7] ARM: sunxi: Fix build break when CONFIG_USB_EHCI is not defined

[Chen-Yu Tsai]

On Fri, Sep 12, 2014 at 2:57 AM, Ian Campbell <ijc@hellion.org.uk> wrote:
> On Thu, 2014-09-11 at 19:19 +0200, Hans de Goede wrote:
>> Hi Chen,
>>
>> On 09/11/2014 07:07 PM, Chen-Yu Tsai wrote:
>> > Hi Ian, Hans,
>> >
>> > On Mon, Sep 8, 2014 at 9:28 PM, Chen-Yu Tsai <wens@csie.org> wrote:
>> >> BOOT_TARGET_DEVICES includes USB unconditionally. This breaks when
>> >> CONFIG_CMD_USB is not defined. Use a secondary macro to conditionally
>> >> include it when CONFIG_EHCI is enabled, as we do for CONFIG_AHCI.
>> >
>> > The other patches are for the next release, but maybe this fix could
>> > go into 2014.10?
>>
>> I agree that this is a benign bug fix, but since we don't have any
>> boards not setting CONFIG_EHCI atm I don't really see the value
>> for getting it into 2014.10.
>
> FWIW I was planning on putting the whole series in #next until the next
> merge window as soon as I find a some spare moments to look through it
> (sorry, might take me a few more days, I'm travelling at the w/e).

OK. Thanks for the heads up.


ChenYu

[U-Boot] [PATCH 1/7] ARM: sunxi: Fix build break when CONFIG_USB_EHCI is not defined

[Ian Campbell]

On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
> BOOT_TARGET_DEVICES includes USB unconditionally. This breaks when
> CONFIG_CMD_USB is not defined. Use a secondary macro to conditionally
> include it when CONFIG_EHCI is enabled, as we do for CONFIG_AHCI.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Ian Campbell <ijc@hellion.org.uk>

[U-Boot] [PATCH 2/7] ARM: sun6i: Add base address for the new controllers in A31

[Chen-Yu Tsai]

From: Oliver Schinagl <oliver@schinagl.nl>

A31 has several new and changed memory address. This patch adds them.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/include/asm/arch-sunxi/cpu.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
index a987e51d..313e6c8 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -95,6 +95,11 @@
 #define SUNXI_MALI400_BASE		0x01c40000
 #define SUNXI_GMAC_BASE			0x01c50000
 
+#define SUNXI_DRAM_COM_BASE		0x01c62000
+#define SUNXI_DRAM_CTL_BASE		0x01c63000
+#define SUNXI_DRAM_PHY_CH1_BASE		0x01c65000
+#define SUNXI_DRAM_PHY_CH2_BASE		0x01c66000
+
 /* module sram */
 #define SUNXI_SRAM_C_BASE		0x01d00000
 
@@ -105,6 +110,10 @@
 #define SUNXI_MP_BASE			0x01e80000
 #define SUNXI_AVG_BASE			0x01ea0000
 
+#define SUNXI_PRCM_BASE			0x01f01400
+#define SUNXI_R_PIO_BASE		0x01f02c00
+#define SUNXI_P2WI_BASE			0x01f03400
+
 /* CoreSight Debug Module */
 #define SUNXI_CSDM_BASE			0x3f500000
 
-- 
2.1.0

[U-Boot] [PATCH 2/7] ARM: sun6i: Add base address for the new controllers in A31

[Ian Campbell]

On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
> From: Oliver Schinagl <oliver@schinagl.nl>
> 
> A31 has several new and changed memory address. This patch adds them.
> 
> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Ian Campbell <ijc@hellion.org.uk>

[U-Boot] [PATCH 3/7] ARM: sun6i: Add support for the new power control module found on the A31

[Chen-Yu Tsai]

From: Oliver Schinagl <oliver@schinagl.nl>

To setup clocks and control voltages.

HdG: Rename the files from the somewhat generic pmu name to prcm.{c,h}
HdG: Make the prcm code only deal with the prcm, remove axp221 bits

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens at csie.org: spacing fixes reported by checkpatch.pl]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/cpu/armv7/sunxi/Makefile      |   1 +
 arch/arm/cpu/armv7/sunxi/prcm.c        |  37 +++++
 arch/arm/include/asm/arch-sunxi/prcm.h | 238 +++++++++++++++++++++++++++++++++
 3 files changed, 276 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/sunxi/prcm.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/prcm.h

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index e9721b2..f0473d2 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -11,6 +11,7 @@ obj-y	+= timer.o
 obj-y	+= board.o
 obj-y	+= clock.o
 obj-y	+= pinmux.o
+obj-$(CONFIG_SUN6I)	+= prcm.o
 obj-$(CONFIG_SUN4I)	+= clock_sun4i.o
 obj-$(CONFIG_SUN5I)	+= clock_sun4i.o
 obj-$(CONFIG_SUN7I)	+= clock_sun4i.o
diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c
new file mode 100644
index 0000000..8f9bea9
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/prcm.c
@@ -0,0 +1,37 @@
+/*
+ * Sunxi A31 Power Management Unit
+ *
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ *
+ * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
+ *
+ * (C) Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+void prcm_init_apb0(void)
+{
+	struct sunxi_prcm_reg *prcm =
+		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+	u32 reg_val;
+
+	reg_val = readl(&prcm->apb0_gate);
+	reg_val |= PRCM_APB0_GATE_P2WI | PRCM_APB0_GATE_PIO;
+	writel(reg_val, &prcm->apb0_gate);
+
+	reg_val = readl(&prcm->apb0_reset);
+	reg_val |= PRCM_APB0_RESET_P2WI | PRCM_APB0_RESET_PIO;
+	writel(reg_val, &prcm->apb0_reset);
+}
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
new file mode 100644
index 0000000..1b40f09
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -0,0 +1,238 @@
+/*
+ * Sunxi A31 Power Management Unit register definition.
+ *
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_PRCM_H
+#define _SUNXI_PRCM_H
+
+#define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4)
+#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3)
+#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1)
+#define PRCM_CPUS_CFG_PRE_DIV(n) \
+	__PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n))
+#define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8)
+#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f)
+#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1)
+#define PRCM_CPUS_CFG_POST_DIV(n) \
+	__PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n))
+#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16)
+#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3)
+#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0
+#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1
+#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2
+#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3
+#define PRCM_CPUS_CFG_CLK_SRC_LOSC \
+	__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC)
+#define PRCM_CPUS_CFG_CLK_SRC_HOSC \
+	__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC)
+#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \
+	__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6)
+#define PRCM_CPUS_CFG_CLK_SRC_PDIV \
+	__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV)
+
+#define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0)
+#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3)
+#define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1)
+#define PRCM_APB0_RATIO_DIV(n) \
+	__PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n))
+
+#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0)
+#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1)
+
+#define PRCM_APB0_GATE_PIO (0x1 << 0)
+#define PRCM_APB0_GATE_IR (0x1 << 1)
+#define PRCM_APB0_GATE_TIMER01 (0x1 << 2)
+#define PRCM_APB0_GATE_P2WI (0x1 << 3)
+#define PRCM_APB0_GATE_UART (0x1 << 4)
+#define PRCM_APB0_GATE_1WIRE (0x1 << 5)
+#define PRCM_APB0_GATE_I2C (0x1 << 6)
+
+#define PRCM_APB0_RESET_PIO (0x1 << 0)
+#define PRCM_APB0_RESET_IR (0x1 << 1)
+#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)
+#define PRCM_APB0_RESET_P2WI (0x1 << 3)
+#define PRCM_APB0_RESET_UART (0x1 << 4)
+#define PRCM_APB0_RESET_1WIRE (0x1 << 5)
+#define PRCM_APB0_RESET_I2C (0x1 << 6)
+
+#define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0)
+#define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1)
+#define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4)
+#define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \
+	__PRCM_PLL_CTRL_USB_CLK_SRC(0x3)
+#define __PRCM_PLL_CTRL_USB_CLK_0 0x0
+#define __PRCM_PLL_CTRL_USB_CLK_1 0x1
+#define __PRCM_PLL_CTRL_USB_CLK_2 0x2
+#define __PRCM_PLL_CTRL_USB_CLK_3 0x3
+#define PRCM_PLL_CTRL_USB_CLK_0 \
+	__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_0)
+#define PRCM_PLL_CTRL_USB_CLK_1 \
+	__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_1)
+#define PRCM_PLL_CTRL_USB_CLK_2 \
+	__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_2)
+#define PRCM_PLL_CTRL_USB_CLK_3 \
+	__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_3)
+#define __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) (((n) & 0x3) << 12)
+#define PRCM_PLL_CTRL_INT_PLL_IN_SEL_MASK \
+	__PRCM_PLL_CTRL_INT_PLL_IN_SEL(0x3)
+#define PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) \
+	__PRCM_PLL_CTRL_INT_PLL_IN_SEL(n)
+#define __PRCM_PLL_CTRL_HOSC_CLK_SEL(n) (((n) & 0x3) << 20)
+#define PRCM_PLL_CTRL_HOSC_CLK_SEL_MASK \
+	__PRCM_PLL_CTRL_HOSC_CLK_SEL(0x3)
+#define __PRCM_PLL_CTRL_HOSC_CLK_0 0x0
+#define __PRCM_PLL_CTRL_HOSC_CLK_1 0x1
+#define __PRCM_PLL_CTRL_HOSC_CLK_2 0x2
+#define __PRCM_PLL_CTRL_HOSC_CLK_3 0x3
+#define PRCM_PLL_CTRL_HOSC_CLK_0 \
+	__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_0)
+#define PRCM_PLL_CTRL_HOSC_CLK_1 \
+	__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_1)
+#define PRCM_PLL_CTRL_HOSC_CLK_2 \
+	__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_2)
+#define PRCM_PLL_CTRL_HOSC_CLK_3 \
+	__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_3)
+#define PRCM_PLL_CTRL_PLL_TST_SRC_EXT (0x1 << 24)
+#define PRCM_PLL_CTRL_LDO_DIGITAL_EN (0x1 << 0)
+#define PRCM_PLL_CTRL_LDO_ANALOG_EN (0x1 << 1)
+#define PRCM_PLL_CTRL_EXT_OSC_EN (0x1 << 2)
+#define PRCM_PLL_CTRL_CLK_TST_EN (0x1 << 3)
+#define PRCM_PLL_CTRL_IN_PWR_HIGH (0x1 << 15) /* 3.3 for hi 2.5 for lo */
+#define __PRCM_PLL_CTRL_VDD_LDO_OUT(n) (((n) & 0x7) << 16)
+#define PRCM_PLL_CTRL_LDO_OUT_MASK \
+	__PRCM_PLL_CTRL_LDO_OUT(0x7)
+/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */
+#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
+	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
+#define PRCM_PLL_CTRL_LDO_OUT_H(n) \
+	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7)
+#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
+	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
+#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \
+	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)
+#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)
+
+#define PRCM_CLK_1WIRE_GATE (0x1 << 31)
+
+#define __PRCM_CLK_MOD0_M(n) (((n) & 0xf) << 0)
+#define PRCM_CLK_MOD0_M_MASK __PRCM_CLK_MOD0_M(0xf)
+#define __PRCM_CLK_MOD0_M_X(n) (n - 1)
+#define PRCM_CLK_MOD0_M(n) __PRCM_CLK_MOD0_M(__PRCM_CLK_MOD0_M_X(n))
+#define PRCM_CLK_MOD0_OUT_PHASE(n) (((n) & 0x7) << 8)
+#define PRCM_CLK_MOD0_OUT_PHASE_MASK(n) PRCM_CLK_MOD0_OUT_PHASE(0x7)
+#define _PRCM_CLK_MOD0_N(n) (((n) & 0x3) << 16)
+#define PRCM_CLK_MOD0_N_MASK __PRCM_CLK_MOD_N(0x3)
+#define __PRCM_CLK_MOD0_N_X(n) (((n) >> 1) - 1)
+#define PRCM_CLK_MOD0_N(n) __PRCM_CLK_MOD0_N(__PRCM_CLK_MOD0_N_X(n))
+#define PRCM_CLK_MOD0_SMPL_PHASE(n) (((n) & 0x7) << 20)
+#define PRCM_CLK_MOD0_SMPL_PHASE_MASK PRCM_CLK_MOD0_SMPL_PHASE(0x7)
+#define PRCM_CLK_MOD0_SRC_SEL(n) (((n) & 0x7) << 24)
+#define PRCM_CLK_MOD0_SRC_SEL_MASK PRCM_CLK_MOD0_SRC_SEL(0x7)
+#define PRCM_CLK_MOD0_GATE_EN (0x1 << 31)
+
+#define PRCM_APB0_RESET_PIO (0x1 << 0)
+#define PRCM_APB0_RESET_IR (0x1 << 1)
+#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)
+#define PRCM_APB0_RESET_P2WI (0x1 << 3)
+#define PRCM_APB0_RESET_UART (0x1 << 4)
+#define PRCM_APB0_RESET_1WIRE (0x1 << 5)
+#define PRCM_APB0_RESET_I2C (0x1 << 6)
+
+#define __PRCM_CLK_OUTD_M(n) (((n) & 0x7) << 8)
+#define PRCM_CLK_OUTD_M_MASK __PRCM_CLK_OUTD_M(0x7)
+#define __PRCM_CLK_OUTD_M_X() ((n) - 1)
+#define PRCM_CLK_OUTD_M(n) __PRCM_CLK_OUTD_M(__PRCM_CLK_OUTD_M_X(n))
+#define __PRCM_CLK_OUTD_N(n) (((n) & 0x7) << 20)
+#define PRCM_CLK_OUTD_N_MASK __PRCM_CLK_OUTD_N(0x7)
+#define __PRCM_CLK_OUTD_N_X(n) (((n) >> 1) - 1)
+#define PRCM_CLK_OUTD_N(n) __PRCM_CLK_OUTD_N(__PRCM_CLK_OUTD_N_X(n)
+#define __PRCM_CLK_OUTD_SRC_SEL(n) (((n) & 0x3) << 24)
+#define PRCM_CLK_OUTD_SRC_SEL_MASK __PRCM_CLK_OUTD_SRC_SEL(0x3)
+#define __PRCM_CLK_OUTD_SRC_LOSC2 0x0
+#define __PRCM_CLK_OUTD_SRC_LOSC 0x1
+#define __PRCM_CLK_OUTD_SRC_HOSC 0x2
+#define __PRCM_CLK_OUTD_SRC_ERR 0x3
+#define PRCM_CLK_OUTD_SRC_LOSC2 \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC2)
+#define PRCM_CLK_OUTD_SRC_LOSC \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC)
+#define PRCM_CLK_OUTD_SRC_HOSC \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_HOSC)
+#define PRCM_CLK_OUTD_SRC_ERR \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_ERR)
+#define PRCM_CLK_OUTD_EN (0x1 << 31)
+
+#define PRCM_CPU0_PWROFF (0x1 << 0)
+#define PRCM_CPU1_PWROFF (0x1 << 1)
+#define PRCM_CPU2_PWROFF (0x1 << 2)
+#define PRCM_CPU3_PWROFF (0x1 << 3)
+#define PRCM_CPU_ALL_PWROFF (0xf << 0)
+
+#define PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF (0x1 << 0)
+#define PRCM_VDD_SYS_DRAM_CH1_PAD_HOLD_PWROFF (0x1 << 1)
+#define PRCM_VDD_SYS_AVCC_A_PWROFF (0x1 << 2)
+#define PRCM_VDD_SYS_CPU0_VDD_PWROFF (0x1 << 3)
+
+#define PRCM_VDD_GPU_PWROFF (0x1 << 0)
+
+#define PRCM_VDD_SYS_RESET (0x1 << 0)
+
+#define PRCM_CPU1_PWR_CLAMP(n) (((n) & 0xff) << 0)
+#define PRCM_CPU1_PWR_CLAMP_MASK PRCM_CPU1_PWR_CLAMP(0xff)
+
+#define PRCM_CPU2_PWR_CLAMP(n) (((n) & 0xff) << 0)
+#define PRCM_CPU2_PWR_CLAMP_MASK PRCM_CPU2_PWR_CLAMP(0xff)
+
+#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0)
+#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff)
+
+#ifndef __ASSEMBLY__
+struct sunxi_prcm_reg {
+	u32 cpus_cfg;		/* 0x000 */
+	u8 res0[0x8];		/* 0x004 */
+	u32 apb0_ratio;		/* 0x00c */
+	u32 cpu0_cfg;		/* 0x010 */
+	u32 cpu1_cfg;		/* 0x014 */
+	u32 cpu2_cfg;		/* 0x018 */
+	u32 cpu3_cfg;		/* 0x01c */
+	u8 res1[0x8];		/* 0x020 */
+	u32 apb0_gate;		/* 0x028 */
+	u8 res2[0x14];		/* 0x02c */
+	u32 pll_ctrl0;		/* 0x040 */
+	u32 pll_ctrl1;		/* 0x044 */
+	u8 res3[0x8];		/* 0x048 */
+	u32 clk_1wire;		/* 0x050 */
+	u32 clk_ir;		/* 0x054 */
+	u8 res4[0x58];		/* 0x058 */
+	u32 apb0_reset;		/* 0x0b0 */
+	u8 res5[0x3c];		/* 0x0b4 */
+	u32 clk_outd;		/* 0x0f0 */
+	u8 res6[0xc];		/* 0x0f4 */
+	u32 cpu_pwroff;		/* 0x100 */
+	u8 res7[0xc];		/* 0x104 */
+	u32 vdd_sys_pwroff;	/* 0x110 */
+	u8 res8[0x4];		/* 0x114 */
+	u32 gpu_pwroff;		/* 0x118 */
+	u8 res9[0x4];		/* 0x11c */
+	u32 vdd_pwr_reset;	/* 0x120 */
+	u8 res10[0x20];		/* 0x124 */
+	u32 cpu1_pwr_clamp;	/* 0x144 */
+	u32 cpu2_pwr_clamp;	/* 0x148 */
+	u32 cpu3_pwr_clamp;	/* 0x14c */
+	u8 res11[0x30];		/* 0x150 */
+	u32 dram_pwr;		/* 0x180 */
+	u8 res12[0xc];		/* 0x184 */
+	u32 dram_tst;		/* 0x190 */
+};
+
+void prcm_init_apb0(void);
+#endif /* __ASSEMBLY__ */
+#endif /* _PRCM_H */
-- 
2.1.0

[U-Boot] [PATCH 3/7] ARM: sun6i: Add support for the new power control module found on the A31

[Ian Campbell]

On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
> From: Oliver Schinagl <oliver@schinagl.nl>
> 
> To setup clocks and control voltages.

perhaps add "... For P2WI and PIO", since that is apparently what it is
doing?

> HdG: Rename the files from the somewhat generic pmu name to prcm.{c,h}
> HdG: Make the prcm code only deal with the prcm, remove axp221 bits

I suppose these comments aren't really meaningful in the final commit
message, probably better to drop them.

> + * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work

Typo in "Allwiner"

> +	reg_val = readl(&prcm->apb0_gate);
> +	reg_val |= PRCM_APB0_GATE_P2WI | PRCM_APB0_GATE_PIO;
> +	writel(reg_val, &prcm->apb0_gate);
> +
> +	reg_val = readl(&prcm->apb0_reset);
> +	reg_val |= PRCM_APB0_RESET_P2WI | PRCM_APB0_RESET_PIO;
> +	writel(reg_val, &prcm->apb0_reset);

I think these should both use the setbits helper.

Ian.

[U-Boot] [PATCH 3/7] ARM: sun6i: Add support for the new power control module found on the A31

[Chen-Yu Tsai]

Hi,

On Mon, Sep 22, 2014 at 1:05 AM, Ian Campbell <ijc@hellion.org.uk> wrote:
> On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
>> From: Oliver Schinagl <oliver@schinagl.nl>
>>
>> To setup clocks and control voltages.
>
> perhaps add "... For P2WI and PIO", since that is apparently what it is
> doing?

Sounds good. I'll expand the message to mention what the PRCM
controls, and what we actually use.

>> HdG: Rename the files from the somewhat generic pmu name to prcm.{c,h}
>> HdG: Make the prcm code only deal with the prcm, remove axp221 bits
>
> I suppose these comments aren't really meaningful in the final commit
> message, probably better to drop them.

I was trying to keep the history of the patches intact.
If Hans agress, I can drop them.

>> + * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
>
> Typo in "Allwiner"
>
>> +     reg_val = readl(&prcm->apb0_gate);
>> +     reg_val |= PRCM_APB0_GATE_P2WI | PRCM_APB0_GATE_PIO;
>> +     writel(reg_val, &prcm->apb0_gate);
>> +
>> +     reg_val = readl(&prcm->apb0_reset);
>> +     reg_val |= PRCM_APB0_RESET_P2WI | PRCM_APB0_RESET_PIO;
>> +     writel(reg_val, &prcm->apb0_reset);
>
> I think these should both use the setbits helper.

Right. Will change them.

Thanks!

ChenYu

[U-Boot] [PATCH 3/7] ARM: sun6i: Add support for the new power control module found on the A31

[Hans de Goede]

Hi,

On 09/22/2014 04:07 AM, Chen-Yu Tsai wrote:
> Hi,
> 
> On Mon, Sep 22, 2014 at 1:05 AM, Ian Campbell <ijc@hellion.org.uk> wrote:
>> On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
>>> From: Oliver Schinagl <oliver@schinagl.nl>
>>>
>>> To setup clocks and control voltages.
>>
>> perhaps add "... For P2WI and PIO", since that is apparently what it is
>> doing?
> 
> Sounds good. I'll expand the message to mention what the PRCM
> controls, and what we actually use.
> 
>>> HdG: Rename the files from the somewhat generic pmu name to prcm.{c,h}
>>> HdG: Make the prcm code only deal with the prcm, remove axp221 bits
>>
>> I suppose these comments aren't really meaningful in the final commit
>> message, probably better to drop them.
> 
> I was trying to keep the history of the patches intact.
> If Hans agress, I can drop them.

Yes dropping them for upstreaming is fine.

Regards,

Hans

> 
>>> + * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
>>
>> Typo in "Allwiner"
>>
>>> +     reg_val = readl(&prcm->apb0_gate);
>>> +     reg_val |= PRCM_APB0_GATE_P2WI | PRCM_APB0_GATE_PIO;
>>> +     writel(reg_val, &prcm->apb0_gate);
>>> +
>>> +     reg_val = readl(&prcm->apb0_reset);
>>> +     reg_val |= PRCM_APB0_RESET_P2WI | PRCM_APB0_RESET_PIO;
>>> +     writel(reg_val, &prcm->apb0_reset);
>>
>> I think these should both use the setbits helper.
> 
> Right. Will change them.
> 
> Thanks!
> 
> ChenYu
> 

[U-Boot] [PATCH 4/7] ARM: sun6i: Add clock support

[Chen-Yu Tsai]

This patch adds the basic clocks support for the Allwinner A31 (sun6i)
processor. This code will not been compiled until the build is hooked
up in a later patch. It has been split out to keep the patches manageable.

This includes changes from the following commits from u-boot-sunxi:

a92051b ARM: sunxi: Add sun6i clock controller structure
1f72c6f ARM: sun6i: Setup the UART0 clocks
5f2e712 ARM: sunxi: Enable pll6 by default on all models
2be2f2a ARM: sunxi-mmc: Add mmc support for sun6i / A31
12e1633 ARM: sun6i: Add initial clock setup for SPL
1a9c9c6 ARM: sunxi: Split clock code into common, sun4i and sun6i code
0b194ee ARM: sun6i: Properly setup the PLL LDO in clock_init_safe
b54c626 sunxi: avoid sr32 for APB1 clock setup.
68fe29c sunxi: remove magic numbers from clock_get_pll{5,6}
c89867d sunxi: clocks: clock_get_pll5 prototype and coding style
501ab1e ARM: sunxi: Fix sun6i PLL6 settings
37f669b ARM: sunxi: Fix macro names for mmc and uart reset offsets
61de1e6 ARM: sunxi: Correct comment for MBUS1 register in sun6i clock definitions

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens at csie.org: styling fixes reported by checkpatch.pl]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
---
 arch/arm/cpu/armv7/sunxi/Makefile             |   1 +
 arch/arm/cpu/armv7/sunxi/clock_sun6i.c        | 107 ++++++++++++++
 arch/arm/include/asm/arch-sunxi/clock.h       |   4 +
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 205 ++++++++++++++++++++++++++
 4 files changed, 317 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/sunxi/clock_sun6i.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/clock_sun6i.h

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index f0473d2..2a42dca 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -14,6 +14,7 @@ obj-y	+= pinmux.o
 obj-$(CONFIG_SUN6I)	+= prcm.o
 obj-$(CONFIG_SUN4I)	+= clock_sun4i.o
 obj-$(CONFIG_SUN5I)	+= clock_sun4i.o
+obj-$(CONFIG_SUN6I)	+= clock_sun6i.o
 obj-$(CONFIG_SUN7I)	+= clock_sun4i.o
 
 ifndef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
new file mode 100644
index 0000000..28fc54f
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -0,0 +1,107 @@
+/*
+ * sun6i specific clock code
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+#ifdef CONFIG_SPL_BUILD
+void clock_init_safe(void)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	struct sunxi_prcm_reg * const prcm =
+		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+	/* Set PLL ldo voltage without this PLL6 does not work properly */
+	writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
+		PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
+		PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
+	writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
+		PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
+		PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
+	writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
+		PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140),
+		&prcm->pll_ctrl1);
+
+	/* AXI and PLL1 settings from boot0 / boot1, PLL1 set to 486 Mhz */
+	writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+	       ATB_DIV_2 << ATB_DIV_SHIFT |
+	       CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
+	       &ccm->cpu_axi_cfg);
+	writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
+	sdelay(200);
+	writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+	       ATB_DIV_2 << ATB_DIV_SHIFT |
+	       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
+	       &ccm->cpu_axi_cfg);
+
+	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+}
+#endif
+
+void clock_init_uart(void)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	/* uart clock source is apb2 */
+	writel(APB2_CLK_SRC_OSC24M|
+	       APB2_CLK_RATE_N_1|
+	       APB2_CLK_RATE_M(1),
+	       &ccm->apb2_div);
+
+	/* open the clock for uart */
+	setbits_le32(&ccm->apb2_gate,
+		     CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
+				       CONFIG_CONS_INDEX - 1));
+
+	/* deassert uart reset */
+	setbits_le32(&ccm->apb2_reset_cfg,
+		     1 << (APB2_RESET_UART_SHIFT +
+			   CONFIG_CONS_INDEX - 1));
+
+	/* Dup with clock_init_safe(), drop once sun6i SPL support lands */
+	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+}
+
+int clock_twi_onoff(int port, int state)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	if (port > 3)
+		return -1;
+
+	/* set the apb clock gate for twi */
+	if (state)
+		setbits_le32(&ccm->apb2_gate,
+			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
+	else
+		clrbits_le32(&ccm->apb2_gate,
+			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
+
+	return 0;
+}
+
+unsigned int clock_get_pll6(void)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	uint32_t rval = readl(&ccm->pll6_cfg);
+	int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
+	int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
+	return 24000000 * n * k / 2;
+}
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
index 5669f39..8f5d860 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -15,7 +15,11 @@
 #define CLK_GATE_CLOSE			0x0
 
 /* clock control module regs definition */
+#ifdef CONFIG_SUN6I
+#include <asm/arch/clock_sun6i.h>
+#else
 #include <asm/arch/clock_sun4i.h>
+#endif
 
 #ifndef __ASSEMBLY__
 int clock_init(void);
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
new file mode 100644
index 0000000..1397b35
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -0,0 +1,205 @@
+/*
+ * sun6i clock register definitions
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_CLOCK_SUN6I_H
+#define _SUNXI_CLOCK_SUN6I_H
+
+struct sunxi_ccm_reg {
+	u32 pll1_cfg;		/* 0x00 pll1 control */
+	u32 reserved0;
+	u32 pll2_cfg;		/* 0x08 pll2 control */
+	u32 reserved1;
+	u32 pll3_cfg;		/* 0x10 pll3 control */
+	u32 reserved2;
+	u32 pll4_cfg;		/* 0x18 pll4 control */
+	u32 reserved3;
+	u32 pll5_cfg;		/* 0x20 pll5 control */
+	u32 reserved4;
+	u32 pll6_cfg;		/* 0x28 pll6 control */
+	u32 reserved5;
+	u32 pll7_cfg;		/* 0x30 pll7 control */
+	u32 reserved6;
+	u32 pll8_cfg;		/* 0x38 pll8 control */
+	u32 reserved7;
+	u32 mipi_pll_cfg;	/* 0x40 MIPI pll control */
+	u32 pll9_cfg;		/* 0x44 pll9 control */
+	u32 pll10_cfg;		/* 0x48 pll10 control */
+	u32 reserved8;
+	u32 cpu_axi_cfg;	/* 0x50 CPU/AXI divide ratio */
+	u32 ahb1_apb1_div;	/* 0x54 AHB1/APB1 divide ratio */
+	u32 apb2_div;		/* 0x58 APB2 divide ratio */
+	u32 axi_gate;		/* 0x5c axi module clock gating */
+	u32 ahb_gate0;		/* 0x60 ahb module clock gating 0 */
+	u32 ahb_gate1;		/* 0x64 ahb module clock gating 1 */
+	u32 apb1_gate;		/* 0x68 apb1 module clock gating */
+	u32 apb2_gate;		/* 0x6c apb2 module clock gating */
+	u32 reserved9[4];
+	u32 nand0_clk_cfg;	/* 0x80 nand0 clock control */
+	u32 nand1_clk_cfg;	/* 0x84 nand1 clock control */
+	u32 sd0_clk_cfg;	/* 0x88 sd0 clock control */
+	u32 sd1_clk_cfg;	/* 0x8c sd1 clock control */
+	u32 sd2_clk_cfg;	/* 0x90 sd2 clock control */
+	u32 sd3_clk_cfg;	/* 0x94 sd3 clock control */
+	u32 ts_clk_cfg;		/* 0x98 transport stream clock control */
+	u32 ss_clk_cfg;		/* 0x9c security system clock control */
+	u32 spi0_clk_cfg;	/* 0xa0 spi0 clock control */
+	u32 spi1_clk_cfg;	/* 0xa4 spi1 clock control */
+	u32 spi2_clk_cfg;	/* 0xa8 spi2 clock control */
+	u32 spi3_clk_cfg;	/* 0xac spi3 clock control */
+	u32 i2s0_clk_cfg;	/* 0xb0 I2S0 clock control*/
+	u32 i2s1_clk_cfg;	/* 0xb4 I2S1 clock control */
+	u32 reserved10[2];
+	u32 spdif_clk_cfg;	/* 0xc0 SPDIF clock control */
+	u32 reserved11[2];
+	u32 usb_clk_cfg;	/* 0xcc USB clock control */
+	u32 gmac_clk_cfg;	/* 0xd0 GMAC clock control */
+	u32 reserved12[7];
+	u32 mdfs_clk_cfg;	/* 0xf0 MDFS clock control */
+	u32 dram_clk_cfg;	/* 0xf4 DRAM configuration clock control */
+	u32 reserved13[2];
+	u32 dram_clk_gate;	/* 0x100 DRAM module gating */
+	u32 be0_clk_cfg;	/* 0x104 BE0 module clock */
+	u32 be1_clk_cfg;	/* 0x108 BE1 module clock */
+	u32 fe0_clk_cfg;	/* 0x10c FE0 module clock */
+	u32 fe1_clk_cfg;	/* 0x110 FE1 module clock */
+	u32 mp_clk_cfg;		/* 0x114 MP module clock */
+	u32 lcd0_ch0_clk_cfg;	/* 0x118 LCD0 CH0 module clock */
+	u32 lcd1_ch0_clk_cfg;	/* 0x11c LCD1 CH0 module clock */
+	u32 reserved14[3];
+	u32 lcd0_ch1_clk_cfg;	/* 0x12c LCD0 CH1 module clock */
+	u32 lcd1_ch1_clk_cfg;	/* 0x130 LCD1 CH1 module clock */
+	u32 csi0_clk_cfg;	/* 0x134 CSI0 module clock */
+	u32 csi1_clk_cfg;	/* 0x138 CSI1 module clock */
+	u32 ve_clk_cfg;		/* 0x13c VE module clock */
+	u32 adda_clk_cfg;	/* 0x140 ADDA module clock */
+	u32 avs_clk_cfg;	/* 0x144 AVS module clock */
+	u32 dmic_clk_cfg;	/* 0x148 Digital Mic module clock*/
+	u32 reserved15;
+	u32 hdmi_clk_cfg;	/* 0x150 HDMI module clock */
+	u32 ps_clk_cfg;		/* 0x154 PS module clock */
+	u32 mtc_clk_cfg;	/* 0x158 MTC module clock */
+	u32 mbus0_clk_cfg;	/* 0x15c MBUS0 module clock */
+	u32 mbus1_clk_cfg;	/* 0x160 MBUS1 module clock */
+	u32 reserved16;
+	u32 mipi_dsi_clk_cfg;	/* 0x168 MIPI DSI clock control */
+	u32 mipi_csi_clk_cfg;	/* 0x16c MIPI CSI clock control */
+	u32 reserved17[4];
+	u32 iep_drc0_clk_cfg;	/* 0x180 IEP DRC0 module clock */
+	u32 iep_drc1_clk_cfg;	/* 0x184 IEP DRC1 module clock */
+	u32 iep_deu0_clk_cfg;	/* 0x188 IEP DEU0 module clock */
+	u32 iep_deu1_clk_cfg;	/* 0x18c IEP DEU1 module clock */
+	u32 reserved18[4];
+	u32 gpu_core_clk_cfg;	/* 0x1a0 GPU core clock config */
+	u32 gpu_mem_clk_cfg;	/* 0x1a4 GPU memory clock config */
+	u32 gpu_hyd_clk_cfg;	/* 0x1a0 GPU HYD clock config */
+	u32 reserved19[21];
+	u32 pll_lock;		/* 0x200 PLL Lock Time */
+	u32 pll1_lock;		/* 0x204 PLL1 Lock Time */
+	u32 reserved20[6];
+	u32 pll1_bias_cfg;	/* 0x220 PLL1 Bias config */
+	u32 pll2_bias_cfg;	/* 0x224 PLL2 Bias config */
+	u32 pll3_bias_cfg;	/* 0x228 PLL3 Bias config */
+	u32 pll4_bias_cfg;	/* 0x22c PLL4 Bias config */
+	u32 pll5_bias_cfg;	/* 0x230 PLL5 Bias config */
+	u32 pll6_bias_cfg;	/* 0x234 PLL6 Bias config */
+	u32 pll7_bias_cfg;	/* 0x238 PLL7 Bias config */
+	u32 pll8_bias_cfg;	/* 0x23c PLL8 Bias config */
+	u32 mipi_bias_cfg;	/* 0x240 MIPI Bias config */
+	u32 pll9_bias_cfg;	/* 0x244 PLL9 Bias config */
+	u32 pll10_bias_cfg;	/* 0x248 PLL10 Bias config */
+	u32 reserved21[13];
+	u32 pll1_pattern_cfg;	/* 0x280 PLL1 Pattern config */
+	u32 pll2_pattern_cfg;	/* 0x284 PLL2 Pattern config */
+	u32 pll3_pattern_cfg;	/* 0x288 PLL3 Pattern config */
+	u32 pll4_pattern_cfg;	/* 0x28c PLL4 Pattern config */
+	u32 pll5_pattern_cfg;	/* 0x290 PLL5 Pattern config */
+	u32 pll6_pattern_cfg;	/* 0x294 PLL6 Pattern config */
+	u32 pll7_pattern_cfg;	/* 0x298 PLL7 Pattern config */
+	u32 pll8_pattern_cfg;	/* 0x29c PLL8 Pattern config */
+	u32 mipi_pattern_cfg;	/* 0x2a0 MIPI Pattern config */
+	u32 pll9_pattern_cfg;	/* 0x2a4 PLL9 Pattern config */
+	u32 pll10_pattern_cfg;	/* 0x2a8 PLL10 Pattern config */
+	u32 reserved22[5];
+	u32 ahb_reset0_cfg;	/* 0x2c0 AHB1 Reset 0 config */
+	u32 ahb_reset1_cfg;	/* 0x2c4 AHB1 Reset 1 config */
+	u32 ahb_reset2_cfg;	/* 0x2c8 AHB1 Reset 2 config */
+	u32 reserved23;
+	u32 apb1_reset_cfg;	/* 0x2d0 APB1 Reset config */
+	u32 reserved24;
+	u32 apb2_reset_cfg;	/* 0x2d8 APB2 Reset config */
+};
+
+/* apb2 bit field */
+#define APB2_CLK_SRC_LOSC		(0x0 << 24)
+#define APB2_CLK_SRC_OSC24M		(0x1 << 24)
+#define APB2_CLK_SRC_PLL6		(0x2 << 24)
+#define APB2_CLK_SRC_MASK		(0x3 << 24)
+#define APB2_CLK_RATE_N_1		(0x0 << 16)
+#define APB2_CLK_RATE_N_2		(0x1 << 16)
+#define APB2_CLK_RATE_N_4		(0x2 << 16)
+#define APB2_CLK_RATE_N_8		(0x3 << 16)
+#define APB2_CLK_RATE_N_MASK		(3 << 16)
+#define APB2_CLK_RATE_M(m)		(((m)-1) << 0)
+#define APB2_CLK_RATE_M_MASK            (0x1f << 0)
+
+/* apb2 gate field */
+#define APB2_GATE_UART_SHIFT	(16)
+#define APB2_GATE_UART_MASK		(0xff << APB2_GATE_UART_SHIFT)
+#define APB2_GATE_TWI_SHIFT	(0)
+#define APB2_GATE_TWI_MASK		(0xf << APB2_GATE_TWI_SHIFT)
+
+/* cpu_axi_cfg bits */
+#define AXI_DIV_SHIFT			0
+#define ATB_DIV_SHIFT			8
+#define CPU_CLK_SRC_SHIFT		16
+
+#define AXI_DIV_1			0
+#define AXI_DIV_2			1
+#define AXI_DIV_3			2
+#define AXI_DIV_4			3
+#define ATB_DIV_1			0
+#define ATB_DIV_2			1
+#define ATB_DIV_4			2
+#define CPU_CLK_SRC_OSC24M		1
+#define CPU_CLK_SRC_PLL1		2
+
+#define PLL1_CFG_DEFAULT		0x90011b21
+
+#define PLL6_CFG_DEFAULT		0x90041811
+
+#define CCM_PLL6_CTRL_N_SHIFT		8
+#define CCM_PLL6_CTRL_N_MASK		(0x1f << CCM_PLL6_CTRL_N_SHIFT)
+#define CCM_PLL6_CTRL_K_SHIFT		4
+#define CCM_PLL6_CTRL_K_MASK		(0x3 << CCM_PLL6_CTRL_K_SHIFT)
+
+#define AHB_GATE_OFFSET_MMC3		11
+#define AHB_GATE_OFFSET_MMC2		10
+#define AHB_GATE_OFFSET_MMC1		9
+#define AHB_GATE_OFFSET_MMC0		8
+#define AHB_GATE_OFFSET_MMC(n)		(AHB_GATE_OFFSET_MMC0 + (n))
+
+#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
+#define CCM_MMC_CTRL_PLL6   (0x1 << 24)
+
+#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
+
+#define AHB_RESET_OFFSET_MMC3		11
+#define AHB_RESET_OFFSET_MMC2		10
+#define AHB_RESET_OFFSET_MMC1		9
+#define AHB_RESET_OFFSET_MMC0		8
+#define AHB_RESET_OFFSET_MMC(n)		(AHB_RESET_OFFSET_MMC0 + (n))
+
+/* apb2 reset */
+#define APB2_RESET_UART_SHIFT		(16)
+#define APB2_RESET_UART_MASK		(0xff << APB2_RESET_UART_SHIFT)
+#define APB2_RESET_TWI_SHIFT		(0)
+#define APB2_RESET_TWI_MASK		(0xf << APB2_RESET_TWI_SHIFT)
+
+#endif /* _SUNXI_CLOCK_SUN6I_H */
-- 
2.1.0

[U-Boot] [PATCH 4/7] ARM: sun6i: Add clock support

[Ian Campbell]

On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:

> +#ifdef CONFIG_SPL_BUILD

Since there is no SPL support this is dead code right now, correct?

I'm wondering whether we should leave it out of mainline until the SPL
stuff is done, so SPL will be upstreamed all at once. What do others
think?

> +	/* Set PLL ldo voltage without this PLL6 does not work properly */

Is "this" here the doing it 3 times bit? If that's deliberate then
please say so explicitly. e.g. "Set PLL LDO voltage 3 times, without ...
etc"), if it's not deliberate then please fix ;-)

I'm assuming this is one of those "no docs, allwinner code did it but
nobody knows why it works" scenarios. Of course if the reason is
known/doc'd then please add a reference.

> +	writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
> +		PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
> +		PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
> +	writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
> +		PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
> +		PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
> +	writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
> +		PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140),
> +		&prcm->pll_ctrl1);
[...]

Ian.

[U-Boot] [PATCH 4/7] ARM: sun6i: Add clock support

[Chen-Yu Tsai]

On Mon, Sep 22, 2014 at 2:35 AM, Ian Campbell <ijc@hellion.org.uk> wrote:
> On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
>
>> +#ifdef CONFIG_SPL_BUILD
>
> Since there is no SPL support this is dead code right now, correct?

This was part of Hans' attempt to support SPL. It was not finished.

> I'm wondering whether we should leave it out of mainline until the SPL
> stuff is done, so SPL will be upstreamed all at once. What do others
> think?

Sounds reasonable.

>> +     /* Set PLL ldo voltage without this PLL6 does not work properly */
>
> Is "this" here the doing it 3 times bit? If that's deliberate then
> please say so explicitly. e.g. "Set PLL LDO voltage 3 times, without ...
> etc"), if it's not deliberate then please fix ;-)

Hans, if you could enlighten us? :)

> I'm assuming this is one of those "no docs, allwinner code did it but
> nobody knows why it works" scenarios. Of course if the reason is
> known/doc'd then please add a reference.

I looked at the boot1 sources we recently got.

First it sets PRCM_PLL_CTRL_LDO_KEY to enable write access to the other
values.

Then it sets PRCM_PLL_CTRL_IN_PWR_HIGH (which is the default) and
PRCM_PLL_CTRL_LDO_OUT_L(1140) in one call.

Then it busy loops for some time to wait for it to stabilize.

>> +     writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
>> +             PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
>> +             PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
>> +     writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
>> +             PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
>> +             PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
>> +     writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
>> +             PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140),
>> +             &prcm->pll_ctrl1);
> [...]

ChenYu

[U-Boot] [PATCH 4/7] ARM: sun6i: Add clock support

[Ian Campbell]

On Mon, 2014-09-22 at 20:47 +0800, Chen-Yu Tsai wrote:
> On Mon, Sep 22, 2014 at 2:35 AM, Ian Campbell <ijc@hellion.org.uk> wrote:
> > On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
> >> +     /* Set PLL ldo voltage without this PLL6 does not work properly */
> >
> > Is "this" here the doing it 3 times bit? If that's deliberate then
> > please say so explicitly. e.g. "Set PLL LDO voltage 3 times, without ...
> > etc"), if it's not deliberate then please fix ;-)
> 
> Hans, if you could enlighten us? :)
> 
> > I'm assuming this is one of those "no docs, allwinner code did it but
> > nobody knows why it works" scenarios. Of course if the reason is
> > known/doc'd then please add a reference.
> 
> I looked at the boot1 sources we recently got.
> 
> First it sets PRCM_PLL_CTRL_LDO_KEY to enable write access to the other
> values.
> 
> Then it sets PRCM_PLL_CTRL_IN_PWR_HIGH (which is the default) and
> PRCM_PLL_CTRL_LDO_OUT_L(1140) in one call.
> 
> Then it busy loops for some time to wait for it to stabilize.

My guess would be that 3 writes happens to cause enough time to pass
that things have (often!) stabilised, which is certainly not as good as
an explicit waiting busy loop. But as you say lets see what Hans says.

> 
> >> +     writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
> >> +             PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
> >> +             PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
> >> +     writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
> >> +             PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
> >> +             PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
> >> +     writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
> >> +             PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140),
> >> +             &prcm->pll_ctrl1);
> > [...]
> 
> ChenYu
> 

[U-Boot] [PATCH 4/7] ARM: sun6i: Add clock support

[Chen-Yu Tsai]

On Mon, Sep 22, 2014 at 9:15 PM, Ian Campbell <ijc@hellion.org.uk> wrote:
> On Mon, 2014-09-22 at 20:47 +0800, Chen-Yu Tsai wrote:
>> On Mon, Sep 22, 2014 at 2:35 AM, Ian Campbell <ijc@hellion.org.uk> wrote:
>> > On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
>> >> +     /* Set PLL ldo voltage without this PLL6 does not work properly */
>> >
>> > Is "this" here the doing it 3 times bit? If that's deliberate then
>> > please say so explicitly. e.g. "Set PLL LDO voltage 3 times, without ...
>> > etc"), if it's not deliberate then please fix ;-)
>>
>> Hans, if you could enlighten us? :)
>>
>> > I'm assuming this is one of those "no docs, allwinner code did it but
>> > nobody knows why it works" scenarios. Of course if the reason is
>> > known/doc'd then please add a reference.
>>
>> I looked at the boot1 sources we recently got.
>>
>> First it sets PRCM_PLL_CTRL_LDO_KEY to enable write access to the other
>> values.
>>
>> Then it sets PRCM_PLL_CTRL_IN_PWR_HIGH (which is the default) and
>> PRCM_PLL_CTRL_LDO_OUT_L(1140) in one call.
>>
>> Then it busy loops for some time to wait for it to stabilize.
>
> My guess would be that 3 writes happens to cause enough time to pass
> that things have (often!) stabilised, which is certainly not as good as
> an explicit waiting busy loop. But as you say lets see what Hans says.

FYI I'm dropping this part from the patch, so this discussion is for
future reference. :)

>> >> +     writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
>> >> +             PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
>> >> +             PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
>> >> +     writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
>> >> +             PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
>> >> +             PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
>> >> +     writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
>> >> +             PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140),
>> >> +             &prcm->pll_ctrl1);
>> > [...]

[U-Boot] [PATCH 4/7] ARM: sun6i: Add clock support

[Hans de Goede]

Hi,

On 09/22/2014 02:47 PM, Chen-Yu Tsai wrote:
> On Mon, Sep 22, 2014 at 2:35 AM, Ian Campbell <ijc@hellion.org.uk> wrote:
>> On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
>>
>>> +#ifdef CONFIG_SPL_BUILD
>>
>> Since there is no SPL support this is dead code right now, correct?
> 
> This was part of Hans' attempt to support SPL. It was not finished.
> 
>> I'm wondering whether we should leave it out of mainline until the SPL
>> stuff is done, so SPL will be upstreamed all at once. What do others
>> think?
> 
> Sounds reasonable.
> 
>>> +     /* Set PLL ldo voltage without this PLL6 does not work properly */
>>
>> Is "this" here the doing it 3 times bit? If that's deliberate then
>> please say so explicitly. e.g. "Set PLL LDO voltage 3 times, without ...
>> etc"), if it's not deliberate then please fix ;-)
> 
> Hans, if you could enlighten us? :)

If you take a closer look at the code you will see not all 3 writes are the
same:

        /* Set PLL ldo voltage without this PLL6 does not work properly */
        writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
                PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
                PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
        writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
                PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
                PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
        writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
                PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140),
                &prcm->pll_ctrl1);

This register is locked with a so called "key", the first write is to set
the key (and has everything else the same in case the key is already
written). The second write actually makes the changes, and the third write
clears the key bits.

I guess this may need some better comments :)

Regards,

Hans

[U-Boot] [PATCH 4/7] ARM: sun6i: Add clock support

[Ian Campbell]

On Sun, 2014-09-28 at 17:23 +0200, Hans de Goede wrote:
> If you take a closer look at the code you will see not all 3 writes are the
> same:
> 
>         /* Set PLL ldo voltage without this PLL6 does not work properly */
>         writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
>                 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
>                 PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
>         writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
>                 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
>                 PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
>         writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
>                 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140),
>                 &prcm->pll_ctrl1);
> 
> This register is locked with a so called "key", the first write is to set
> the key (and has everything else the same in case the key is already
> written). The second write actually makes the changes, and the third write
> clears the key bits.

Even after staring really hard I still don't see what differs in the
first and second ones ;-)

> I guess this may need some better comments :)

Perhaps setclr_bits and friends might help make it obvious what is
changing at each phase by allowing the other values to be omitted?

Or maybe a #define for the settings themselves so that the remaining
bits stand out more?

Ian.

[U-Boot] [PATCH 4/7] ARM: sun6i: Add clock support

[Hans de Goede]

Hi,

On 09/28/2014 05:37 PM, Ian Campbell wrote:
> On Sun, 2014-09-28 at 17:23 +0200, Hans de Goede wrote:
>> If you take a closer look at the code you will see not all 3 writes are the
>> same:
>>
>>         /* Set PLL ldo voltage without this PLL6 does not work properly */
>>         writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
>>                 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
>>                 PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
>>         writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
>>                 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
>>                 PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
>>         writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
>>                 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140),
>>                 &prcm->pll_ctrl1);
>>
>> This register is locked with a so called "key", the first write is to set
>> the key (and has everything else the same in case the key is already
>> written). The second write actually makes the changes, and the third write
>> clears the key bits.
> 
> Even after staring really hard I still don't see what differs in the
> first and second ones ;-)

Right, that is because there is no change between the first 2, I guess
using setclr_bits to first only set the key, then only the bits, then
only clear the key would be a good idea here :)

Regards,

Hans

[U-Boot] [PATCH 4/7] ARM: sun6i: Add clock support

[Olliver Schinagl]

On 28-09-14 17:42, Hans de Goede wrote:
> Hi,
>
> On 09/28/2014 05:37 PM, Ian Campbell wrote:
>> On Sun, 2014-09-28 at 17:23 +0200, Hans de Goede wrote:
>>> If you take a closer look at the code you will see not all 3 writes are the
>>> same:
>>>
>>>          /* Set PLL ldo voltage without this PLL6 does not work properly */
>>>          writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
>>>                  PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
>>>                  PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
>>>          writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
>>>                  PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
>>>                  PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
>>>          writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
>>>                  PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140),
>>>                  &prcm->pll_ctrl1);
>>>
>>> This register is locked with a so called "key", the first write is to set
>>> the key (and has everything else the same in case the key is already
>>> written). The second write actually makes the changes, and the third write
>>> clears the key bits.
>> Even after staring really hard I still don't see what differs in the
>> first and second ones ;-)
> Right, that is because there is no change between the first 2, I guess
> using setclr_bits to first only set the key, then only the bits, then
> only clear the key would be a good idea here :)
I think I wrote those lines ages ago, and I think i used writel instead 
of setclr_bits and friends initially, was to first 'copy' over the 
original implementation and swap magic values for defines. Once that 
could be verified to working, change over to prettier code :)

Granted, Since we have little docs and no comments, merging the first 
two lines requires some testing, which without hardware is near 
impossible. It would have probably worked having only set the key on the 
first line, key + values on the second and leave 3rd as is.

Olliver
>
> Regards,
>
> Hans

[U-Boot] [PATCH 5/7] ARM: sunxi-mmc: Add mmc support for sun6i / A31

[Chen-Yu Tsai]

From: Hans de Goede <hdegoede@redhat.com>

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens at csie.org: use setbits_le32 for reset control, drop obsolete changes,
		squash "sunxi-mmc: sun6i has its fifo at a different address"]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/include/asm/arch-sunxi/mmc.h | 2 --
 drivers/mmc/sunxi_mmc.c               | 9 +++++++++
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
index 53196e3..bafde4b 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -42,8 +42,6 @@ struct sunxi_mmc {
 	u32 idie;		/* 0x8c internal DMA interrupt enable */
 	u32 chda;		/* 0x90 */
 	u32 cbda;		/* 0x94 */
-	u32 res1[26];
-	u32 fifo;		/* 0x100 FIFO access address */
 };
 
 #define SUNXI_MMC_CLK_POWERSAVE		(0x1 << 17)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index d4e574f..b035bba 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -57,7 +57,11 @@ static int mmc_resource_init(int sdc_no)
 		printf("Wrong mmc number %d\n", sdc_no);
 		return -1;
 	}
+#ifdef CONFIG_SUN6I
+	mmchost->database = (unsigned int)mmchost->reg + 0x200;
+#else
 	mmchost->database = (unsigned int)mmchost->reg + 0x100;
+#endif
 	mmchost->mmc_no = sdc_no;
 
 	return 0;
@@ -75,6 +79,11 @@ static int mmc_clk_io_on(int sdc_no)
 	/* config ahb clock */
 	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 
+#if defined(CONFIG_SUN6I)
+	/* unassert reset */
+	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
+#endif
+
 	/* config mod clock */
 	pll_clk = clock_get_pll6();
 	/* should be close to 100 MHz but no more, so round up */
-- 
2.1.0

[U-Boot] [PATCH 5/7] ARM: sunxi-mmc: Add mmc support for sun6i / A31

[Ian Campbell]

On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
> From: Hans de Goede <hdegoede@redhat.com>
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> [wens at csie.org: use setbits_le32 for reset control, drop obsolete changes,
> 		squash "sunxi-mmc: sun6i has its fifo at a different address"]
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Adding CC to Pantelis (MMC custodian).

Pantelis, once you are happy with this I propose we take this via the
sunxi tree along with the rest of the series.

For my part I only have nitpicks:

> ---
>  arch/arm/include/asm/arch-sunxi/mmc.h | 2 --
>  drivers/mmc/sunxi_mmc.c               | 9 +++++++++
>  2 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
> index 53196e3..bafde4b 100644
> --- a/arch/arm/include/asm/arch-sunxi/mmc.h
> +++ b/arch/arm/include/asm/arch-sunxi/mmc.h
> @@ -42,8 +42,6 @@ struct sunxi_mmc {
>  	u32 idie;		/* 0x8c internal DMA interrupt enable */
>  	u32 chda;		/* 0x90 */
>  	u32 cbda;		/* 0x94 */
> -	u32 res1[26];
> -	u32 fifo;		/* 0x100 FIFO access address */

This seems unrelated to the stated purpose of the commit, should
probably be a separate cleanup.

>  };
>  
>  #define SUNXI_MMC_CLK_POWERSAVE		(0x1 << 17)
> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> index d4e574f..b035bba 100644
> --- a/drivers/mmc/sunxi_mmc.c
> +++ b/drivers/mmc/sunxi_mmc.c
> @@ -57,7 +57,11 @@ static int mmc_resource_init(int sdc_no)
>  		printf("Wrong mmc number %d\n", sdc_no);
>  		return -1;
>  	}
> +#ifdef CONFIG_SUN6I
> +	mmchost->database = (unsigned int)mmchost->reg + 0x200;
> +#else
>  	mmchost->database = (unsigned int)mmchost->reg + 0x100;
> +#endif

Adding a #define to ./include/configs/sun?i.h would be preferred, I
think.

Ian.

[U-Boot] [PATCH 5/7] ARM: sunxi-mmc: Add mmc support for sun6i / A31

[Chen-Yu Tsai]

On Mon, Sep 22, 2014 at 2:44 AM, Ian Campbell <ijc@hellion.org.uk> wrote:
> On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
>> From: Hans de Goede <hdegoede@redhat.com>
>>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>> [wens at csie.org: use setbits_le32 for reset control, drop obsolete changes,
>>               squash "sunxi-mmc: sun6i has its fifo at a different address"]
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>
> Adding CC to Pantelis (MMC custodian).
>
> Pantelis, once you are happy with this I propose we take this via the
> sunxi tree along with the rest of the series.
>
> For my part I only have nitpicks:
>
>> ---
>>  arch/arm/include/asm/arch-sunxi/mmc.h | 2 --
>>  drivers/mmc/sunxi_mmc.c               | 9 +++++++++
>>  2 files changed, 9 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
>> index 53196e3..bafde4b 100644
>> --- a/arch/arm/include/asm/arch-sunxi/mmc.h
>> +++ b/arch/arm/include/asm/arch-sunxi/mmc.h
>> @@ -42,8 +42,6 @@ struct sunxi_mmc {
>>       u32 idie;               /* 0x8c internal DMA interrupt enable */
>>       u32 chda;               /* 0x90 */
>>       u32 cbda;               /* 0x94 */
>> -     u32 res1[26];
>> -     u32 fifo;               /* 0x100 FIFO access address */
>
> This seems unrelated to the stated purpose of the commit, should
> probably be a separate cleanup.

This was part of "sunxi-mmc: sun6i has its fifo at a different address",
but yeah, it definitely looks like a separate cleanup now. I'll split it
out.

>>  };
>>
>>  #define SUNXI_MMC_CLK_POWERSAVE              (0x1 << 17)
>> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
>> index d4e574f..b035bba 100644
>> --- a/drivers/mmc/sunxi_mmc.c
>> +++ b/drivers/mmc/sunxi_mmc.c
>> @@ -57,7 +57,11 @@ static int mmc_resource_init(int sdc_no)
>>               printf("Wrong mmc number %d\n", sdc_no);
>>               return -1;
>>       }
>> +#ifdef CONFIG_SUN6I
>> +     mmchost->database = (unsigned int)mmchost->reg + 0x200;
>> +#else
>>       mmchost->database = (unsigned int)mmchost->reg + 0x100;
>> +#endif
>
> Adding a #define to ./include/configs/sun?i.h would be preferred, I
> think.

Sounds reasonable. I wonder what else (in other drivers) we should
move over there.

ChenYu

[U-Boot] [PATCH 5/7] ARM: sunxi-mmc: Add mmc support for sun6i / A31

[Chen-Yu Tsai]

On Mon, Sep 22, 2014 at 10:11 AM, Chen-Yu Tsai <wens@csie.org> wrote:
> On Mon, Sep 22, 2014 at 2:44 AM, Ian Campbell <ijc@hellion.org.uk> wrote:
>> On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
>>> From: Hans de Goede <hdegoede@redhat.com>
>>>
>>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>>> [wens at csie.org: use setbits_le32 for reset control, drop obsolete changes,
>>>               squash "sunxi-mmc: sun6i has its fifo at a different address"]
>>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>>
>> Adding CC to Pantelis (MMC custodian).
>>
>> Pantelis, once you are happy with this I propose we take this via the
>> sunxi tree along with the rest of the series.
>>
>> For my part I only have nitpicks:
>>
>>> ---
>>>  arch/arm/include/asm/arch-sunxi/mmc.h | 2 --
>>>  drivers/mmc/sunxi_mmc.c               | 9 +++++++++
>>>  2 files changed, 9 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
>>> index 53196e3..bafde4b 100644
>>> --- a/arch/arm/include/asm/arch-sunxi/mmc.h
>>> +++ b/arch/arm/include/asm/arch-sunxi/mmc.h
>>> @@ -42,8 +42,6 @@ struct sunxi_mmc {
>>>       u32 idie;               /* 0x8c internal DMA interrupt enable */
>>>       u32 chda;               /* 0x90 */
>>>       u32 cbda;               /* 0x94 */
>>> -     u32 res1[26];
>>> -     u32 fifo;               /* 0x100 FIFO access address */
>>
>> This seems unrelated to the stated purpose of the commit, should
>> probably be a separate cleanup.
>
> This was part of "sunxi-mmc: sun6i has its fifo at a different address",
> but yeah, it definitely looks like a separate cleanup now. I'll split it
> out.
>
>>>  };
>>>
>>>  #define SUNXI_MMC_CLK_POWERSAVE              (0x1 << 17)
>>> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
>>> index d4e574f..b035bba 100644
>>> --- a/drivers/mmc/sunxi_mmc.c
>>> +++ b/drivers/mmc/sunxi_mmc.c
>>> @@ -57,7 +57,11 @@ static int mmc_resource_init(int sdc_no)
>>>               printf("Wrong mmc number %d\n", sdc_no);
>>>               return -1;
>>>       }
>>> +#ifdef CONFIG_SUN6I
>>> +     mmchost->database = (unsigned int)mmchost->reg + 0x200;
>>> +#else
>>>       mmchost->database = (unsigned int)mmchost->reg + 0x100;
>>> +#endif
>>
>> Adding a #define to ./include/configs/sun?i.h would be preferred, I
>> think.
>
> Sounds reasonable. I wonder what else (in other drivers) we should
> move over there.

Ian, include/configs/sun?i.h and sunxi-common.h only have config
related #defines. Are we sure this is the place for something
like register offsets?

For reference, drivers/i2c/mvtwsi.c has sunxi specific register
offsets wrapped in a #define in the file itself.


Cheers
ChenYu

[U-Boot] [PATCH 5/7] ARM: sunxi-mmc: Add mmc support for sun6i / A31

[Ian Campbell]

On Tue, 2014-09-23 at 19:50 +0800, Chen-Yu Tsai wrote:
> Ian, include/configs/sun?i.h and sunxi-common.h only have config
> related #defines. Are we sure this is the place for something
> like register offsets?

I guess not ;-)

> For reference, drivers/i2c/mvtwsi.c has sunxi specific register
> offsets wrapped in a #define in the file itself.

How about either ./arch/arm/include/asm/arch-sunxi/mmc.h or near the top
of this C file (i.e. outside the code itself)?

Ian.

[U-Boot] [PATCH 5/7] ARM: sunxi-mmc: Add mmc support for sun6i / A31

[Chen-Yu Tsai]

On Tue, Sep 23, 2014 at 7:54 PM, Ian Campbell <ijc@hellion.org.uk> wrote:
> On Tue, 2014-09-23 at 19:50 +0800, Chen-Yu Tsai wrote:
>> Ian, include/configs/sun?i.h and sunxi-common.h only have config
>> related #defines. Are we sure this is the place for something
>> like register offsets?
>
> I guess not ;-)
>
>> For reference, drivers/i2c/mvtwsi.c has sunxi specific register
>> offsets wrapped in a #define in the file itself.
>
> How about either ./arch/arm/include/asm/arch-sunxi/mmc.h or near the top
> of this C file (i.e. outside the code itself)?

Adding it to the register definitions in ./arch/arm/include/asm/arch-sunxi/mmc.h
seems like a good choice. The last bit of struct sunxi_mmc would be like:

        u32 idie;               /* 0x8c internal DMA interrupt enable */
        u32 chda;               /* 0x90 */
        u32 cbda;               /* 0x94 */
#if defined(CONFIG_SUN6I)
        u32 res1[126];
#else
        u32 res1[26];
#endif
        u32 fifo;               /* 0x100 (0x200 on sun6i) FIFO access address */
 };

And have

    mmchost->database = &mmchost->reg->fifo;

Or just get rid of ->database and use ->reg->fifo directly.
The latter seems better.


ChenYu

[U-Boot] [PATCH 5/7] ARM: sunxi-mmc: Add mmc support for sun6i / A31

[Ian Campbell]

On Tue, 2014-09-23 at 20:07 +0800, Chen-Yu Tsai wrote:
> On Tue, Sep 23, 2014 at 7:54 PM, Ian Campbell <ijc@hellion.org.uk> wrote:
> > On Tue, 2014-09-23 at 19:50 +0800, Chen-Yu Tsai wrote:
> >> Ian, include/configs/sun?i.h and sunxi-common.h only have config
> >> related #defines. Are we sure this is the place for something
> >> like register offsets?
> >
> > I guess not ;-)
> >
> >> For reference, drivers/i2c/mvtwsi.c has sunxi specific register
> >> offsets wrapped in a #define in the file itself.
> >
> > How about either ./arch/arm/include/asm/arch-sunxi/mmc.h or near the top
> > of this C file (i.e. outside the code itself)?
> 
> Adding it to the register definitions in ./arch/arm/include/asm/arch-sunxi/mmc.h
> seems like a good choice. The last bit of struct sunxi_mmc would be like:
> 
>         u32 idie;               /* 0x8c internal DMA interrupt enable */
>         u32 chda;               /* 0x90 */
>         u32 cbda;               /* 0x94 */
> #if defined(CONFIG_SUN6I)
>         u32 res1[126];
> #else
>         u32 res1[26];
> #endif
>         u32 fifo;               /* 0x100 (0x200 on sun6i) FIFO access address */
>  };
> 
> And have
> 
>     mmchost->database = &mmchost->reg->fifo;
> 
> Or just get rid of ->database and use ->reg->fifo directly.
> The latter seems better.

Yep, sounds good.

You could also consider just
#if defined(CONFIG_SUN6I)
         u32 res2[100];
#endif
after the existing res1.

[U-Boot] [PATCH 6/7] ARM: sun6i: Setup the A31 UART0 muxing

[Chen-Yu Tsai]

From: Maxime Ripard <maxime.ripard@free-electrons.com>

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens at csie.org: commit message was "ARM: sunxi: Setup the A31 UART0 muxing"]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/cpu/armv7/sunxi/board.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index f2cedbb..fc6aa4b 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -54,6 +54,10 @@ int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
 	sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), 2);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), 2);
+	sunxi_gpio_set_pull(SUNXI_GPH(21), 1);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
-- 
2.1.0

[U-Boot] [PATCH 6/7] ARM: sun6i: Setup the A31 UART0 muxing

[Ian Campbell]

On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
> From: Maxime Ripard <maxime.ripard@free-electrons.com>
> 
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> [wens at csie.org: commit message was "ARM: sunxi: Setup the A31 UART0 muxing"]
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Ian Campbell <ijc@hellion.org.uk>

[U-Boot] [PATCH 6/7] ARM: sun6i: Setup the A31 UART0 muxing

[Michael Trimarchi]

Hi

Il 08/set/2014 15:36 "Chen-Yu Tsai" <wens@csie.org> ha scritto:
>
> From: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> [wens at csie.org: commit message was "ARM: sunxi: Setup the A31 UART0
muxing"]
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  arch/arm/cpu/armv7/sunxi/board.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/sunxi/board.c
b/arch/arm/cpu/armv7/sunxi/board.c
> index f2cedbb..fc6aa4b 100644
> --- a/arch/arm/cpu/armv7/sunxi/board.c
> +++ b/arch/arm/cpu/armv7/sunxi/board.c
> @@ -54,6 +54,10 @@ int gpio_init(void)
>         sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
>         sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
>         sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
> +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I)
> +       sunxi_gpio_set_cfgpin(SUNXI_GPH(20), 2);
> +       sunxi_gpio_set_cfgpin(SUNXI_GPH(21), 2);
> +       sunxi_gpio_set_pull(SUNXI_GPH(21), 1);
>  #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
>         sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
>         sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
> --
> 2.1.0
>

I don't know if it is correct that every architecture has a specific
function to MUX, but can we define what is 2 2 and 1?

Michael

> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 6/7] ARM: sun6i: Setup the A31 UART0 muxing

[Chen-Yu Tsai]

On Mon, Sep 22, 2014 at 2:10 PM, Michael Trimarchi
<michael@amarulasolutions.com> wrote:
> Hi
>
> Il 08/set/2014 15:36 "Chen-Yu Tsai" <wens@csie.org> ha scritto:
>
>
>>
>> From: Maxime Ripard <maxime.ripard@free-electrons.com>
>>
>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>> [wens at csie.org: commit message was "ARM: sunxi: Setup the A31 UART0
>> muxing"]
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>>  arch/arm/cpu/armv7/sunxi/board.c | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/arm/cpu/armv7/sunxi/board.c
>> b/arch/arm/cpu/armv7/sunxi/board.c
>> index f2cedbb..fc6aa4b 100644
>> --- a/arch/arm/cpu/armv7/sunxi/board.c
>> +++ b/arch/arm/cpu/armv7/sunxi/board.c
>> @@ -54,6 +54,10 @@ int gpio_init(void)
>>         sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
>>         sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
>>         sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
>> +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I)
>> +       sunxi_gpio_set_cfgpin(SUNXI_GPH(20), 2);
>> +       sunxi_gpio_set_cfgpin(SUNXI_GPH(21), 2);
>> +       sunxi_gpio_set_pull(SUNXI_GPH(21), 1);
>>  #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
>>         sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
>>         sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
>> --
>> 2.1.0
>>
>
> I don't know if it is correct that every architecture has a specific
> function to MUX, but can we define what is 2 2 and 1?

Yes they do. I will add them in a patch before this one in v2,
and also a separate patch to clean up the existing sunxi_gpio_set_pull
calls.


ChenYu

[U-Boot] [PATCH 7/7] ARM: sunxi: Add basic A31 support

[Chen-Yu Tsai]

From: Maxime Ripard <maxime.ripard@free-electrons.com>

Add a new sun6i machine that doesn't do much for now.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens at csie.org: use SPDX labels, adapt to Kconfig system, drop ifdef
		around mmc and smp code, drop MACH_TYPE]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/Kconfig                    |  3 +++
 arch/arm/cpu/armv7/sunxi/cpu_info.c |  2 ++
 board/sunxi/Kconfig                 | 10 +++++++++-
 configs/Colombus_defconfig          |  4 ++++
 include/configs/sun6i.h             | 26 ++++++++++++++++++++++++++
 5 files changed, 44 insertions(+), 1 deletion(-)
 create mode 100644 configs/Colombus_defconfig
 create mode 100644 include/configs/sun6i.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 22f0f09..bfbe6f1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -439,6 +439,9 @@ config TARGET_SUN4I
 config TARGET_SUN5I
 	bool "Support sun5i"
 
+config TARGET_SUN6I
+	bool "Support sun6i"
+
 config TARGET_SUN7I
 	bool "Support sun7i"
 
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index 5cf35ac..40c4e13 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -23,6 +23,8 @@ int print_cpuinfo(void)
 	case 7: puts("CPU:   Allwinner A10s (SUN5I)\n"); break;
 	default: puts("CPU:   Allwinner A1X (SUN5I)\n");
 	}
+#elif defined CONFIG_SUN6I
+	puts("CPU:   Allwinner A31 (SUN6I)\n");
 #elif defined CONFIG_SUN7I
 	puts("CPU:   Allwinner A20 (SUN7I)\n");
 #else
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 7bdf958..c78750e 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -14,6 +14,14 @@ config SYS_CONFIG_NAME
 
 endif
 
+if TARGET_SUN6I
+
+config SYS_CONFIG_NAME
+	string
+	default "sun6i"
+
+endif
+
 if TARGET_SUN7I
 
 config SYS_CONFIG_NAME
@@ -22,7 +30,7 @@ config SYS_CONFIG_NAME
 
 endif
 
-if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN7I
+if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I
 
 config SYS_CPU
 	string
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
new file mode 100644
index 0000000..16800de
--- /dev/null
+++ b/configs/Colombus_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="COLOMBUS"
+CONFIG_ARM=y
+CONFIG_TARGET_SUN6I=y
+CONFIG_FDTFILE="sun6i-a31-colombus.dtb"
diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h
new file mode 100644
index 0000000..93a1d96
--- /dev/null
+++ b/include/configs/sun6i.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ * (C) Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * Configuration settings for the Allwinner A31 (sun6i) CPU
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A31 specific configuration
+ */
+#define CONFIG_SUN6I		/* sun6i SoC generation */
+
+#define CONFIG_SYS_PROMPT		"sun6i# "
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
-- 
2.1.0

[U-Boot] [PATCH 7/7] ARM: sunxi: Add basic A31 support

[Ian Campbell]

On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
> From: Maxime Ripard <maxime.ripard@free-electrons.com>
> 
> Add a new sun6i machine that doesn't do much for now.

Can you briefly outline here what it _does_ do, please.

The actual code looks ok to me. There is some possibility we might
consolidate some of these Kconfig options, or at least move them to the
sunxi Kconfig. We can cross the bridge when we come to it though.

Any links to some info about the Colombus? Is it the WITS development
kit which google found for me?

Ian.

[U-Boot] [PATCH 7/7] ARM: sunxi: Add basic A31 support

[Maxime Ripard]

Hi Ian,

On Sun, Sep 21, 2014 at 07:51:17PM +0100, Ian Campbell wrote:
> On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
> > From: Maxime Ripard <maxime.ripard@free-electrons.com>
> > 
> > Add a new sun6i machine that doesn't do much for now.
> 
> Can you briefly outline here what it _does_ do, please.

When I contributed this patch, it was only having the UART support,
but judging from the rest of the patches Chen-Yu sent, I guess it does
a bit more than that now, especially MMC.

> The actual code looks ok to me. There is some possibility we might
> consolidate some of these Kconfig options, or at least move them to the
> sunxi Kconfig. We can cross the bridge when we come to it though.
> 
> Any links to some info about the Colombus? Is it the WITS development
> kit which google found for me?

It is.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 819 bytes
Desc: Digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20140921/9486ea4e/attachment.pgp>

[U-Boot] [PATCH 7/7] ARM: sunxi: Add basic A31 support

[Chen-Yu Tsai]

On Mon, Sep 22, 2014 at 3:01 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi Ian,
>
> On Sun, Sep 21, 2014 at 07:51:17PM +0100, Ian Campbell wrote:
>> On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
>> > From: Maxime Ripard <maxime.ripard@free-electrons.com>
>> >
>> > Add a new sun6i machine that doesn't do much for now.
>>
>> Can you briefly outline here what it _does_ do, please.
>
> When I contributed this patch, it was only having the UART support,
> but judging from the rest of the patches Chen-Yu sent, I guess it does
> a bit more than that now, especially MMC.

Yeah. I'll rewrite the commit message.

>> The actual code looks ok to me. There is some possibility we might
>> consolidate some of these Kconfig options, or at least move them to the
>> sunxi Kconfig. We can cross the bridge when we come to it though.
>>
>> Any links to some info about the Colombus? Is it the WITS development
>> kit which google found for me?
>
> It is.

I'll split out the Colombus defconfig into a separate patch, like we
split machine support and board files for the kernel.


ChenYu

[U-Boot] [PATCH 0/7] ARM: sunxi: Add basic support for Allwinner A31 (sun6i)

[Hans de Goede]

Hi,

On 09/08/2014 03:28 PM, Chen-Yu Tsai wrote:
> Hi everyone,
> 
> This series add basic support for Allwinner's A31 SoC. The patches,
> excluding the first one, were cherry-picked from u-boot-sunxi. Due to
> the difference between u-boot mainline and u-boot-sunxi, some patches
> were rearranged or squashed to better fit the current state of u-boot,
> and not introduce any build breaks. It follows Ian's initial merge
> method of sun7i support: introducing various components first, then
> enabling them in the last commit. I tried to keep the commits separate,
> thus retaining the original author and Signed-off-bys.
> 
> Patch 1 adds a wrapper around "func(USB, usb, 0)" in BOOT_TARGET_DEVICES
> to deal with breakage when USB support is not enabled.
> 
> Patch 2 adds memory addresses for some hardware blocks new in sun6i.
> 
> Patch 3 adds support for the new PRCM (power reset and clock management)
> block, which also contains PLL bias voltage control.
> 
> Patch 4 adds support for the clock module. This patch is a bunch of
> different sun6i related patches on the clock code, from when sun6i
> support was introduced to u-boot-sunxi, up to its current form.
> This is done to avoid various conflicts and needlessly introducing
> then removing macros.
> 
> Patch 5 adds mmc support on sun6i.
> 
> Patch 6 adds uart0 muxing on sun6i.
> 
> Patch 7 enables sun6i support and adds defconfig for the Colombus board.

Chen,

Many thanks for working on this!

Just a quick not for people celebrating too early, this is the *incomplete*
sun7i support from the linux-sunxi/u-boot-sunxi git repo. It is fine to
merge this upstream, but this does not include SPL support.

This allows replacing u-boot.bin on allwinnner sd-card images, which is
very useful. But it does not get us all the way to booting sun7i devices
we still need boot0 and boot1 binaries from allwinner for that (for now).

Regards,

Hans

[U-Boot] [linux-sunxi] Re: [PATCH 0/7] ARM: sunxi: Add basic support for Allwinner A31 (sun6i)

[Siarhei Siamashka]

On Tue, 09 Sep 2014 09:00:57 +0200
Hans de Goede <hdegoede@redhat.com> wrote:

> Hi,
> 
> On 09/08/2014 03:28 PM, Chen-Yu Tsai wrote:
> > Hi everyone,
> > 
> > This series add basic support for Allwinner's A31 SoC. The patches,
> > excluding the first one, were cherry-picked from u-boot-sunxi. Due to
> > the difference between u-boot mainline and u-boot-sunxi, some patches
> > were rearranged or squashed to better fit the current state of u-boot,
> > and not introduce any build breaks. It follows Ian's initial merge
> > method of sun7i support: introducing various components first, then
> > enabling them in the last commit. I tried to keep the commits separate,
> > thus retaining the original author and Signed-off-bys.
> > 
> > Patch 1 adds a wrapper around "func(USB, usb, 0)" in BOOT_TARGET_DEVICES
> > to deal with breakage when USB support is not enabled.
> > 
> > Patch 2 adds memory addresses for some hardware blocks new in sun6i.
> > 
> > Patch 3 adds support for the new PRCM (power reset and clock management)
> > block, which also contains PLL bias voltage control.
> > 
> > Patch 4 adds support for the clock module. This patch is a bunch of
> > different sun6i related patches on the clock code, from when sun6i
> > support was introduced to u-boot-sunxi, up to its current form.
> > This is done to avoid various conflicts and needlessly introducing
> > then removing macros.
> > 
> > Patch 5 adds mmc support on sun6i.
> > 
> > Patch 6 adds uart0 muxing on sun6i.
> > 
> > Patch 7 enables sun6i support and adds defconfig for the Colombus board.
> 
> Chen,
> 
> Many thanks for working on this!
> 
> Just a quick not for people celebrating too early, this is the *incomplete*
> sun7i support from the linux-sunxi/u-boot-sunxi git repo. It is fine to
> merge this upstream, but this does not include SPL support.
> 
> This allows replacing u-boot.bin on allwinnner sd-card images, which is
> very useful. But it does not get us all the way to booting sun7i devices
> we still need boot0 and boot1 binaries from allwinner for that (for now).

If I understand it correctly, one of the things that needs to be done
in SPL is the initialization of the DRAM controller. A few weeks ago
Oliver has updated the http://linux-sunxi.org/DRAM_Controller page
and added a link to the 'dram_sun6i.c' file from the rhombus-tech.net
u-boot repository:
    http://git.rhombus-tech.net/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/sunxi/dram_sun6i.c;hb=refs/heads/allwinner-sunxi-a31
Does this repository look like exactly the missing part of code?
Assuming that this code works, it provides a usable starting point
for us.

It looks like the Allwinner A31 DRAM controller registers are very
similar to what is used in RK3288 (I have not checked the details,
but if we are very lucky, it might be even a 100% perfect match):
    https://chromium-review.googlesource.com/#/c/209419/
And thanks to the Rockchip developers (who are contributing this
DRAM controller support code to coreboot), now we have a lot of
named defines for the individual bitfields in the hardware
registers. So we can decode the magic constants used in the
Allwinner code. And thanks to Texas Instruments, we also have
some useful documentation, which also happens to be a reasonably
good match:
    http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf

In general, if we are on our own, then we just need to do all the
boring work again (similar to what we did with the Allwinner
A10/A13/A20 DRAM controller earlier). Starting with the creation of the
    http://linux-sunxi.org/A31_DRAM_Controller_Register_Guide
wiki page and populating it with the information gathered from the
Allwinner and Rockchip source code and also from the TI Keystone2
documentation. Naturally, every bit of this information needs to
be verified on real Allwinner A31 hardware before we can make any
assumptions.

However Allwinner has promised to provide us with some better
documentation later this month:
    https://www.mail-archive.com/linux-sunxi at googlegroups.com/msg06840.html
I don't know if they are going to include the documentation for the
DRAM controller in the first new documentation delivery. It surely
may be complicated, because Allwinner is obviously licensing the DRAM
controller IP from a third party and not designing it from scratch
(in a nice company with Rockchip and Texas Instruments). But Texas
Instruments somehow can provide the DRAM controller documentation
in free public access. So I would guess that it should be possible
for Allwinner too.

We still need proper Power-Down and Self-Refresh mode support for
Allwinner A10/A13/A20. And I had plans to do some investigation for
this stuff. But now this activity is temporarily suspended until
we see what kind of assistance Allwinner is going to provide to us
(A usable DRAM controller documentation? A contribution of DRAM
code for u-boot? Nothing?).

-- 
Best regards,
Siarhei Siamashka

[U-Boot] [linux-sunxi] Re: [PATCH 0/7] ARM: sunxi: Add basic support for Allwinner A31 (sun6i)

[Hans de Goede]

Hi,

On 09/18/2014 06:27 AM, Siarhei Siamashka wrote:
> On Tue, 09 Sep 2014 09:00:57 +0200
> Hans de Goede <hdegoede@redhat.com> wrote:
> 
>> Hi,
>>
>> On 09/08/2014 03:28 PM, Chen-Yu Tsai wrote:
>>> Hi everyone,
>>>
>>> This series add basic support for Allwinner's A31 SoC. The patches,
>>> excluding the first one, were cherry-picked from u-boot-sunxi. Due to
>>> the difference between u-boot mainline and u-boot-sunxi, some patches
>>> were rearranged or squashed to better fit the current state of u-boot,
>>> and not introduce any build breaks. It follows Ian's initial merge
>>> method of sun7i support: introducing various components first, then
>>> enabling them in the last commit. I tried to keep the commits separate,
>>> thus retaining the original author and Signed-off-bys.
>>>
>>> Patch 1 adds a wrapper around "func(USB, usb, 0)" in BOOT_TARGET_DEVICES
>>> to deal with breakage when USB support is not enabled.
>>>
>>> Patch 2 adds memory addresses for some hardware blocks new in sun6i.
>>>
>>> Patch 3 adds support for the new PRCM (power reset and clock management)
>>> block, which also contains PLL bias voltage control.
>>>
>>> Patch 4 adds support for the clock module. This patch is a bunch of
>>> different sun6i related patches on the clock code, from when sun6i
>>> support was introduced to u-boot-sunxi, up to its current form.
>>> This is done to avoid various conflicts and needlessly introducing
>>> then removing macros.
>>>
>>> Patch 5 adds mmc support on sun6i.
>>>
>>> Patch 6 adds uart0 muxing on sun6i.
>>>
>>> Patch 7 enables sun6i support and adds defconfig for the Colombus board.
>>
>> Chen,
>>
>> Many thanks for working on this!
>>
>> Just a quick not for people celebrating too early, this is the *incomplete*
>> sun7i support from the linux-sunxi/u-boot-sunxi git repo. It is fine to
>> merge this upstream, but this does not include SPL support.
>>
>> This allows replacing u-boot.bin on allwinnner sd-card images, which is
>> very useful. But it does not get us all the way to booting sun7i devices
>> we still need boot0 and boot1 binaries from allwinner for that (for now).
> 
> If I understand it correctly, one of the things that needs to be done
> in SPL is the initialization of the DRAM controller. A few weeks ago
> Oliver has updated the http://linux-sunxi.org/DRAM_Controller page
> and added a link to the 'dram_sun6i.c' file from the rhombus-tech.net
> u-boot repository:
>     http://git.rhombus-tech.net/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/sunxi/dram_sun6i.c;hb=refs/heads/allwinner-sunxi-a31
> Does this repository look like exactly the missing part of code?

Yes it does, interesting. I had found that file before, but this one
was missing in the repo I found then:

http://git.rhombus-tech.net/?p=u-boot.git;a=blob;f=arch/arm/include/asm/arch-sunxi/dram.h;hb=refs/heads/allwinner-sunxi-a31

But with that one added, this is definitely interesting.

> Assuming that this code works, it provides a usable starting point
> for us.

Yep, assuming :) If no one beats me to it I'll take a look at this as
time permits.

> It looks like the Allwinner A31 DRAM controller registers are very
> similar to what is used in RK3288 (I have not checked the details,
> but if we are very lucky, it might be even a 100% perfect match):
>     https://chromium-review.googlesource.com/#/c/209419/
> And thanks to the Rockchip developers (who are contributing this
> DRAM controller support code to coreboot), now we have a lot of
> named defines for the individual bitfields in the hardware
> registers. So we can decode the magic constants used in the
> Allwinner code. And thanks to Texas Instruments, we also have
> some useful documentation, which also happens to be a reasonably
> good match:
>     http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf

Sounds good / useful.

> In general, if we are on our own, then we just need to do all the
> boring work again (similar to what we did with the Allwinner
> A10/A13/A20 DRAM controller earlier). Starting with the creation of the
>     http://linux-sunxi.org/A31_DRAM_Controller_Register_Guide
> wiki page and populating it with the information gathered from the
> Allwinner and Rockchip source code and also from the TI Keystone2
> documentation. Naturally, every bit of this information needs to
> be verified on real Allwinner A31 hardware before we can make any
> assumptions.

Yep.

> However Allwinner has promised to provide us with some better
> documentation later this month:
>     https://www.mail-archive.com/linux-sunxi at googlegroups.com/msg06840.html
> I don't know if they are going to include the documentation for the
> DRAM controller in the first new documentation delivery. It surely
> may be complicated, because Allwinner is obviously licensing the DRAM
> controller IP from a third party and not designing it from scratch
> (in a nice company with Rockchip and Texas Instruments). But Texas
> Instruments somehow can provide the DRAM controller documentation
> in free public access. So I would guess that it should be possible
> for Allwinner too.
> 
> We still need proper Power-Down and Self-Refresh mode support for
> Allwinner A10/A13/A20. And I had plans to do some investigation for
> this stuff. But now this activity is temporarily suspended until
> we see what kind of assistance Allwinner is going to provide to us
> (A usable DRAM controller documentation? A contribution of DRAM
> code for u-boot? Nothing?).

Regards,

Hans

[U-Boot] [linux-sunxi] Re: [PATCH 0/7] ARM: sunxi: Add basic support for Allwinner A31 (sun6i)

[Chen-Yu Tsai]

Hi,

On Thu, Sep 18, 2014 at 4:31 PM, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi,
>
> On 09/18/2014 06:27 AM, Siarhei Siamashka wrote:
>> On Tue, 09 Sep 2014 09:00:57 +0200
>> Hans de Goede <hdegoede@redhat.com> wrote:
>>
>>> Hi,
>>>
>>> On 09/08/2014 03:28 PM, Chen-Yu Tsai wrote:
>>>> Hi everyone,
>>>>
>>>> This series add basic support for Allwinner's A31 SoC. The patches,
>>>> excluding the first one, were cherry-picked from u-boot-sunxi. Due to
>>>> the difference between u-boot mainline and u-boot-sunxi, some patches
>>>> were rearranged or squashed to better fit the current state of u-boot,
>>>> and not introduce any build breaks. It follows Ian's initial merge
>>>> method of sun7i support: introducing various components first, then
>>>> enabling them in the last commit. I tried to keep the commits separate,
>>>> thus retaining the original author and Signed-off-bys.
>>>>
>>>> Patch 1 adds a wrapper around "func(USB, usb, 0)" in BOOT_TARGET_DEVICES
>>>> to deal with breakage when USB support is not enabled.
>>>>
>>>> Patch 2 adds memory addresses for some hardware blocks new in sun6i.
>>>>
>>>> Patch 3 adds support for the new PRCM (power reset and clock management)
>>>> block, which also contains PLL bias voltage control.
>>>>
>>>> Patch 4 adds support for the clock module. This patch is a bunch of
>>>> different sun6i related patches on the clock code, from when sun6i
>>>> support was introduced to u-boot-sunxi, up to its current form.
>>>> This is done to avoid various conflicts and needlessly introducing
>>>> then removing macros.
>>>>
>>>> Patch 5 adds mmc support on sun6i.
>>>>
>>>> Patch 6 adds uart0 muxing on sun6i.
>>>>
>>>> Patch 7 enables sun6i support and adds defconfig for the Colombus board.
>>>
>>> Chen,
>>>
>>> Many thanks for working on this!
>>>
>>> Just a quick not for people celebrating too early, this is the *incomplete*
>>> sun7i support from the linux-sunxi/u-boot-sunxi git repo. It is fine to
>>> merge this upstream, but this does not include SPL support.
>>>
>>> This allows replacing u-boot.bin on allwinnner sd-card images, which is
>>> very useful. But it does not get us all the way to booting sun7i devices
>>> we still need boot0 and boot1 binaries from allwinner for that (for now).
>>
>> If I understand it correctly, one of the things that needs to be done
>> in SPL is the initialization of the DRAM controller. A few weeks ago
>> Oliver has updated the http://linux-sunxi.org/DRAM_Controller page
>> and added a link to the 'dram_sun6i.c' file from the rhombus-tech.net
>> u-boot repository:
>>     http://git.rhombus-tech.net/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/sunxi/dram_sun6i.c;hb=refs/heads/allwinner-sunxi-a31
>> Does this repository look like exactly the missing part of code?
>
> Yes it does, interesting. I had found that file before, but this one
> was missing in the repo I found then:
>
> http://git.rhombus-tech.net/?p=u-boot.git;a=blob;f=arch/arm/include/asm/arch-sunxi/dram.h;hb=refs/heads/allwinner-sunxi-a31
>
> But with that one added, this is definitely interesting.

The A31 Hummingbird's SDK has provided us with full boot0/boot1,
which also includes the dram code:

http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_v4.5_hummingbird_kfb_ok/lichee/boot-v1.0/boot/source/init_dram/

It is more complex than what we found in u-boot.
This code also shows what is encoded into the dram parameters
found in the fex files.

>> Assuming that this code works, it provides a usable starting point
>> for us.
>
> Yep, assuming :) If no one beats me to it I'll take a look at this as
> time permits.
>
>> It looks like the Allwinner A31 DRAM controller registers are very
>> similar to what is used in RK3288 (I have not checked the details,
>> but if we are very lucky, it might be even a 100% perfect match):
>>     https://chromium-review.googlesource.com/#/c/209419/
>> And thanks to the Rockchip developers (who are contributing this
>> DRAM controller support code to coreboot), now we have a lot of
>> named defines for the individual bitfields in the hardware
>> registers. So we can decode the magic constants used in the
>> Allwinner code. And thanks to Texas Instruments, we also have
>> some useful documentation, which also happens to be a reasonably
>> good match:
>>     http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf
>
> Sounds good / useful.
>
>> In general, if we are on our own, then we just need to do all the
>> boring work again (similar to what we did with the Allwinner
>> A10/A13/A20 DRAM controller earlier). Starting with the creation of the
>>     http://linux-sunxi.org/A31_DRAM_Controller_Register_Guide
>> wiki page and populating it with the information gathered from the
>> Allwinner and Rockchip source code and also from the TI Keystone2
>> documentation. Naturally, every bit of this information needs to
>> be verified on real Allwinner A31 hardware before we can make any
>> assumptions.
>
> Yep.

Matching the register bits with the parts decoded from dram
parameters seems like a place to start, though i don't understand
much of the terminology.

>> However Allwinner has promised to provide us with some better
>> documentation later this month:
>>     https://www.mail-archive.com/linux-sunxi at googlegroups.com/msg06840.html
>> I don't know if they are going to include the documentation for the
>> DRAM controller in the first new documentation delivery. It surely
>> may be complicated, because Allwinner is obviously licensing the DRAM
>> controller IP from a third party and not designing it from scratch
>> (in a nice company with Rockchip and Texas Instruments). But Texas
>> Instruments somehow can provide the DRAM controller documentation
>> in free public access. So I would guess that it should be possible
>> for Allwinner too.
>>
>> We still need proper Power-Down and Self-Refresh mode support for
>> Allwinner A10/A13/A20. And I had plans to do some investigation for
>> this stuff. But now this activity is temporarily suspended until
>> we see what kind of assistance Allwinner is going to provide to us
>> (A usable DRAM controller documentation? A contribution of DRAM
>> code for u-boot? Nothing?).

Cheers
ChenYu

[U-Boot] [linux-sunxi] Re: [PATCH 0/7] ARM: sunxi: Add basic support for Allwinner A31 (sun6i)

[Hans de Goede]

Hi,

On 09/18/2014 05:31 PM, Chen-Yu Tsai wrote:
> Hi,
> 
> On Thu, Sep 18, 2014 at 4:31 PM, Hans de Goede <hdegoede@redhat.com> wrote:
>> Hi,
>>
>> On 09/18/2014 06:27 AM, Siarhei Siamashka wrote:
>>> On Tue, 09 Sep 2014 09:00:57 +0200
>>> Hans de Goede <hdegoede@redhat.com> wrote:
>>>
>>>> Hi,
>>>>
>>>> On 09/08/2014 03:28 PM, Chen-Yu Tsai wrote:
>>>>> Hi everyone,
>>>>>
>>>>> This series add basic support for Allwinner's A31 SoC. The patches,
>>>>> excluding the first one, were cherry-picked from u-boot-sunxi. Due to
>>>>> the difference between u-boot mainline and u-boot-sunxi, some patches
>>>>> were rearranged or squashed to better fit the current state of u-boot,
>>>>> and not introduce any build breaks. It follows Ian's initial merge
>>>>> method of sun7i support: introducing various components first, then
>>>>> enabling them in the last commit. I tried to keep the commits separate,
>>>>> thus retaining the original author and Signed-off-bys.
>>>>>
>>>>> Patch 1 adds a wrapper around "func(USB, usb, 0)" in BOOT_TARGET_DEVICES
>>>>> to deal with breakage when USB support is not enabled.
>>>>>
>>>>> Patch 2 adds memory addresses for some hardware blocks new in sun6i.
>>>>>
>>>>> Patch 3 adds support for the new PRCM (power reset and clock management)
>>>>> block, which also contains PLL bias voltage control.
>>>>>
>>>>> Patch 4 adds support for the clock module. This patch is a bunch of
>>>>> different sun6i related patches on the clock code, from when sun6i
>>>>> support was introduced to u-boot-sunxi, up to its current form.
>>>>> This is done to avoid various conflicts and needlessly introducing
>>>>> then removing macros.
>>>>>
>>>>> Patch 5 adds mmc support on sun6i.
>>>>>
>>>>> Patch 6 adds uart0 muxing on sun6i.
>>>>>
>>>>> Patch 7 enables sun6i support and adds defconfig for the Colombus board.
>>>>
>>>> Chen,
>>>>
>>>> Many thanks for working on this!
>>>>
>>>> Just a quick not for people celebrating too early, this is the *incomplete*
>>>> sun7i support from the linux-sunxi/u-boot-sunxi git repo. It is fine to
>>>> merge this upstream, but this does not include SPL support.
>>>>
>>>> This allows replacing u-boot.bin on allwinnner sd-card images, which is
>>>> very useful. But it does not get us all the way to booting sun7i devices
>>>> we still need boot0 and boot1 binaries from allwinner for that (for now).
>>>
>>> If I understand it correctly, one of the things that needs to be done
>>> in SPL is the initialization of the DRAM controller. A few weeks ago
>>> Oliver has updated the http://linux-sunxi.org/DRAM_Controller page
>>> and added a link to the 'dram_sun6i.c' file from the rhombus-tech.net
>>> u-boot repository:
>>>     http://git.rhombus-tech.net/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/sunxi/dram_sun6i.c;hb=refs/heads/allwinner-sunxi-a31
>>> Does this repository look like exactly the missing part of code?
>>
>> Yes it does, interesting. I had found that file before, but this one
>> was missing in the repo I found then:
>>
>> http://git.rhombus-tech.net/?p=u-boot.git;a=blob;f=arch/arm/include/asm/arch-sunxi/dram.h;hb=refs/heads/allwinner-sunxi-a31
>>
>> But with that one added, this is definitely interesting.
> 
> The A31 Hummingbird's SDK has provided us with full boot0/boot1,
> which also includes the dram code:
> 
> http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_v4.5_hummingbird_kfb_ok/lichee/boot-v1.0/boot/source/init_dram/
> 
> It is more complex than what we found in u-boot.
> This code also shows what is encoded into the dram parameters
> found in the fex files.

Interesting, if I ever find the time I may look into adding what ever
is missing from the u-boot dram init code by looking at the algorithm
used in the boot0 code. But as said, that depends on me finding the
time ...  So if others want to work on this, please do.

Regards,

Hans