[U-Boot] [PATCH 1/4] Add snoop disable for slave port 0, port 1 and port 2

[U-Boot] [PATCH 1/4] Add snoop disable for slave port 0, port 1 and port 2

[Alison Wang]

From: Jason Jin <Jason.Jin@freescale.com>

Disable the snoop for slave interface 0, 1 and 2
to avoid the interleaving on the CCI400 BUS.

Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  1 +
 board/freescale/ls1021aqds/ls1021aqds.c           |  7 +++++++
 board/freescale/ls1021atwr/ls1021atwr.c           | 10 ++++++++++
 3 files changed, 18 insertions(+)

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 7995fe2..a1f4fdb 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -448,6 +448,7 @@ struct ccsr_ddr {
 
 #define CCI400_CTRLORD_TERM_BARRIER	0x00000008
 #define CCI400_CTRLORD_EN_BARRIER	0
+#define CCI400_SHAORD_NON_SHAREABLE	0x00000002
 
 /* CCI-400 registers */
 struct ccsr_cci400 {
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 12e83f7..e32dbeb 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -220,6 +220,13 @@ int board_init(void)
 	/* Set CCI-400 control override register to
 	 * enable barrier transaction */
 	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+	/*
+	 * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
+	 * All transactions are treated as non-shareable
+	 */
+	out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+	out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+	out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index b522ff2..811c911 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -272,6 +272,16 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+
+	/*
+	 * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
+	 * All transactions are treated as non-shareable
+	 */
+	out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+	out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+	out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
 #ifndef CONFIG_SYS_FSL_NO_SERDES
 	fsl_serdes_init();
 	config_serdes_mux();
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 2/4] arm: ls102xa: Remove bit reversing for SCFG registers

[Alison Wang]

SCFG_SCFGREVCR is SCFG bit reverse register. This register
must be written with 0xFFFFFFFF before writing to any other
SCFG register. Then other SCFG register could be written in
big-endian mode.

Address: 157_0000h base + 200h offset = 157_0200h
Bit   0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
W/R                                   SCFGREV
Reset 0 0 0 0 0 0 0 0 0 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
0-31
SCFGREV SCFG Bit Reverse Control Filed
32'h 0000_0000 - No bit reverse is applied
32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as 0:31

This patch removes the bit reversing for SCFG registers in
u-boot. It will be implemented through PBI commands in RCW
.pbi
write 0x570200, 0xffffffff
.end
So other SCFG register could be written in big-endian mode
in u-boot or kernel directly.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
---
 board/freescale/ls1021aqds/ls1021aqds.c | 2 --
 board/freescale/ls1021atwr/ls1021atwr.c | 5 -----
 2 files changed, 7 deletions(-)

diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index e32dbeb..56028f8 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -136,9 +136,7 @@ int board_early_init_f(void)
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 
 #ifdef CONFIG_TSEC_ENET
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
 	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
 #endif
 
 #ifdef CONFIG_FSL_IFC
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 811c911..ff7130e 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -250,11 +250,8 @@ int board_early_init_f(void)
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 
 #ifdef CONFIG_TSEC_ENET
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
 	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
-	udelay(10);
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
 #endif
 
 #ifdef CONFIG_FSL_IFC
@@ -262,9 +259,7 @@ int board_early_init_f(void)
 #endif
 
 #ifdef CONFIG_FSL_DCU_FB
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
 	out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
 #endif
 
 	return 0;
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 3/4] ls102xa: ifc: nor: fix the write issue when bytes unaligned.

[Alison Wang]

From: Yuan Yao <yao.yuan@freescale.com>

Add define CONFIG_SYS_WRITE_SWAPPED_DATA.
For LS1021AQDS and LS1021QTWR nor flash read and write should swap the
bytes when handle unaligned tail bytes.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
---
 include/configs/ls1021aqds.h | 1 +
 include/configs/ls1021atwr.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index bb47813..7e78e78 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -109,6 +109,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS	45
 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
 
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 45b2272..2427f2e 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -93,6 +93,7 @@
 #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }
 
 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
 
 /* CPLD */
 
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 4/4] arm: ls102xa: Add SystemID EEPROM support for LS1021ATWR board

[Alison Wang]

SystemID information could be read through I2C1 from EEPROM
on LS1021ATWR board.

As LS1 is a little-endian processor, getting the version ID by
be32_to_cpu() is wrong. Fix it by using e.version directly.
This change will be compatible for both ARM and PowerPC.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
---
 board/freescale/common/sys_eeprom.c | 4 ++--
 include/configs/ls1021atwr.h        | 9 +++++++++
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index 6144c53..3426b8a 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -90,7 +90,7 @@ static void show_eeprom(void)
 	/* EEPROM tag ID, either CCID or NXID */
 #ifdef CONFIG_SYS_I2C_EEPROM_NXID
 	printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
-		be32_to_cpu(e.version));
+	       e.version);
 #else
 	printf("ID: %c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
 #endif
@@ -485,7 +485,7 @@ int mac_read_from_eeprom(void)
 
 #ifdef CONFIG_SYS_I2C_EEPROM_NXID
 	printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
-		be32_to_cpu(e.version));
+	       e.version);
 #else
 	printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
 #endif
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 2427f2e..b02fda2 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -155,6 +155,15 @@
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		1
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+
 /*
  * MMC
  */
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 3/4] ls102xa: ifc: nor: fix the write issue when bytes unaligned.

[Prabhakar Kushwaha]

On 9/29/2014 8:23 AM, Alison Wang wrote:
> From: Yuan Yao <yao.yuan@freescale.com>
>
> Add define CONFIG_SYS_WRITE_SWAPPED_DATA.
> For LS1021AQDS and LS1021QTWR nor flash read and write should swap the
> bytes when handle unaligned tail bytes.
>
> Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
>

Subject and description of patch has mismatch.
Subject say it is for "write" but description say for both read & write.

Regards,
Prabhakar

[U-Boot] [PATCH 2/4] arm: ls102xa: Remove bit reversing for SCFG registers

[Prabhakar Kushwaha]

On 9/29/2014 8:23 AM, Alison Wang wrote:
> SCFG_SCFGREVCR is SCFG bit reverse register. This register
> must be written with 0xFFFFFFFF before writing to any other
> SCFG register. Then other SCFG register could be written in
> big-endian mode.
>
> Address: 157_0000h base + 200h offset = 157_0200h
> Bit   0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
> W/R                                   SCFGREV
> Reset 0 0 0 0 0 0 0 0 0 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
> 0-31
> SCFGREV SCFG Bit Reverse Control Filed
> 32'h 0000_0000 - No bit reverse is applied
> 32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as 0:31
>
> This patch removes the bit reversing for SCFG registers in
> u-boot. It will be implemented through PBI commands in RCW
> .pbi
> write 0x570200, 0xffffffff
> .end
> So other SCFG register could be written in big-endian mode
> in u-boot or kernel directly.

If I understand correctly, below patch removes both setting 0xffffffff 
and 0x00000000.
does re-setting of SCFG_SCFGREVCR not a requirement?

Just a suggestion:  if SCFG_SCFGREVCR_REV and SCFG_SCFGREVCR_NOREV not 
required, remove the defines also.

> Signed-off-by: Alison Wang <alison.wang@freescale.com>
> ---
>   board/freescale/ls1021aqds/ls1021aqds.c | 2 --
>   board/freescale/ls1021atwr/ls1021atwr.c | 5 -----
>   2 files changed, 7 deletions(-)
>
> diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
> index e32dbeb..56028f8 100644
> --- a/board/freescale/ls1021aqds/ls1021aqds.c
> +++ b/board/freescale/ls1021aqds/ls1021aqds.c
> @@ -136,9 +136,7 @@ int board_early_init_f(void)
>   	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
>   
>   #ifdef CONFIG_TSEC_ENET
> -	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
>   	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
> -	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
>   #endif
>   
>   #ifdef CONFIG_FSL_IFC
> diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
> index 811c911..ff7130e 100644
> --- a/board/freescale/ls1021atwr/ls1021atwr.c
> +++ b/board/freescale/ls1021atwr/ls1021atwr.c
> @@ -250,11 +250,8 @@ int board_early_init_f(void)
>   	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
>   
>   #ifdef CONFIG_TSEC_ENET
> -	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
>   	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
>   	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
> -	udelay(10);
> -	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
>   #endif
>   
>   #ifdef CONFIG_FSL_IFC
> @@ -262,9 +259,7 @@ int board_early_init_f(void)
>   #endif
>   
>   #ifdef CONFIG_FSL_DCU_FB
> -	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
>   	out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
> -	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
>   #endif
>   
>   	return 0;

[U-Boot] [PATCH 2/4] arm: ls102xa: Remove bit reversing for SCFG registers

[Huan Wang]

Hi, Prabhakar,

> On 9/29/2014 8:23 AM, Alison Wang wrote:
> > SCFG_SCFGREVCR is SCFG bit reverse register. This register must be
> > written with 0xFFFFFFFF before writing to any other SCFG register.
> > Then other SCFG register could be written in big-endian mode.
> >
> > Address: 157_0000h base + 200h offset = 157_0200h
> > Bit   0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23
> 24 25 26 27 28 29 30 31
> > W/R                                   SCFGREV
> > Reset 0 0 0 0 0 0 0 0 0 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
> 0
> > 0  0  0  0  0  0  0
> > 0-31
> > SCFGREV SCFG Bit Reverse Control Filed 32'h 0000_0000 - No bit
> reverse
> > is applied 32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be
> > stored/read as 0:31
> >
> > This patch removes the bit reversing for SCFG registers in u-boot. It
> > will be implemented through PBI commands in RCW .pbi write 0x570200,
> > 0xffffffff .end So other SCFG register could be written in big-endian
> > mode in u-boot or kernel directly.
> 
> If I understand correctly, below patch removes both setting 0xffffffff
> and 0x00000000.
> does re-setting of SCFG_SCFGREVCR not a requirement?
[Alison Wang] Re-setting is not required. It is preferred to remain the bits 
reversed for other SCFG Registers. 
> 
> Just a suggestion:  if SCFG_SCFGREVCR_REV and SCFG_SCFGREVCR_NOREV not
> required, remove the defines also.
[Alison Wang] ok.
> 
> > Signed-off-by: Alison Wang <alison.wang@freescale.com>
> > ---
> >   board/freescale/ls1021aqds/ls1021aqds.c | 2 --
> >   board/freescale/ls1021atwr/ls1021atwr.c | 5 -----
> >   2 files changed, 7 deletions(-)
> >
> > diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
> > b/board/freescale/ls1021aqds/ls1021aqds.c
> > index e32dbeb..56028f8 100644
> > --- a/board/freescale/ls1021aqds/ls1021aqds.c
> > +++ b/board/freescale/ls1021aqds/ls1021aqds.c
> > @@ -136,9 +136,7 @@ int board_early_init_f(void)
> >   	struct ccsr_cci400 *cci = (struct ccsr_cci400
> > *)CONFIG_SYS_CCI400_ADDR;
> >
> >   #ifdef CONFIG_TSEC_ENET
> > -	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
> >   	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
> > -	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
> >   #endif
> >
> >   #ifdef CONFIG_FSL_IFC
> > diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
> > b/board/freescale/ls1021atwr/ls1021atwr.c
> > index 811c911..ff7130e 100644
> > --- a/board/freescale/ls1021atwr/ls1021atwr.c
> > +++ b/board/freescale/ls1021atwr/ls1021atwr.c
> > @@ -250,11 +250,8 @@ int board_early_init_f(void)
> >   	struct ccsr_scfg *scfg = (struct ccsr_scfg
> > *)CONFIG_SYS_FSL_SCFG_ADDR;
> >
> >   #ifdef CONFIG_TSEC_ENET
> > -	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
> >   	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
> >   	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
> > -	udelay(10);
> > -	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
> >   #endif
> >
> >   #ifdef CONFIG_FSL_IFC
> > @@ -262,9 +259,7 @@ int board_early_init_f(void)
> >   #endif
> >
> >   #ifdef CONFIG_FSL_DCU_FB
> > -	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
> >   	out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
> > -	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
> >   #endif
> >
> >   	return 0;

Best Regards,
Alison Wang

[U-Boot] [PATCH 1/4] Add snoop disable for slave port 0, port 1 and port 2

[Albert ARIBAUD]

Hi Alison,

On Mon, 29 Sep 2014 10:53:11 +0800, Alison Wang <b18965@freescale.com>
wrote:

> From: Jason Jin <Jason.Jin@freescale.com>
> 
> Disable the snoop for slave interface 0, 1 and 2
> to avoid the interleaving on the CCI400 BUS.

Please be more specific: this patch specifically targets arch ls102xa
and some associated boards, but the subject/commit summary (and commit
message) does not mention that, making it look like a very generic
patch.

Amicalement,
-- 
Albert.

[U-Boot] [PATCH 1/4] Add snoop disable for slave port 0, port 1 and port 2

[Huan Wang]

Hi, Albert, 

> On Mon, 29 Sep 2014 10:53:11 +0800, Alison Wang <b18965@freescale.com>
> wrote:
> 
> > From: Jason Jin <Jason.Jin@freescale.com>
> >
> > Disable the snoop for slave interface 0, 1 and 2 to avoid the
> > interleaving on the CCI400 BUS.
> 
> Please be more specific: this patch specifically targets arch ls102xa
> and some associated boards, but the subject/commit summary (and commit
> message) does not mention that, making it look like a very generic
> patch.
> 
[Alison Wang] Yes, I will change it in v2. Thanks.


Best Regards,
Alison Wang