From mboxrd@z Thu Jan  1 00:00:00 1970
From: Prabhakar Kushwaha <prabhakar@freescale.com>
Date: Mon, 29 Sep 2014 09:07:16 +0530
Subject: [U-Boot] [PATCH 2/4] arm: ls102xa: Remove bit reversing for
 SCFG registers
In-Reply-To: <1411959194-48189-2-git-send-email-b18965@freescale.com>
References: <1411959194-48189-1-git-send-email-b18965@freescale.com>
	<1411959194-48189-2-git-send-email-b18965@freescale.com>
Message-ID: <5428D3EC.2060202@freescale.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

On 9/29/2014 8:23 AM, Alison Wang wrote:
> SCFG_SCFGREVCR is SCFG bit reverse register. This register
> must be written with 0xFFFFFFFF before writing to any other
> SCFG register. Then other SCFG register could be written in
> big-endian mode.
>
> Address: 157_0000h base + 200h offset = 157_0200h
> Bit   0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
> W/R                                   SCFGREV
> Reset 0 0 0 0 0 0 0 0 0 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
> 0-31
> SCFGREV SCFG Bit Reverse Control Filed
> 32'h 0000_0000 - No bit reverse is applied
> 32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as 0:31
>
> This patch removes the bit reversing for SCFG registers in
> u-boot. It will be implemented through PBI commands in RCW
> .pbi
> write 0x570200, 0xffffffff
> .end
> So other SCFG register could be written in big-endian mode
> in u-boot or kernel directly.

If I understand correctly, below patch removes both setting 0xffffffff 
and 0x00000000.
does re-setting of SCFG_SCFGREVCR not a requirement?

Just a suggestion:  if SCFG_SCFGREVCR_REV and SCFG_SCFGREVCR_NOREV not 
required, remove the defines also.

> Signed-off-by: Alison Wang <alison.wang@freescale.com>
> ---
>   board/freescale/ls1021aqds/ls1021aqds.c | 2 --
>   board/freescale/ls1021atwr/ls1021atwr.c | 5 -----
>   2 files changed, 7 deletions(-)
>
> diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
> index e32dbeb..56028f8 100644
> --- a/board/freescale/ls1021aqds/ls1021aqds.c
> +++ b/board/freescale/ls1021aqds/ls1021aqds.c
> @@ -136,9 +136,7 @@ int board_early_init_f(void)
>   	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
>   
>   #ifdef CONFIG_TSEC_ENET
> -	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
>   	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
> -	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
>   #endif
>   
>   #ifdef CONFIG_FSL_IFC
> diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
> index 811c911..ff7130e 100644
> --- a/board/freescale/ls1021atwr/ls1021atwr.c
> +++ b/board/freescale/ls1021atwr/ls1021atwr.c
> @@ -250,11 +250,8 @@ int board_early_init_f(void)
>   	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
>   
>   #ifdef CONFIG_TSEC_ENET
> -	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
>   	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
>   	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
> -	udelay(10);
> -	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
>   #endif
>   
>   #ifdef CONFIG_FSL_IFC
> @@ -262,9 +259,7 @@ int board_early_init_f(void)
>   #endif
>   
>   #ifdef CONFIG_FSL_DCU_FB
> -	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
>   	out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
> -	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
>   #endif
>   
>   	return 0;